Lecture 7. Possible Bipolar Amplifier Topologies

Transcription

1 Lecture 7 OUTLINE Bipolar mplifier Topologies (1) Common-Emitter mplifiers Reading: Chapter EE105 Spring 2008 Lecture 7, Slide 1 Prof. Wu, UC Berkeley Possible Bipolar mplifier Topologies Three possible ways to apply an input to an amplifier and three possible ways to sense its output. Howeer, in reality only three of six input/output combinations are useful. EE105 Spring 2008 Lecture 7, Slide 2 Prof. Wu, UC Berkeley EE105 Fall

2 Study of Common Emitter Topology nalysis of CE Core Inclusion of Early Effect Emitter Degeneration Inclusion of Early Effect CE Stage with Biasing EE105 Spring 2008 Lecture 7, Slide 3 Prof. Wu, UC Berkeley Common Emitter Topology EE105 Spring 2008 Lecture 7, Slide 4 Prof. Wu, UC Berkeley EE105 Fall

3 Small Signal of CE mplifier out in out gπ g RC g R m C m m in EE105 Spring 2008 Lecture 7, Slide 5 Prof. Wu, UC Berkeley Limitation on CE Voltage Gain ICRC VT VRC VT VCC V < V T BE Since g m can be written as I C /V T, the CE oltage gain can be written as the ratio of V RC and V T. V RC is the potential difference between V CC and V CE, and V CE cannot go below V BE in order for the transistor to be in actie region. EE105 Spring 2008 Lecture 7, Slide 6 Prof. Wu, UC Berkeley EE105 Fall

4 Tradeoff between Voltage Gain and Headroom EE105 Spring 2008 Lecture 7, Slide 7 Prof. Wu, UC Berkeley I/O Impedances of CE Stage R R R in rπ out C i i When measuring output impedance, the input port has to be grounded so that V in 0. EE105 Spring 2008 Lecture 7, Slide 8 Prof. Wu, UC Berkeley EE105 Fall

5 CE Stage Trade offs EE105 Spring 2008 Lecture 7, Slide 9 Prof. Wu, UC Berkeley Inclusion of Early Effect g m( R C r O) R R r out C O Early effect will lower the gain of the CE amplifier, as it appears in parallel with RC. EE105 Spring 2008 Lecture 7, Slide 10 Prof. Wu, UC Berkeley EE105 Fall

6 Intrinsic Gain g r V V T m O s R C goes to infinity, the oltage gain reaches the product of g m and r O, which represents the maximum oltage gain the amplifier can hae. The intrinsic gain is independent of the bias current. EE105 Spring 2008 Lecture 7, Slide 11 Prof. Wu, UC Berkeley Current Gain iout I iin β I CE nother parameter of the amplifier is the current gain, which is defined as the ratio of current deliered to the load to the current flowing into the input. For a CE stage, it is equal to β. EE105 Spring 2008 Lecture 7, Slide 12 Prof. Wu, UC Berkeley EE105 Fall

7 Emitter Degeneration By inserting a resistor in series with the emitter, we degenerate the CE stage. This topology will decrease the gain of the amplifier but improe other aspects, such as linearity, and input impedance. EE105 Spring 2008 Lecture 7, Slide 13 Prof. Wu, UC Berkeley Small Signal Model gmrc 1 + g R m E RC 1 + R g m E Interestingly, this gain is equal to the total load resistance to ground diided by 1/g m plus the total resistance placed in series with the emitter. EE105 Spring 2008 Lecture 7, Slide 14 Prof. Wu, UC Berkeley EE105 Fall

8 Emitter Degeneration Example I 1 g m1 R C + R The input impedance of Q 2 can be combined in parallel with R E to yield an equialent impedance that degenerates Q 1. EE105 Spring 2008 Lecture 7, Slide 15 Prof. Wu, UC Berkeley E r π 2 Emitter Degeneration Example II RC rπ RE gm 1 In this example, the input impedance of Q 2 can be combined in parallel with R C to yield an equialent collector impedance to ground. EE105 Spring 2008 Lecture 7, Slide 16 Prof. Wu, UC Berkeley EE105 Fall

9 Input Impedance of Degenerated CE Stage V r i + RE(1 + β ) i π Rin rπ + ( β + 1) R i With emitter degeneration, the input impedance is increased from r π to r π + (β+1)r E ; a desirable effect. EE105 Spring 2008 Lecture 7, Slide 17 Prof. Wu, UC Berkeley E Output Impedance of Degenerated CE Stage without Considering Early Effect V π 0 π + + g π R rπ π 0 Rout RC i in m E Emitter degeneration does not alter the output impedance in this case. (More on this later.) EE105 Spring 2008 Lecture 7, Slide 18 Prof. Wu, UC Berkeley EE105 Fall

10 Capacitor at Emitter t DC the capacitor is open and the current source biases the amplifier. For ac signals, the capacitor is short and the amplifier is degenerated by RE. EE105 Spring 2008 Lecture 7, Slide 19 Prof. Wu, UC Berkeley Example: Design CE Stage with Degeneration as a Black Box V in iout gm ( rπ + gm) RE iout gm Gm in 1 + gmre If g m R E is much greater than unity, G m is more linear. EE105 Spring 2008 Lecture 7, Slide 20 Prof. Wu, UC Berkeley EE105 Fall