Cbyp. RoutCS 2N7000. Chi-CS. Cs Cbyp. CS-CC figure 1: Two stage amplifier

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Julie Harrison
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1 Under construction: Let me know of any errors. Design tools for Two stage DC coupled CS CC amplifier Richard Cooper October The Two-stage amplifier will combine two amplifiers that we have already designed with some changes. We will start with the output requirement as before with the Common Collector CC as the output stage. The Common Source CS will be the input stage The Q-point for the CC will about the same as before. The base bias resistors Rb1, and Rb2 will not be use because MOSFET CS drain voltage will be the voltage supplied to the base of the BJT CC. Design the CC stage for maximum output voltage swing. Choose the voltage (Vs) on the CS stage MOSFET source between 2V and 3V. CS stage Vcc CC Stage Cbyp Cbyp Vin Rin Ri Cin Rg1 Rd 2N7000 RoutCS Chi-CS RbaseCC 2N2222 Riso Cout Vout 50 Rgen Rin2CS Vgen Rg2 Rs Cs Cbyp Re Chi-CC Rout Rload Cbyp = 0.1uF, 0.047uF, or 0.01uF CS-CC figure 1: Two stage amplifier Common Collector CC Amplifier Design Designing procedure of common collector BJT amplifier can be grouped into three systematic stages. First, we have to set the Q-point, which is the DC operating point. Since, no specification regarding the Q-point is mentioned in the design requirements; it leaves the designer enough freedom to choose the operating point as necessary for the application. However, remember that the specifications given in terms of input and output impedance, gain, Page 1 of 14

2 frequency response characteristics and peak output voltages are tight and ultimately restricts the Q-point in a narrow window. It is difficult to analytically derive this point without some intelligent guess and the following steps would work out for the given conditions. For common collector configuration, the circuit diagram is shown in CS_CCFig.1. The small signal equivalent model is provided in CC Fig.3. For this configuration, same steps are involved for the calculation of R E with few minor changes. CC Figure 2: CC BJT curve. CC Part 1: Measure the device parameters Step CC1.1: We need to estimate a Q-point to find an estimate for V CEsat, ro and β. For the design of the amplifier, the 3 parameter values required are V CEsat, r o and β. Derived from the transistor characteristics curve shown in CC Fig.2, one can set an approximate Q-point (V CE and I C) in the active region and measure ro and β. We will solve for V CE and estimate I C. Solve for V CE see below. For an estimated I C Q-point use I C 2.6 * I load this is not the solution to your design Q-point. We can use an estimated I C because ro and β will not very much with small changes in Q-point. Page 2 of 14

3 ro = ΔV CE / ΔI C the slope of a line thru the estimated Q-point. Use rocc = 4.5K β = ΔI C / ΔV CE measured around the estimated Q-point. Use β = 150 Plot the estimated Q-point (V CE, I C) on the BJT characteristics curve. From the curves CC Fig. 2 estimate V CEsat the point where the curve begins to flattens out V CEsat 0.2 Vdc CC Part 2: Find the Q-point Step CC2.1: Derive V E Q- point Iload = Vout / Rload Output signal voltage at emitter Vouteis higher. Because of Riso in series with Rload Voute = Vout + Iload *Riso We will start with V E(max) and V E(min). V CEsat = 0.2V V E(max) = Vcc V CEsat (Voute + 20%Voute) V E(min) = Vouet + 20%Voute V E = (V E(max) + V E(min)) / 2 Midpoint V E Q-point Step CC2.2: Now find the value of R E, I E, and I C Voute = Vout + Iload *Riso The DC equation: V E = R E I E The AC equation: Voute = i e ( R E r occ ( Riso + R Load ) Combined equation: Voute = V E (r occ (Riso + R Load) ) / (R E + (r occ (Riso + R Load))) Rearrange combined equation V R E = E (r V oute + 20%V occ (Riso + R L )) r occ (Riso + R L ) oute Calculate I E I E = V E / R E Calculate I C Ic = I E (β / (β + 1)) use β from data sheet β = 150 CC Part 3: Find Vb, and Vd Step CC3.1: Calculate V B and V D V B = V E + V BE Q - point values V B will be used as the V D Q-point voltage for the CS stage V D = V B Q-point CS stage Page 3 of 14

4 RoutCS VoutCS Ib Rπ E C NPN β Ib rocc Vout AC RinCC Rbase E Re Riso Rout Rload CC Figure 3: Small signal equivalent model for common collector model CC Part 4: Calculate RinCC, Rout Step CC4.1: Input Impedance of CC Use β from data sheet β = 150 Rπ = β vt / Ic and for Gain AvCC as small as possible so the VinCC will as large possible. Rbase = Rπ + (β + 1) ((rocc R E (Riso + Rload))) Impedance looking into CC BJT base. RinCC = Rbase RloadCS = RinCC The load on the CS stage will be the input impedance of CC stage Step CC4.2: CC output Impedance Moved to end of CS Step CC4.3: Calculation of AvCC Voltage Gain V oute = i b (β + 1) (R E rocc (Riso + Rload)) AC signal voltage at the emitter v out = v oute * (Rload / (Rload + Riso)) voltage divider Riso and Rload Page 4 of 14

5 AC signal voltage at input to CC stage v incc = v outcs V incc = Rπ i b + i b (β +1) (R E rocc (Riso + Rload)) V incc = i b (Rπ + (β+1) (R E rocc ( Riso + Rload)) AC signal voltage at input to the CC stage. AvCCe = v out / v incc = (β+ 1) i b (R E rocc (Riso+Rload) / i b (Rπ + (β+1) (R E rocc (Riso + Rload))) Canceling out i b AvCCe at emitter =(β + 1)(R E rocc (Riso + Rload) / (Rπ + (β+1)(r E rocc (Riso + Rload))) AvCC = ( AvCCe at emitter) (Rload / (Rload + Riso)) gain at load resistor Thus, the voltage gain should be close to 1. Hence, the output follows the input. So, the Common collector configuration is also known as Emitter follower. Step CC4.4: Calculation Ai Current Gain AiCC = AvCC (RinCC / Rload) Step CC4.5: Find AC VinCC AC signal v incc needed to check minimum and maximum range of V D Q-point v incc = v out / AvCC AC signal voltage v out is the peak output voltage required. Step CC4.6: Calculate the Minimum and Maximum V D Need Check that V B is between V D max and V Dmin Chose Vs between 2.0Vdc and 3.0Vdc. Vs Q-point We will add 20% to VinCC so the design is not on the edge of the solution. VinCC is the output voltage from CS stage required to drive the CC V D(max) = V DD - (VinCC + 20%VinCC) V D(min) = V S+V DS sat + (VinCC + 20%VinCC) Check V D(min) < V B < V D(max) DC voltage Bias point. If V B is not within CS V D range, we will need to adjust the CC Q-point. Page 5 of 14

6 Common source (CS) Designing procedure of common source MOSFET amplifier can be grouped into three systematic stages. First, we have to set the Q-point, which is the DC operating point. Since, no specification regarding the Q-point is mentioned in the design requirements, it leaves the designer enough freedom to choose the operating point as necessary for the application. However, remember that the specifications given in terms of input and output impedance, gain, frequency response characteristics and peak output voltages are fairly tight and ultimately restricts the Q-point in a narrow window. It is difficult to analytically derive this point without some intelligent guess and the following steps would work out for the given conditions. Common Source with Source Resistance Bypassed Configuration In this configuration, R S is completely bypassed. The circuit diagram with necessary variables is provided in CS Fig.1. Rsf = 0 Page 6 of 14

7 CS Figure 2: MOSFET characteristics, Example not your Q-point CS Part 1: Measure the device parameters For the design of the amplifier, the 4 parameter values required are Vds sat, V GS, r o and gm. Derived from the transistor characteristics curve shown in CS Fig.2, one can set an approximate Q-point (V DS and I D) in the active region and measure ro and gm. We will solve for V DS and estimate ID. Solve for V DS see below. Rin CC is the load seen by the CS amplifier. Where Vin CC is the AC signal required by the CC stage to produce the required Vout. VinCC = Vout / Av CC I loadcs = (Vout/Av CC ) / Rin CC Page 7 of 14

8 For an approximate I D Q-point use I D 2.2 * I loadcs this is not the solution to your design Q-point. We can use an approximate I D because ro and gm will not very much with small changes in Q- point. ro = ΔV DS / ΔI D the slope of a line thru Q-point use rocs = 8k to match LTspice gm = ΔI D / ΔV GS measured around Q-point use gm = to match LTspice Plot the estimated Q-point (V DS,I D) on the MOSFET characteristics curve. From the curves estimate V DSsat the point where the curve begins to flattens out (beyond the triode region) Vds sat 1 Vdc and V GS 2.0Vdc CS Part 2: Determine the Q-point. Start with your MOSFET and selecting 4 resistors. Step CS2.1: Choose V S Set V S = between 2V to 3V. Step CS2.2: Check the range of V D. Check range of V D selection will be able supply the required base voltage for the CC amp. We will add 20% to VinCC so the design is not on the edge of the solution. Where VinCC is the AC signal required by the CC stage to produce the required Vout. V D(max) = V DD - (VinCC + 20%VinCC) V D(min) = V S+V DS sat + (VinCC + 20%VinCC) V DS = V D V S Q-point Vds Step CS2.3: Calculate R D. Vd and VoutCS from VinCC (required input to CC) see above V D = V B Q-point Vd DC voltage VoutCS = VinCC AC signal voltage RloadCS = RinCC i Rbase = v incc / R base VinCC is AC input signal voltage to CC, i Rbase is the Iload for CS The DC equation: V DD V D = V RD= R D( I D + I B) The AC equation: VoutCS = (i d + i Rbase )( R D r ocs R incc ) Combined equation: VoutCS = V RD (r ocs R incc) / (Rc + (r ocs R incc)) V R D = DD V D (r V outcs + 20%V ocs R incc ) (r ocs R incc ) outcs Step CS2.4: Calculate I D. I RD = I D + I B = (V DD V D) / R D I D = I RD I B Thus, Q-point is (V DS,I D). Step CS2.5: Find V GS, and V G Plot the Q-point (V DS,I D) on the MOSFET characteristics curve. Page 8 of 14

9 Rin Rgen AC From the curves, find V GS. Use V GS = 2.0Vdc V G = V S + V GS Vin Ri Rin2 CS Vin2 Rg G + Vgs - NMOS D S gmvgs ro CS Rd Rout CS VoutCS RinCC RbaseCC CS Figure 3: Common Source Small Signal Equivalent Circuit CS Part 3: Determine CS bias resistors. Step CS3.1: Calculate R S. I S = I D R S = V S I S Step CS3.2: Calculate R g1, R g2. Set Rin to desired value V G = V S + V GS DC bias point Rin desired = RinW Rin2W = RinW Ri Rg1 = (Vdd / V G ) Rin2W Rg2 = Rg1 V G / (Vdd V G) Check Rin meets requierments Rin2 = Rg = Rg1 Rg2 Rin = Ri + Rin2 Page 9 of 14

10 CS Part 4: Voltage Gain of CS stage Step CS4.1: Voltage Gain of CS stage VoutCS = - gm v gs(rd rocs RinCC) Vin2 = v gs This is not the Q-point, v gs = AC input voltage to the gate. Vin = (Rin/Rin2) Vin2 AvCS = VoutCS / Vin = - gm v gs(rd rocs RinCC) / (Rin/Rin2) v gs Rearrange AvCS = - gm (Rin2/Rin) (Rd rocs RinCC) CS-CC Part 1: Calculating impedance and Gain Refer to the small signal equivalent of the circuit you have just built in CS-CC Fig. 4. The capacitor values will be calculated in the next step. We can calculate the following: Rgen AC Vin Rin Ri Rin2 CS Vin2 Rg G + Vgs - S D NMOS gmvgs ro CS VoutCS Rd Rout CS Ib B RinCC RbaseCC C Rπ E NPN β Ib Re rocc Riso Rout Vout Rload CS-CC Figure 4: Two stage Small Signal Equivalent Circuit Page 10 of 14

11 Step CS-CC1.1: Input Impedance: CS-CC CS stage Rin2CS = Rg = R g1 R g2 Rin = Rin2CS + Ri For R S completely bypassed CC stage RbaseCC = RπCC + (β + 1) ((rocc R E Rload)) Impedance looking into BJT base. RinCC = RbaseCC CS-CC input impedance Rin = Rin2CS + Ri Step CS-CC1.2: Output Impedance: CS-CC Step CS-CC4.2: Output Impedance of CC RemitterBase is the impedance looking in the BJT emitter to base. RoutCS = Rd rocs CS stage, Rs completely bypassed by Cs RemitterBase = (RπCC + RoutCS) / (β + 1) Look into the CC emitter, note we will see the RoutCS of the CS. Rout =Riso + ( R E rocc RemitterBase) output impedance of the CC stage. CS Stage RoutCS = Rd rocs CC stage Page 11 of 14

12 Referring to CC Fig.3, let us find Vout / VinCC which would be a key step in calculating Av. RemitterBase = (RπCC + RoutCS) / (β + 1) Impedance looking into the BJT emitter Rout = R E rocc RemitterBase CS-CC Output impedance Rout = Riso + (R E rocc RemitterBase) Step CS-CC1.3: Voltage Gain AvCS = - gm (Rin2/Rin) (Rd rocs RinCC) AvCC = (Rload /(Rload * Riso)) (β + 1) (R E rocc (Riso + Rload) / (Rπ + (β+1) (R E rocc (Riso + Rload)) AvCS-CC = v out / v in = AvCS * AvCC Step CS-CC1.4: Current Gain AiCS-CC = Iload / Iin = AiCS * AiCC = AvCS-CC (Rin /Rload) AiCS-CC = AvCS-CC (Rin /Rload) Frequency response of Two Stage CS CC amplifier CS-CC Part 2: Frequency response With the Q-point being set after the sequence of steps, we can go for the selection of capacitors and finally connect the signal generator at input and measure the output amplified waveform. Step CS-CC2.1: Set low frequency cutoff break points Select C incs, C outcc and C S which jointly would set the roll-off beyond the lower cut-off frequency. Set any low frequency cutoff (F L) within the range as your lower cut-off frequency range requirement. Three capacitors will introduce 3 poles in the transfer function of the system. Because we will set 3 pole at the same frequency we must use the Band Width Shrinkage factor. Page 12 of 14

13 BWshrinkage = 2 1 n 1 Where n is the number of poles for low frequency breakpoints at same frequency. Setting 3 frequencies equal, we get, n= 3 1 F CinCS = F Cout CC= F CS = F L Find the C for each breakpoint f Cin, f Cout, and f CE where n = 3. C = 1 2πf C (R seen by C) Where C is the capacitor that sets the breakpoint f C R is the Thevenin equivalent resistance seen by the capacitor. R Cin = Ri + Rgen + Rin2CS R Cs = Rs ( rocs + R D RbaseCC ) ( 1 / gm ) Step CS-CC2.2: Set high frequency cutoff break points In this case because ChiCS, and ChiCC are set to the same break point. We must use the band shrinkage factor with n = 2. We need only to find a two zeros at F h / bandshrinage = f chi = f ch2 to set the high frequency cutoff. Set FchiCS = FchiCC = Fh / ChiCS RoutCS = Rd rocs RinCC = Rbase = Rπ + (β + 1) ((rocc R E (Riso + Rload))) Impedance looking into CC BJT base. R seen by C hics R ChiCS = RoutCS RinCC C hics = 1 2πf Chi (R seen by C hics ) Page 13 of 14

14 ChiCC R seen by C hicc Looking into the CC emitter, note we will see the Rout of the CS. RemitterBase = (Rπ + RoutCS) / (β + 1) Rout = (R E rocc RemitterBase) + Riso looking in to the CC stage. R ChiCC = Rout Rload C hicc = 1 2πf Chi2 (R seen by C hicc ) The following table enlists the particular expressions. Rsig Rgen+Ri C in Rgen + Ri + Rin2CS Cout RLoad + RoutCC C S Rs ( rocs + (R D RinCC)) ( 1 / gm ) C hics C hicc RoutCS RinCC RoutCC Rload CS - CC Table 1: Resistance Seen By Capacitors Page 14 of 14

In a cascade configuration, the overall voltage and current gains are given by:

In a cascade configuration, the overall voltage and current gains are given by: ECE 3274 Two-Stage Amplifier Project 1. Objective The objective of this lab is to design and build a direct coupled two-stage amplifier, including a common-source gain stage and a common-collector buffer