Design of Monotonic Digitally Controlled Oscillator (DCO) for Wide Tuning Range

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1 Volume. No. 1, Iue No. 3, Sep Dec 013, ISSN: Deign of Monotonic Digitally Controlled Ocillator (DCO) for Wide Tuning Range Abhihek Tomar1, Rameh K. Pokharel, Haruichi Kanaya 3, and Keiji Yohida 4 1 G.B.Pant Univerity of Agriculture & Technology, Pantnagar, India-63145,3,4 Electronic Department, Kyuhu Univerity, Fukuoka, Japan Abhihek.tomar@gbpuat-tech.ac.in,pokharel@ed.kyuhu-u.ac.jp Abtract An analytical equation to make a trade off between tuning range and differential non-linearity (DNL) for a digitally controlled ocillator (DCO) i derived and baed on the equation, an optimization method to obtain monotonic behavior of DCO i propoed. To verify the approach, a 1 bit DCO i deigned, in 0.18 m CMOS technology. The deigned DCO ha achieved Differential Non-linearity of LSB without degrading other parameter. The DNL achieved i within the limit and deigned DCO how highly monotonic behavior over the entire tuning range from 3.1 GHz to 4.15 GHz (30% of the tuning range). The imulated phae noie i 135. dbc/hz (@ 4 MHz offet) at ocillation frequency of 3.6 GHz with 14. mw power conumption. Index Term Digitally Controlled Ocillator, Monotonic, Wide tuning range, Phae noie, 0.18 m CMOS. I. INTRODUCTION Recent trend of implementing digitally controlled RF circuit in deep ubmicron CMOS technology i very attractive, due to it improved frequency characteritic and high integral ability. Furthermore, limited voltage headroom that provide very teep and compreed linear range for analog circuit deign favor the digital aited approache in analog circuit [1]. Digitally controlled ocillator [DCO] []-[6] whoe output frequency i a function of digital controlled word (DCW), i alo an example of analog circuit implemented uing digital aited approache. In LC-DCO, DCW change t(e capacitance of varactor cel, "y witching between high and low level voltage to tune ocillation frequency. The varactor cell i implemented in capacitor array. Thi capacitor array i implemented in block uch a block for compenation for proce, voltage, and temperature (PVT) variation, coare tuning block (CTB), fine tuning block (FTB), tracking bank etc for tuning. DCO ame a voltage controlled ocillator (VCO) are deigned for different wirele tandard ame which have many trict requirement uch a phae noie, wide tuning range, linearity and o on. Beide thee DCO ha other Parameter characteritic like tep ize, monotonic behavior to be full fill. Thee Digital characteritic are important during locking of all-digital phae locked loop (ADPLL) ued a local ocillator (LO) in wirele tranceiver. In locking proce, ADPLL firt capture and then lock with the RF frequency, o the output frequency mut be linear and monotonic for Smooth locking with the DCW generated by the digital phae frequency detector. Thi i very important parameter of the DCO which ha not been given much attention in DCO deign reported o far []-[6]. DCO [] i implemented in ring topology which ha poor phae noie and high power conumption with low operating frequency o it i not uitable for high frequency wirele communication application. DCO [3]-[6], implemented in LC topology have capabilitie to operate at GHz with good phae noie performance but have narrow tuning range. Therefore, variable capacitor bank i ued to obtain higher tuning range in the deign of a DCO. To achieve fine tuning frequency tep, capacitor array i implemented uing multiple block [3][5] and imultaneou witching i not allowed. Thi may improve the linearity but ued many digital input which increae varactor area and interconnect paraitic capacitance. Mot of the above mentioned DCO were concerned about frequency tuning tep and le concerned about linearity. No analytical approache have been reported o far to trade-off between DNL, tuning range and mimatch in capacitive array for optimization of the DCO deign which can provide a ytematic approach in the election between the number of varactor array and coding cheme i.e. binary weighted coding, thermometer coding or egmented coding to implement the varactor cell in the array. In thi paper we have analyzed nonlinearity of a DCO uing nonlinear mathematical equation, mimatch among the tuning element and ytematic and graded error and derived an analytical equation which provide a ytematic approach to deign monotonic DCO for large tuning range and limited permiible DNL. Baed on the above model, 1 bit DCO 8

2 Volume. No. 1, Iue No. 3, Sep Dec 013, ISSN: wa deigned in 0.18 m CMOS technology to check the mathematical concept.. Non-linearity Conideration in DCO Deign.1 Baic In a conventional cro-coupled LC-ocillator [7][8] the ocillating frequency i decided by the parallel reonance of LC tank. Frequency tuning can be achieved by either varying the inductance (L) or the capacitance(c). However, capacitor i varied to achieve fine tuning tep, wide tuning range and le chip area. In Fig.1. equivalent circuit of a functional LC-DCO i hown. The DCO conit of an inductor L, varactor array implemented by a parallel combination N varactor cell and a negative reitance (-R) MOS pair. The negative reitance i ued to compenate the loe of the capacitor and the inductor and implemented by cro-coupled MOS pair. The ocillating frequency (f) of binary weighted N-bit DCO i given by Equation (1) 1 f (1) N 1 L ( C P C ) k0 k where, C = ( C d C ) () k 0 k LSB Where N i the number of control bit, C P i the paraitic capacitance which include the capacitance of inductance, cro-coupled tranitor capacitance, driver capacitance and all interconnection capacitance etc., L i the total inductance. In Eqn. () capacitor (C k ) conit of low tate and high tate capacitance of K th bit. d k repreent digital tatu of K th digital control bit and C LSB i the effective witchable capacitance of LSB and decide tuning tep. Digital control bit (d k ) are inverted to repreent high capacitance value for low digital tate and vice vera. Thi lock ocillation frequency with digital code.. Non-Linearity and Tuning Range In a conventional VCO, gain i meaured by Kvco = (F)/(V) where F i the change in frequency due to the change in the control voltage (V). If the tranfer curve i traight, that how the high linearity and for monotonic function the lope of the line hould not be negative even when (V) tend to zero. But in cae of DCO, the tranfer characteritic i not continuou rather it i dicrete. Therefore gain i the change in ocillating frequency for LSB witching. So linearity for DCO i expreed in term of DNL. If the ratio of maximum tep (ΔF max ) and minimum tep (ΔF min ) to average tep (ΔF Ideal ) i le than 1.5 and greater than 0.5 repectively, the DCO i aumed to be linear and monotonic. The minimum tep ize of DCO with witching of LSB i calculated uing Equation (1). Since the witching capacitance of LSB ( C LSB ) i very mall a compared to the total k capacitance, the tep ize can be eaily approximated Taylor equation in Equation (1) and i given in Equation (3). 3 F F L ( ) (3) C LSB Where F, F and L are frequency tep ize, center frequency and inductance, repectively. Equation (3) ha not included the effect due to mimatch variation among the varactor cell. Frequency tep ize i calculated for n th code (ΔF n ) with mimatch variation in Equation (4). 3 F ( F F ) L C (1 T ( C)) (4) n n1 n1 Here, F n-1 and ΔF n-1 are ocillating frequency and frequency tep for (n-1) th digital control code. ( C) repreent tandard deviation for variation in witching capacitance. T i a contant which decide permiible variation for required yield. Equation (4) how that the frequency tep depend on center frequency and mimatch for equal witching capacitance. Conider a DCO with tuning frequency from F 1 to F. The minimum and maximum tep ize can be obtained on the lowet frequency (F 1 ) and highet frequency (F) when witching capacitance have minimum and maximum value due to maximum variation and given by Equation (5) and (6), repectively. Ideal tep i derived by replacing F from Equation (7) to Equation (3). F F min max LSB 3 F L ( C (1 T ( C))) (5) 1 LSB 3 F L ( C (1 T ( C))) (6) LSB F = F F 1 (7) So for DNL 0.5 LSB, maximum tep ize and minimum tep ize ratio with ideal tep ize hould be le than 1.5 and greater than 0.5, repectively. Thi i given by Equation (8) and (9). Equation (10) define the tuning range (TR %) in term of minimum (F1) and maximum (F) frequency. F F max Ideal F = F (1 T ( C)) 1.5 (8) Fmin F1 = (1 T ( C)) 0.5 (9) FIdeal F F F1 TR (%) = 100 (10) F 9

3 Volume. No. 1, Iue No. 3, Sep Dec 013, ISSN: % Mimatch in Capacitance % Tuning Range Low frequency High frequency Fig.1. Optimization curve between tuning range and mimatch capacitance for DNL=0.5 LSB. To take the effect of nonlinear mathematical equation on frequency tep, a graph, hown in Fig.. i plotted uing Equation (8), (9) and (10) between TR (%) and permiible capacitance mimatch (%).Thi graph can be ued for any center frequency. For example if tuning range i 10%, then permiible variation in capacitance i 8% whatever be the center frequency. The two line in Fig. how the permiible variation in capacitance for minimum frequency and maximum frequency. Since the frequency tep at higher frequency i alway greater than lower frequency, the permiible capacitance mimatch will alo be higher. So, only higher frequency curve i ufficient to calculate variation in capacitance. 3. Deign of 1 bit DCO 3.1 DCO Core The propoed tructure of LC-DCO i hown in Fig.3. The center tap on chip inductor (L) in parallel with capacitor bank make parallel reonance. Two cro-coupled NMOS tranitor M1 and M provide the neceary gain to compenate lo in the reonator and to utain ocillation. 1 bit Capacitor bank i ued for required tuning range. Thi i implemented by two part. Firt part ha -bit MIM capacitor in erie with NMOS tranitor for coare tuning. Second, i implemented by PMOS pair for fine tuning tep. DCO i deigned to reduce the performance degradation and to achieve good DNL. The center tap differential inductance provided by 0.18 m TSMC 1P6M CMOS proce with 3 turn i ued to get high quality factor (Q-factor) with ymmetrical tructure and better coupling coefficient [9]. High Q-factor inductance reduce LC tank lo and improve phae noie performance. Alo, the Q-factor of capacitor i improved by reducing the paraitic. Simulation i performed to trade off between phae noie and tuning range. The maximum tuning range without degrading the phae noie i approximately 30% at 3.6 GHz center frequency. Thi i the coare tuning range (CTR). Fig. how that if the tuning range i more than 6% then the permiible variation in mimatch among the varactor cell i zero which i practically impoible to achieve. So, thi CTR i divided in four part implemented with -bit which ha 10% tuning range for one part with 8% permiible variation in capacitance. Thi CTR i large and i achieved by the large witching capacitance device. Metal inulator metal (MIM) capacitor in erie with NMOS tranitor implemented in binary weighted coding are uitable candidate. The important parameter here i that the witching capacitance of FTB hould be greater than witching capacitance of CTB for it any digital code. Pleae note that in thi deign we fixed the mallet frequency tuning tep to be 0.4 MHz to prove the propoed optimization method. So, if the frequency tuning tep i 0.4 MHz, the number of required digital bit for given FTR i decided by tep ize. Therefore, for FTR of 300 MHz, 10 bit are ufficient when frequency tep i 0.4 MHz. Out 0 Out 180 Fig.. Detail of MIM capacitor implementation in propoed DCO. Thi 10 bit varactor array i implemented with egmented architecture. PMOS tranitor are ued a varactor. Varactor ize i decided for 0.4 MHz frequency tep at the central frequency of 3.6 GHz. Thi i optimized for large tuning range, by electing the higher value of C max /C min with minimum area. The dimenion of PMOS for the varactor i W=0 nm and L=500 nm for LSB. Monte-Carlo imulation i performed to calculate the mimatch variation for the identical cell. Standard deviation value i 1.46% of the nominal value. For a 99.5% yield, the value of T i.871. So, permiible variation in capacitance for LSB i 4.%. The permiible capacitance variation i equally divided between graded error and mimatch. So, mimatch i limited to be 14%. The number of binary bit and thermometer bit for required DNL i determined to be and 8, repectively [9]. The 8 bit thermometer decoded cell are implemented in 16 by 16 matrixe. -bit binary weighted cell are placed at the center of matrix. Identical varactor cell are made by connecting 4 PMOS pair in parallel for binary weighted and thermometer decoded varactor cell to improve matching in FTB. One and two pair of PMOS are electrically connected for lower order binary bit. 30

4 Volume. No. 1, Iue No. 3, Sep Dec 013, ISSN: Digital Circuit 10 bit FTB i implemented with 8 bit thermometer decoding and bit binary weighted varactor cell. The digital circuit are ued to implement propoed logic decoder. Thi decoder decreae the area of varactor array and paraitic at chematic a well a at layout level. The row, column and local decoder are implemented with minimum ize logic gate. The decoding cheme i demontrated here for 4 bit. bit (D3-D) are row bit and bit (D1-D0) are column bit. In the propoed cheme, the row decoder and column decoder take binary weighted input ignal and generate the ignal a hown in table I(A) & I(B). Then, thee line (R1-R4 and C1- C4) are routed in the varactor array and fed to local decoder adjacent to varactor cell. Local decoder generate appropriate ignal to varactor cell. The local decoder chematic for even and odd row are hown in Fig.5. TABLE I (A): TRUTH TABLE OF ROW DECODER INPUT ignal OUTPUT ignal D3 D R1 R R3 R TABLE I (B): TRUTH TABLE OF COLUMN DECODER ON ON and OFF, repectively 1 1 X OFF Pleae note, that witched ON and OFF mean i that output capacitance of varactor cell i LOW and HIGH, repectively. Here again we defined the three tate of row ON, ACTIVE, OFF. Row # ON, OFF and ACTIVE ignifie that all varactor in row # are ON, OFF and tatu depend on column ignal. For odd and even row of tatu ACTIVE varactor cell will be ON if column ignal i high or low, repectively. The main advantage of thi cheme i that 1. It reduce the number of ignal line to 3 for 16 by 16 matrix a compared to 48 in [4].. Conventional decoder can be implemented by 3 line, but every line need to be vertically routed for 16 local decoder to the adjacent row which i equivalent to 48. Alo, additional pace i required to iolate thee line with column and RF ignal line. But in propoed logic no row line need not to be vertically routed. INPUT ignal OUTPUT ignal D D1 D0 C1 C C3 C (a) Schematic of odd row of local decoder and varactor cell in varactor array. R N R N+1 C Varactor cell in R N and R N+1 row are 0 0 X ON OFF ON and OFF repectively Fig.3. Layout of varactor array for bit by bit. 31

5 Volume. No. 1, Iue No. 3, Sep Dec 013, ISSN: Layout Conideration The propoed decoder require only 3 digital ignal interconnect line a compare to 48 in [4]. Thee ignal line run parallel in layout o they mut have ome minimum ditance to reduce the paraitic capacitance and to avoid witching diturbance. Thi pace hould be further increaed if digital ignal line run parallel with RF ignal line. In [4] 3 digital ignal line with 16 RF line run in 16 row. Thi mean in each row two ignal andone RF line. To iolate RF ignal line with digital ignal at leat time pace i required o for 16 line thi come to be 3 which i ignificant. In our layout, digital and RF ignal line run in eparate row and eparated by digital block. Digital ignal line run in odd row and RF ignal in even row. In Fig. 6. layout i demontrated for 4 control bit. Higher order bit are converted into 4 digital ignal (R1-R4) and lower order bit into 4 digital ignal (C1-C4) by row and column decoder, repectively a per the propoed logic.rf1 and Rf are varactor output line. The layout i made to reduce the area and paraitic. 4. SIMULATION RESULT OF DCO The DCO wa deigned in 0.18 m CMOS technology to tet the propoed optimization technique for DNL, capacitive mimatch and tuning range. The propoed DCO layout i deigned uing cadence layout tool. Fig. 7 how the imulated tuning range of the DCO. Tuning range i meaured by fixing CTW and varying FTW from 0 to 103. Fine tuning code i plotted on X-axi. The tuning curve how four line for CTW00, 01, 10 and 11. The DCO operate between GHz at CTW= (00), GHz at CTW= (01), GHz at CTW= (10), and GHz at CTW= (11) and the imulated data curve how highly monotonic behavior. DCO Frequency [MHz] Fine Code CTW 11 CTW 10 CTW 01 CTW 00 Fig.4.Simulated tuning range for CTW= (00), CTW (01), CTW (10) and CTW (11). Phae Noie [dbc/hz] e+3 1e+4 1e+5 1e+6 1e+7 Frequency Offet [Hz] Fig.5. Simulated phae noie of propoed DCO. f oc=3.8 GHz, CTW= (11). The imulated phae noie pectrum i hown in Fig. 8 where the phae noie i dbc/hz at 4 MHz offet from the center frequency of 3.8 GHz. Fig. 9 how the DNL for the 10 bit FTW. The meaured DNL i LSB which i le than 0.5 LSB reported in [4] which how that propoed optimization technique i not followed. The meaured DNL i not high, rather it i a expected ince DNL have contribution of LSB and LSB due to nonlinear mathematical equation and mimatch among varactor cell and ret of the value i added due to variou gradient. The power diipation of the propoed ocillator i 19.8 mw. DC O Tech. [nm] TABLE II DCO PERFORMANCES COMPARISON TR [%] DNL [LSB] Phae Noie [dbc/hz] [3] 130 0% - -11@ 0.5MHz [4] 65 10% @ 1MHz [5] 130 6% @ 1MHz Thi % Power [mw] FOM [dbc/hz] DCO CTB CTS FTB DCO FTS [MHz] [LSB] Size [khz] [mm ] [3] [4] [5] Thi In Table II, the overall performance of the propoed DCO i compared with other publihed DCO where figure of merit (FOM) i comparable or lightly better than other DCO but the main advantage of thi DCO i the good linearity and highly monotonic behavior compared to other. A widely

6 Volume. No. 1, Iue No. 3, Sep Dec 013, ISSN: known equation (11) [11] i ued to compute figure of merit (FOM) of the DCO and compared the reult in Table II. f 0 PDC FOM L f 0log 10log (11) f 1mW Here, L{f} i the meaured phae noie at offet frequency {f} from the carrier frequency f 0. P DC i VCO power conumption in mw. The meaured FOM i 18dBc/Hz at 3.8 GHz frequency 5. Concluion A 1 bit DCO i deigned employing the propoed mathematical model for optimization of DNL and tuning range for a given frequency tuning tep. DNL i within the limit and highly monotonic frequency tuning curve i achieved with 1 bit digital control code. Varactor array i implemented i implemented uing new decoding cheme which reduce the area about 40% propoed which ignificantly reduce the paraitic. The tuning range of the propoed DCO i very cloe to 30% which i the theoretical limit of a LC-ocillator without uing any frequency tuning extenion circuit under the deign limit of DNL. Thi monotonic behavior of the DCO will eae the deign of an alldigital phae locked loop for wirele tranceiver, which will be taken a one of the mot important future work. Reference [1] A. Matuzawa, "Digital-centric RF CMOS technologie", IEICE Tran. Electron., vol. E91-C, no. 11, pp , Nov [] B. Fah, W. Y. Ali-Ahmad, and P. Gamand, A two-tage ring ocillator in 0.13-um CMOS for UWB impule radio, IEEE Microwave Theory and Technique, vol. 57, no. 5, pp , May 009. [3] R.B.Stazewki, et al, A firt multigigahertz digitally controlled ocillator for wirele application, IEEE Tran. on Microwave Theory and Technique (MTT), vol. 51, no.11, pp , Nov [4] N. Da Dalt, C. Kropf, M. Burian, T. Hartig, H. Eul, A 10b 10 GHz digitally controlled LC ocillator in 65 nm CMOS, in IEEE Int. Solid- State Circuit Conf. Dig. Tech. Paper, 006, pp [5] T. Pittorino, Y. Chen, V. Neubauer, T. Mayer, and L. Maurer, A UMTS-compliant fully digitally controlled ocillator with 100 MHz fine-tuning range in 0.13 um CMOS in IEEE Int. Solid-State Circuit Conf. Dig. Tech. Paper, 006, pp [6] R.K. Pokharel, K. Uchida, A. Tomar, H. Kanaya, and K. Yohida, Low phae noie 18 khz frequency tuning Step 5 GHz DCO uing tiny capacitor baed on tranmiion line, IEEE 10 th Topical Meeting on Silicon Monolithic Integrated Circuit in RF Sytem, New Orlean, USA, January, 010, pp [7] L. Dai and R. Harjani, Deign of high-performance CMOS voltage controlled ocillator, Kluwer Academic Publiher, 003. [8] A. Hajimiri and T. H. Lee, The deign of low noie ocillator, Kluwer Academic Publiher, 004. [9] M.Tibeout, Low power low phae noie differentially tuned quadrature VCO deign in tandard CMOS, IEEE Journal of Solid-State Circuit, vol. 36, no.7, pp , July 001 [10] A. Van den Boch et al, A 10-bit 1-GS/ Nyquit current teering CMOS D/A converter, IEEE Journal of Solid-State Circuit, vol. 36, no.3, pp , March 001. [11] N.Fong, J.Plouchart, N.Zamdmer, D.Liu, L.Waggner, C.Plett, and N.tarr, Deign of wide-band CMOS VCO for multiband wirele LAN application, IEEE Journal of Solid-State Circuit, vol. 38, no.8, pp , Aug