ABSTRACT. In this dissertation, we propose a novel technique for the voltage-mode control of switchedmode

Transcription

1 ABSTRACT BAWA, GAURAV. Switched-Capacitor Filter Baed Type-III Compenation for Voltage- Mode Control of Switched-Mode Buck Converter. (Under the direction of Dr. Alex Q. Huang). In thi diertation, we propoe a novel technique for the voltage-mode control of witchedmode fixed-frequency Buck Converter uing Switched-Capacitor Filter (SCF). The alient feature of the analog ampled-data Type-III filter embodiment (uing SCF) i a monolithic olution, automatic calability of the filter tranfer function w.r.t. the Buck Converter witching frequency, and moderate on-chip area and power conumption. While the propoed technique i aimed to explore a new deign-pace, it wa oberved that it can potentially combine the performance benefit of the conventional all-analog (power efficiency) and alldigital implementation (integration and programmability) of the Type-III compenation. In our prototype, the propoed Type-III SCF-baed voltage-mode controller Integrated Circuit (IC) i implemented in Texa Intrument 0.36-µm BCD (Bipolar-CMOS- DMOS) technology. The IC i configured to control the Buck Converter for two programmable witching frequencie of 500 KHz and MHz. The IC conume. ma of tatic current from a 3.3 V power upply, and ha an active-area of ~ 0.65 mm 2. The theoretical foundation have been validated by performing cloed-loop load tranient repone and open-loop frequency repone experiment; while operating the controller IC in cloed-loop configuration with a Buck converter power tage.

2 Copyright 203 by Gaurav Bawa All Right Reerved

3 Switched-Capacitor Filter Baed Type-III Compenation for Voltage-Mode Control of Switched-Mode Buck Converter by Gaurav Bawa A diertation ubmitted to the Graduate Faculty of North Carolina State Univerity in partial fulfillment of the requirement for the degree of Doctor of Philoophy Electrical Engineering Raleigh, North Carolina 203 APPROVED BY: Dr. Alex Q. Huang Committee Chair Dr. Subhahih Bhattacharya Dr. Brian A. Floyd Dr. Srdjan Lukic

4 DEDICATION To my Parent ii

5 BIOGRAPHY Gaurav Bawa wa born in India in 98. He received the B. Tech. in Electrical Engineering from Indian Intitute of Technology (IIT), Delhi, in From , he wa employed a a Deign Engineer at STMicroelectronic, where he worked on the deign and validation of Flah Memory and Analog-to-Digital Converter circuit. In Fall 2006, he tarted hi graduate tudie at the Department of Electrical and Computer Engineering at NC State Univerity, Raleigh, NC. Here, he received M.S. (with Thei) in 2008, and joined the Ph.D. program henceforth. Hi reearch interet include Analog/RF Integrated Circuit Deign, Signal Proceing and Device Phyic. iii

6 ACKNOWLEDGMENTS Firtly, I would like to incerely thank my advior, Dr. Alex Huang, for howing great faith in me, and allowing me to explore the beautiful cientific univere with all the freedom in the world. The journey wa not eay (it never i), but hi guiding hand wa alway there looking out for me. He i truly like a father figure and great ource of inpiration for me. I have deep gratitude toward my committee member Dr. Brian Floyd, Dr. Subhahih Bhattacharya, and Dr. Srdjan Lukic, for their feedback on the work, which helped hape the diertation in a better way. I am grateful to Dr. Mayam Ghovanloo for hi adviing during my M.S. Thei at NCSU. I would like to once again thank Dr. Kevin Gard, Dr. Leda Lunardi and Dr. Lianne Cartee, for erving on my M.S. Thei committee, and mentoring me during the early tage of my graduate life. I am thankful to Elaine Hardin for alway being there, and taking care of all the graduation formalitie. A lot of gratitude goe out to the upport received from Texa Intrument Inc. (TI) in term of reearch funding, and fabricating/packaging of the integrated circuit through the LBC7 Zebra program. At TI, I would like to thank Edward Deak, John Li, Dale Skelton and Vwodek Wiktor for their upport and encouragement during the coure of thi work. I would like to peronally thank Amnat Yakamna (of TI) and Hulgize Kaa (of FREEDM Sytem Center) for their upport with populating the PCB. At TI Lehigh Valley (formerly Ciclon Semiconductor), I thank David Jauregui for being an excellent mentor and guide who undertood me deeply. iv

7 At NC State, I thank my friend over the year for providing me ome unforgettable moment: Pawandeep Singh Taluja, Sureh Thummalapenta, Carlo Cela, Gaurav Gupta, Gary Charle, Jingzhen Hu, Ming Yin, Jia Wang, Uei-Ming Jow, Xueliang Huo, Ahutoh Mahajan, Sandeep Navada, Abhik Sarkar, Niket Chaudhary, Shivam Priyadarhi, Mutafa Berke Yelten, Edward Van Brunt, Gangyao Wang, Xiaomin Li and Sanujit Sahoo. I am thankful to Gaurav Gulati for graciouly hoting me during my tay at TI Lehigh Valley coop. I am extremely grateful to Taiuke Kazama (viiting from TI Japan), the aweome friend with whom I had great many philoophical dicuion over deliciou lunche and dinner, and who wa alway there whenever my car broke down! I alo thank Paulaji, for howering her unconditional love on numerou occaion and being the mom-away-from-home. I wih to thank my profeor from my undergraduate day at IIT Delhi and Univerità di Udine: Dr. Dipankar Nagchoudhuri, Dr. G. S. Viwewaran, Dr. S. C. Dutta Roy and Dr. Antonio Abramo, for inpiring me at an impreionable age. I thank all my buddie from the IIT day, who have upported me for everal year now (far too many to be named here). I jut cannot imagine a life without them. Latly, I would like to thank my parent and family member, with whom it would not have been poible to urvive the onlaught of the pat few year. It i truly through their value, love and upport, that I have been able to tand on olid ground even when facing extreme adveritie. I jut cannot thank them enough for alway being there for me. v

8 TABLE OF CONTENTS LIST OF TABLES... viii LIST OF FIGURES... ix Chapter.... Introduction.... Background and Prior-Art....2 Reearch Motivation Key Contribution Organization of the Diertation Chapter Baic of Switched-Capacitor Circuit Simplet Switched-Capacitor Network Switched-Capacitor Time-Contant Propertie Switched-Capacitor Filter Theory z Tranformation Method Chapter Specification for the Type-III SCF Deign Small-ignal Repone of the Buck Converter LC Filter Deign Type-III Analog Compenator Deign Chapter Theoretical Conideration for the Type-III SCF Deign Propoed Strategy Tradeoff in choice of Sampling Frequency (f S ) Bi-Linear Tranformation (BLT) Anti-Aliaing Analyi SCF Cacading Problem Chapter Practical Conideration for the Type-III SCF Deign G m -C Integrator SCF # High-frequency pole implementation Effect of Finite Opamp Gain-Bandwidth Opamp Deign Sample-and-hold Amplifier (SHA) SCF # Gain Stage Chapter Practical Conideration for the Interfacing Circuitry Double-ampling SCF conideration DC Coupling Effect Propoed Clocking Scheme vi

9 6.4 PWM Comparator Block... 0 Chapter Simulation Reult Open-Loop Frequency Repone Cloed-Loop Tranient Repone Chapter Meaurement Reult Power and Area Summary Meaured Reult Comparion with the tate-of-the-art prototype Chapter Concluion and Future Work Concluion Future Work REFERENCES vii

10 LIST OF TABLES Table.: Comparion of variou Buck Converter control cheme... 5 Table.2: Comparion of linear PWM Buck Converter control cheme... 2 Table.3: Comparion of variou active filter topologie Table 2.: Variou -z tranformation method Table 3.: Power-Stage deign for Buck Converter at f SW = MHz Table 3.2: Type-III analog filter component for pecification in Table Table 7.: Open-loop frequency repone of variou Type-III filter embodiment... 0 Table 8.: Nominal current conumption of the Type-III SCF... 5 Table 8.2: Capacitor value and area of the Type-III SCF... 6 Table 8.3: Type-III SCF controller IC pecification Table 8.4: Performance comparion of the propoed cheme with recent publihed work 27 Table 9.: Comparion of linear PWM control cheme (contemporary and propoed) viii

11 LIST OF FIGURES Figure.: Example of tate-of-the-art portable device: ipad and iphone [].... Figure.2: Diagram howing variou functional block and their aociated upply voltage in typical portable device uch a the one hown in Fig.. [2] Figure.3: Circuit chematic of a linear regulator [3] Figure.4: Circuit chematic of a tep-down charge-pump regulator during C and C 2 charging in (a) 3:2 and (b) 2: configuration. [4]... 6 Figure.5: Circuit chematic of a witched-mode ynchronou Buck Converter Figure.6: Circuit chematic of a linear PWM control baed Buck Converter Figure.7: Circuit chematic of a hyteretic control baed Buck Converter [3] Figure.8: Circuit of contant-on/off-time control baed Buck Converter [3] Figure.9: Type-III filter circuit ued for analog compenation in Fig Figure.0: Frequency repone of the Type-III filter circuit in Fig Figure.: Block diagram howing the concept of Digital PWM control Figure.2: Indirect automatic tuning cheme uing (a) VCF and (b) VCO Figure.3: Direct automatic tuning cheme with no interruption in proceing Figure 2.: A baic witched-capacitor network with aociated clock phae Figure 2.2: A baic witched-capacitor integrator with aociated clock phae Figure 2.3: Block-diagram howing the ignal proceing concept in SCF Figure 2.4: Frequency-domain repreentation of the ignal proceing in Fig Figure 2.5: Figure howing the area under the curve uing Trapezoidal Integration Figure 3.: Simplified circuit chematic of a witch-mode Buck converter Figure 3.2: Snaphot of the iotool howing complete open-loop repone of Buck converter with Type-III compenation Figure 4.: Circuit chematic emulating the Type-III filter in Fig Figure 4.2: Switched-capacitor derivative of the analog filter hown in Fig Figure 4.3: Spectral content due to ampling operation in the SCF of Fig. 4.2 without any pre-filtering and f S = 2 f SW Figure 4.4: Spectral content due to ampling operation in the SCF of Fig. 4.2 with analog integrator a an AAF and f S = 2 f SW Figure 4.5: SCF architecture for f-calability with integrator a an AAF Figure 4.6: SCF architecture for eliminating the SCF cacading problem uing SHA Figure 4.7: SHA magnitude and phae repone for f S = 2 MHz Figure 5.: SCF architecture incorporating the reference voltage elector for oft-tart of the converter Figure 5.2: G m -C integrator tage with buffer chematic Figure 5.3: PTAT current/voltage generation circuitry in a BiCMOS proce Figure 5.4: A BiCMOS Operational Tranconductance Amplifier (OTA) Figure 5.5: (a) Concept of a multi-tanh doublet. (b) G m compenation [28] Figure 5.6: Propoed circuit to replace the G m tage in Fig. 5.5 (N = 2) Figure 5.7: DC repone howing differential (a) output current (b) tranconductance, with large-ignal differential input for the circuit in Fig. 5.6 for N = 4 cae ix

12 Figure 5.8: SCF architecture including the integrator tuning cheme uing I DAC Figure 5.9: Circuit element for realizing BLT and it aociated witch phae Figure 5.: Improved BLT circuit element for ymmetry and reduction of paraitic Figure 5.2: SCF # circuit chematic with the witching phae indicated Figure 5.3: A t order analog high-pa filter with finite Gain Bandwidth Opamp Figure 5.4: A folded-cacode amplifier with cla-ab output tage Figure 5.5: Monte-carlo output for AC repone imulation of Opamp in Fig Figure 5.6: Monte-carlo output for tep repone imulation of Opamp in Fig Figure 5.7: SHA implementation a a cacade of two THA Figure 5.8: A rail-to-rail amplifier with cla-ab output tage Figure 5.9: Monte-carlo output for AC repone imulation of Opamp in Fig Figure 5.20: Monte-carlo output for tep repone imulation of Opamp in Fig Figure 5.2: Baic concept of T-network approach (Star-Delta tranformation) Figure 5.22: Propoed chematic of SCF # 2 and it aociated witch phae Figure 5.23: Gain-Block amplifier followed by a RC low-pa filter Figure 5.24: Final propoed Type-III SCF architecture Figure 6.: Equivalent Type-III SCF architecture at low frequencie Figure 6.2: Propoed clocking cheme for the Type-III SCF architecture Figure 6.3: Variou clock and awtooth waveform for the cae f SW = MHz Figure 6.4: PWM Comparator Block and it aociated waveform Figure 6.5: Rail-to-rail ICMR aynchronou PWM Comparator Figure 7.: Simulation etup for characterizing the DUT Figure 7.2: Simulation of Fig. 7. howing reult for (a) PSS (b) PAC (V SH ) Figure 7.3: Simulation of Fig. 7. howing PAC reult for (a) V COMP (b) V OUT Figure 7.4: Simulation of Type-III SCF howing PAC reult B TUNE_F = [0, ] Figure 7.5: Simulation of load tep repone for conventional ARCF in Fig Figure 7.6: Simulation of load tep repone for cacaded ARCF in Fig Figure 7.7: Simulation of load tep repone for cacaded SCF in Fig Figure 8.: Die photo of the propoed Type-III controller IC Figure 8.2: PCB photo for teting the propoed controller IC with Buck converter power tage Figure 8.3: Meaured waveform howing the load tep tranient at f SW = 0.5 MHz Figure 8.4: Meaured waveform howing the load tep tranient at f SW =.0 MHz Figure 8.5: Meaured loop repone of the complete ytem at f SW = 0.5 and.0 MHz Figure 8.6: Meaured waveform howing the V SW jitter performance at f SW = 0.5 MHz and V IN /V OUT = 3.3/.0 V Figure 8.7: Meaured waveform howing the V SW jitter performance at f SW =.0 MHz and V IN /V OUT = 3.3/.0 V x

13 Chapter. Introduction. Background and Prior-Art Lat decade ha een the emergence of highly compact, light and efficient portable device which combine everal function into one. For example, a contemporary handheld cellular phone can erve a an audio/video recorder, a digital camera, a wirele internet brower and a jukebox, to mention a few. Thi ha been made poible largely by the rapid hrinking of the MOS tranitor dimenion that allow fater digital computing (Moore Law) while occupying leer area on an Integrated Circuit (IC). In contrat, the battery Figure.: Example of tate-of-the-art portable device: ipad and iphone [].

14 Figure.2: Diagram howing variou functional block and their aociated upply voltage in typical portable device uch a the one hown in Fig.. [2]. 2

15 technology needed to power the microproceor and all the peripheral circuitry ha not been able to keep up with the advancement in IC technology. With the battery ize being a function of the ytem power requirement, it end up occupying a larger portion of the total available ize in the contemporary handheld device, uch a the one hown in Fig... Thi of-coure i neceitated by the need to enure a minimum uer full-load uer on-time before the battery recharging can take place. Thu, with the ize (and weight) of the device at a premium, it i important that the ytem i deigned to be highly area and power efficient, at the ame time. Thee parameter are dicued in greater detail here:. Area Minimization: The bet way to minimize the area i to try and implement a many circuit function a integrated olution, and minimize the off-chip component. In addition, ince the IC can be batch-fabricated, it reult in a highly cot-effective olution with coniderably lower price per die. However, ince not all circuitry can be implemented on a ingle mammoth packaged IC, it i judiciou to have variou IC and their repective package egregated on the bai of their functionality. Thi alo lead to greater deign flexibility. A a reult, a printed circuit board (PCB) olution that contain everal packaged IC, individually optimized for high performance and low cot i achievable. 2. Power Efficiency Maximization: To undertand the power requirement, we can refer to Fig..2, which give a generalized block-diagram baed overview of power management in portable device. It can be een that everal poitive/negative voltage need to be upplied to variou circuit component from a ingle Li-Ion battery, which can provide an input DC voltage in the range V. In addition, every circuit component ha a 3

16 different current requirement. Hence, with braiding a ingle common power rail acro the PCB not being an option, the efficient olution i point-of-load (POL) regulation. In POL, every voltage regulator i optimally deigned for the given load voltage/current requirement and phyically preent right next to it. Now, the CPU (Fig..2) i the mot power-hungry block in the entire architecture, with power amplifier for audio/rf tranmitter and LCD driver being a ditant econd. The CPU i eentially a microcontroller core operating on a high-peed clock, which conume everal ampere of current at full-load (and about a tenth at lightload), and require a low upply voltage of.8 V. Hence, a dedicated power converter which can efficiently tep-down the battery voltage to the rated CPU voltage i indipenable in enuring high overall ytem power efficiency. The deign of uch a regulator i indeed the focu of thi reearch. With the aforementioned area and power requirement in mind, a fully-integrated high-efficiency tep-down voltage regulator would indeed be a plauible olution. Thi eentially give u the following three option:. Linear Regulator The chematic of a linear regulator i hown in Fig..3. The output voltage (V OUT ), i regulated to a caled verion of the on-chip bandgap reference voltage (V REF ), by the reitor R,2 and the error amplifier in feedback: V V REF 2 R R OUT (.) 4

17 Figure.3: Circuit chematic of a linear regulator [3]. The linear regulator can be a fully-integrated olution (with the exception of load capacitor) but uffer from poor efficiency. The efficiency, auming only the load current flow through the pa device, and zero current in the error amplifier, i given by: P P V V OUT OUT LIN (.2) IN IN For a given regulated V OUT (=.5 V), the efficiency i maximum at lowet battery input voltage, V IN (= V DD = 2.7 V). Hence, the bet cae efficiency (= 55 %) i unacceptably low. It mut be undertood that even though thi olution i fully-integrated and hould reult in lower area, the poor efficiency will reult in a larger battery ize (for a given uer on-time). In addition, poor efficiency will alo reult in higher overall power diipation for a given load power requirement, and can ignificantly heat up the device. Hence, power efficiency i the bottleneck to building a compact portable device. 5

18 2. Capacitive Charge-Pump Regulator Fig..4 how the chematic of a tep-down capacitive charge-pump baed regulator in two different configuration. In a charge-pump, the flying capacitor C and C 2 are (a) (b) Figure.4: Circuit chematic of a tep-down charge-pump regulator during C and C 2 charging in (a) 3:2 and (b) 2: configuration. [4] charged by V IN in one phae, and hare charge with C OUT in the complementary phae. Baed on the connection of the witche between the flying capacitor, the charge-pump can have variou V IN and V OUT configuration (Fig..4). Several operating mode are required in order to maintain high efficiency when the battery voltage (V IN ) change for a given output voltage (V OUT ). With the exception of C, C 2, C IN and C OUT, the entire architecture can be fullyintegrated. In addition, thee capacitor can be made maller by chooing a higher witching frequency, which decreae the output impedance of the converter. In [4], C, 2 = 0.22 μf, C IN = μf, C OUT = 4.7 μf, for a witching frequency of 2 MHz and load current requirement of 50 ma. More than 85 % efficiency under teady-tate condition i enured in variou 6

19 Figure.5: Circuit chematic of a witched-mode ynchronou Buck Converter. operating mode. A fundamental limitation with the charge-pump (and the linear regulator a well) i the maximum current that can be upplied to the load [5]. Thi i limited by the input current drain, and hence high efficiencie can only be obtained for load current up-to 200 ma. In addition, ince a charge pump ha dicrete operating mode, it ha poor regulation capability and efficiency around the point of mode tranition. 3. Switch-mode Inductive Buck Regulator Fig..5 how the circuit chematic of witch-mode Buck converter, with controller directly ening the output voltage V OUT, for regulation. Now, the High-Side (HS) and Low- Side (LS) NMOS are driven by complementary witche uch that the witch-node V SW, emulate a quare wave with amplitude V IN and duty cycle D at any given witching frequency (f SW ). The duty cycle alo correpond to the time for which the inductor (L) i charged by witching the HS NMOS On. Thi quare wave (at V SW ) when filtered by a low- 7

20 lo LC filter provide a table output DC voltage V OUT, to the load. It can be proved under teady-tate condition with V CTRL (and hence V SW ) having a duty-cycle D at a given f SW, and auming zero lo in witche and LC tank [6]: V D (.3) OUT VIN Thu, with 0 < D <, the output voltage i a caled-down verion of the input voltage. Now, the Buck converter can handle large output current and it i indeed the preferred olution for powering the CPU (ee Fig..2) [5]. In tate-of-the-art BCD technologie it i alo poible to integrate the HS/LS NMOS and their correponding Driver on one die, while delivering full-load current of 3 A at an efficiency ~ 90 % [7]. Thi efficiency target i achieved at a nominal witching frequency of. MHz, at which it i not poible to integrate the LC filter. Higher witching frequencie (> 00 MHz) can be targeted to decreae the LC filter ize for poible integration, but are generally not preferred due to the decreae in efficiency, a a reult of increaed frequency-dependent witching loe [6]. The main limitation exit in the witching device technology, which ha a fundamental tradeoff between it on-reitance (conduction loe) and gate-capacitance (dynamic loe) minimization. In addition, the LS NMOS body-diode (ee Fig..5) revere-recovery loe (during dead-time) alo increae with higher current and fater witching tranient. Recently, many high-frequency Buck converter have been reported to be integrated deign [8]-[2]. Amongt thee, the maximum reported load current i 300 ma for a correponding efficiency of 83.2 % at f SW = 233 MHz [0]. The author have employed Surface-Mount Technology (SMT) air-core inductor mounted on-chip, while the output filter capacitor i integrated. In [], when both L and C were integrated on-chip with f SW = 70 MHz, an efficiency of only 77.9 % wa 8

21 achieved for a 90 ma load. It mut be undertood that the current device technology preent fundamental barrier to the attainment of a high frequency (> 00 MHz) and high full-load current (> A) witch-mode Buck converter with high power converion efficiency (> 90 %). With the LC filter integration not poible for the given load current requirement, our focu now hift to the controller (Fig..5). The controller i an eential component of the Buck converter deign that enure the regulation of output voltage even in the preence of noie, line/load tranient and temperature variation. Thi i accomplihed through negative feedback from the output voltage to control the duty cycle of the Buck converter. The following conideration are important in deigning a controller for a Buck converter baed CPU power upply: i. DC Regulation: The teady-tate regulation of the converter need to be very tight for computing power application (< %). Thi i becaue it directly affect the performance and reliability of the digital circuitry. The DC regulation include both the line and load regulation. Thi eentially mean that the output DC voltage hould not change by more that % over the entire range of battery voltage and load current requirement (light/full load). ii. Output Voltage Ripple: The ripple requirement for digital circuitry are much relaxed compared to that for enitive analog deign. Hence, typically a ripple voltage of le than 5 % i conidered acceptable. It mut be undertood that the output voltage ripple i determined by the output LC filter deign for a given load current and witching 9

22 frequency. However, a dicued later, certain control trategie can alo place minimum output voltage ripple requirement on the LC filter for voltage regulation. iii. Stability Conideration: The converter hould be table under varying line/load condition and LC filter value (determined by the wort cae voltage/current ripple requirement). In addition, the controller mut enure that the converter i table while tranitioning from Continuou Conduction Mode (CCM) to Dicontinuou Conduction Mode (DCM), and vice vera. iv. Tranient Repone: The output voltage of the Buck converter hould be able to recover quickly when a load tep tranient take place. The cloed-loop tranient repone i characterized by the voltage overhoot and ettling time, and i a function of the load tep magnitude and it di/dt. If the cloed-loop tability i enured with an under-damped 2 nd order repone, the overhoot and ettling time are inverely related. Typically, an over- /under-hoot < 0 % i an acceptable pecification for CPU power upplie, which have di/dt ~ A/μ. Note that we have only conidered the effect of controller repone on the tranient performance, inide the control-loop bandwidth. In reality, the LC filter, PCB layout and IC packaging paraitic inductance alo impact the tranient repone, by defining the high-frequency output impedance. To conduct a fair comparion, we will conider thee effect to be the ame for all type of compenation cheme. v. Electro-Magnetic Interference (EMI) Conideration: EMI i an important concern for witching regulator epecially due to the high trength of the current ignal being commutated between HS and LS NMOS witche (Fig..5). EMI thu need to be controlled in order to meet the FCC regulation. Another eriou concern i the poible 0

23 malfunction of the enitive RF/analog circuitry preent on the ame board (ee Fig..2). There are two way in which a controller can lead to poor EMI performance: Firtly, if the V CTRL ignal i jittery, it can fire the HS/LS commutation at non-uniform interval or even lead to puriou witch activation. Secondly, if the frequency of the converter i not explicitly defined, it i prone to preading over a range of value due to noie and temperature variation. In addition, it would not be poible to ynchronize the converter with the ytem clock. Filtering of uch effect can create havoc for the adjacent ignal/power proceing circuitry ince it exact characteritic are unpredictable. In addition to thee requirement, the controller mut have low enough power conumption uch that the light-load efficiency i not ignificantly affected. In addition, a fully-integrated olution i preferred ince it reult in lower area. The aforementioned requirement are very much in-line with the overall power converter deign requirement, and will not be dicued in more detail. At thi point, we can compare the available control cheme for voltage regulation. Thee can be categorized a either linear or non-linear control method. Linear control cheme are baed on the low-frequency linear mall-ignal repone of the witching converter [6]. Such cheme ue a fixed witching frequency (f SW ) for the converter uing an on-chip clock ocillator (Fig..6). The compenator morph the input error ignal (V OUT V REF ) baed on it frequency repone and generate V COMP. The V COMP ignal mut now be tranlated into appropriate duty cycle information for the converter. Thi i done by the aynchronou comparator comparing V COMP with a linear ramp (awtooth running at f SW ), to generate a Pule-Width Modulated (PWM) ignal, V PWM. Since the witching converter

24 Figure.6: Circuit chematic of a linear PWM control baed Buck Converter. linearity i only valid for low-frequencie, it i the job of the compenator to enure cloedloop tability with a low cutoff bandwidth f C ~ f SW /0. Thu, the tranient repone i limited by the witching frequency of the converter. Contemporary architecture employ f SW ~ 4 MHz, which preent a reaonable tradeoff between ize, efficiency and tranient performance [5]. Baic non-linear control cheme monitor the output voltage ripple and can be baed on either of the following two: A. Hyteretic Control: 2

25 Figure.7: Circuit chematic of a hyteretic control baed Buck Converter [3]. Fig..7 how the chematic of a hyteretic regulator. The aynchronou comparator (with hyterei band V H ) compare the divided output voltage (V FB ) with the reference voltage V REF, and turn the witch S On whenever V FB < V REF V H /2. The witch i turned Off when V FB > V REF + V H /2. Thu, the output voltage i regulated to: V OUT V REF R v R2 (.4) v V R 2 R H max 2 (.5) Hence, V OUT i the um of a DC component and an AC voltage ripple (Δv), and it maximum amplitude i given by Δv max. The ripple magnitude (and hence large R C ) i clearly needed to be high for ucceful operation in a noiy environment. If V H band i made maller, the hyteretic converter i prone to jittery behavior. In addition, the teady-tate witching frequency (f SW ) i a function of L, C, L C, R C, V H and T D. Here, T D i the comparator delay, 3

26 Figure.8: Circuit of contant-on/off-time control baed Buck Converter [3]. which i a highly non-linear function of temperature, proce variation and input voltage lope. Clearly, the witching frequency i poorly defined. The advantage of uch a control are low power conumption, fully-integrated architecture, fat tranient repone (ettle within 2 witching cycle [3]) and reduction in f SW under DCM condition (to enure good light-load efficiency). B. Contant-On-Time Control: An improvement over the hyteretic regulator i the Contant-On-Time controller (Fig..8). In thi cheme, all the advantage of hyteretic regulator are inherited, while the problem of large f SW pread, high noie enitivity and poor DC regulation are improved upon. Thi i accomplihed by generating a contant duty pule whenever V FB < V REF. Thi 4

27 Table.: Comparion of variou Buck Converter control cheme Performance Metric Fixed-Frequency Hyteretic Contant-On DC Regulation Accuracy Good Poor Average V OUT Ripple Magnitude Small Large Large Stability Concern Stable with all LC Large R C R C C > T ON /2 Tranient Repone Average Good Good EMI Regulation Good Poor Average Power Conumption Analog Moderate Digital Very High Low Low Monolithic Solution Analog No Digital Ye Ye Ye charge the inductor L for a given time (= T ON ), which can be programmed uing a Monotable Multi-Vibrator (or one-hot). Thu, only the Off time i impacted by T D and thu the frequency ha lower pread than the hyteretic regulator. The comparator till need to monitor the V OUT ripple and hence R C cannot be made mall. In addition, there i a tability concern in CCM which limit the minimum value of R C to T ON /2C [3]. Table. compare the linear (fixed-frequency) control cheme with the two nonlinear cheme (dicued above) on variou controller performance metric. Thoe cell have been highlighted in yellow in which the bet performance i enured by the control cheme under conideration. It can be een that fixed-frequency (FF) control outperform the non-linear cheme on DC regulation, output voltage ripple, tability acro all LC (deigned to meet ripple requirement) and EMI regulation. The bigget advantage of the non-linear cheme are their fat tranient repone and low power conumption. It mut be undertood that our target application i high-performance computing platform, in which 5

28 DC regulation and voltage ripple are parameter which cannot be compromied. In addition, EMI i a eriou concern ince it i a high-current (> A) witching converter that can impact the performance of nearby circuitry (Fig..2). To conclude, we have een that a witch-mode Buck regulator i indeed a viable olution for high-current high-efficiency tep-down power converion for high-performance digital computing uch a the CPU in portable application. To ave area, it i poible to integrate the witching device and their aociated driver. However, the LC filter cannot be integrated in current technologie. On the controller front, the dicuion in Table. lead u to conclude that fixed-frequency control i indeed the way forward. However, a can be een in Table., enuring a monolithic and power efficient olution for FF-control i not poible at the ame time. Thi i indeed the topic of our next dicuion and motivation for further reearch..2 Reearch Motivation In thi ection, we will firt compare and contrat the analog v. digital control cheme that are employed in PWM control baed Buck converter. Our focu i thu on the H C () block in Fig..6. In the analog implementation, Type-III compenation i ued, epecially in Buck converter deign that employ low-esr Multi-Layer Ceramic Capacitor (MLCC) for mall V OUT ripple, low EMI and mall footprint requirement [7]. Thi filter ha the following tranfer function correponding to the circuit in Fig..9. HC C R R 2 R 3C 3 C R R 3C 2 C 3 ( ) (.6) R 2 C 2 C 3 6

29 Figure.9: Type-III filter circuit ued for analog compenation in Fig..6. Thu, a Type-III filter conit of an integrator for cloed-loop DC regulation and two real zeroe for phae boot cloe to the LC filter double-pole. One pole i generally placed at the ESR zero frequency (given by /R C C from Fig..6) and another pole i placed at high frequency for attenuating the high-frequency witching harmonic. The Bode Plot of the Magnitude and Phae repone of the filter i hown in Fig..0, uing aymptotic approximation. Now, we mut conider the power requirement for amplifier ued in Fig..9. In order to uccefully realize the filter tranfer function, the amplifier Gain Band- Width (GBW) mut be at-leat 0 time higher than the filter Unity-Gain Bandwidth (UGB) given by f UGB in Fig..0. Now, for a Buck converter deigned for f SW = MHz, typically f UGB > MHz and hence the amplifier GBW, f GBW > 0 MHz. In addition, the load capacitance to be driven by the amplifier i in the nf range [7]. Thee deign requirement reult in the amplifier burning > ma of current in it output tage, jut to puh the non- 7

30 Figure.0: Frequency repone of the Type-III filter circuit in Fig..9. dominant pole outide f GBW. It mut be undertood that puhing higher witching frequencie would correpondingly reult in an increaed level of amplifier power diipation. Thi level of power conumption i, however, acceptable even for enuring high light-load efficiency in the current application. Thi i alo made poible by the fact that many protection function uch a Over-current Protection (OCP) and Under-Voltage Lock-Out (UVLO) can be eaily implemented by low-power analog circuitry. In [7], the total power conumed i ~ 2.2 ma for f SW =. MHz Buck converter deign. Another iue with thi filter i that the capacitor value are too large to be integrated on-chip (in nf range). An example calculation for all 8

31 Figure.: Block diagram howing the concept of Digital PWM control. filter component for a MHz Buck converter deign i given later in Table 3. in Section 3.3. In addition, the RC time contant will vary ±40 % due to Proce, Voltage and Temperature (PVT) variation, once they are implemented on-chip. Thee conideration rule out the poibility of a monolithic olution and reult in a larger footprint and increaed cot. Finally, the power upply deigner can chooe to operate the witching converter at a frequency of choice, baed on area v. power efficiency contraint in a given application. While the power-tage (excluding the LC filter) can remain the ame, the filter component need to be redeigned and there exit no programmability. To counter the aforementioned problem of the analog implementation of thoe of integration and programmability, there exit a Digital-PWM (DPWM) implementation. Thi i conceptually hown in Fig... The output voltage i firt conditioned, which include calculation of the error ignal (V OUT V REF ) and ubequent amplification. Thereafter, it i fed into a low-reolution high-peed Analog-to-Digital Converter (ADC), and it give N -bit 9

32 digital output. Thi digital data i then proceed by a Digital Signal Proceing (DSP) circuitry, which implement the Type-III filter and the aociated PWM function. Thi digital output i then converted into an analog PWM ignal every witching interval by a high-reolution Digital-to-Analog Converter (DAC). The fater the DSP clock peed, higher i the temporal reolution of the controller and better the tranient performance. Thu, in order to achieve a tranient performance comparable to the analog counterpart, a very high peed clock i required and the analog front-end and digital circuitry end up burning a lot of power. In addition, the DC regulation i largely a function of the DAC reolution, again making it a power intenive unit to meet the large SNR requirement. For a tate-of-the-art DPWM baed controller in [5], the power conumption for a 4-phae deign i 40 ma (digital) and 8 ma (analog). Thi implie about 2 ma power conumption per phae. It i for thi reaon that DPWM controller are more attractive for multiphae deign ince a lot of digital monitoring and communication function can be hared. The DPWM cheme i fully-integrated on-chip and a highly programmable one. The uer can configure the pole/zero placement, and even tune them baed on the witching frequency. However, the large power conumption make it unattractive for ingle-phae power converion cheme, uch a the one we are targeting for the CPU power upply deign in portable device. Table.2 ummarize the comparion between the analog and digital filter implementation. It clearly motivate the need for a filter that can be fully-integrated, i programmable and diipate moderate amount of power without ignificantly degrading the tranient 20

33 Table.2: Comparion of linear PWM Buck Converter control cheme Performance Metric Analog Digital Area High $ Moderate Filter Variability High $ Low Degree of Freedom Low High Frequency Scalability None High DC Regulation Accuracy Good Good Tranient Repone Average Average Power Conumption Moderate High Monolithic Solution No Ye $ Auming fully-integrated RC component for the Analog Filter. Digital Filter require much higher power to achieve a DC and tranient performance comparable to the Analog Filter. performance (chooe all yellow boxe). To achieve thi goal, we have conidered variou integrated filter implementation cheme, and they can be mainly be categorized in the following way:. Active-RC Filter The continuou-time Active-RC Filter (ARCF) ue reitor (R) and capacitor (C) to implement the filter tranfer function. Typically, an active element (amplifier) i required to realize the ignal amplification in the filter. In addition, the active element can be ued for realizing high-q filter, by emulating inductor or negative reitance onchip via feedback mechanim. The advantage of ARCF are very high linearity due to ue of highly linear on-chip RC element, low noie performance and a a reult, a very high dynamic range. Thi i indeed true for the filter implementation a hown in Fig..9. However, a dicued, thi filter uffer from large on-chip variation requiring 2

34 extenive trimming for tatic proce variation. For dynamic variation w.r.t. temperature and voltage hift, typically on-line or off-line calibration i required which i hard to achieve in thi cae. Another poibility i to implement reitor uing MOS tranitor operating in triode region, and controlling their reitance via their gate voltage. Thi approach open up the poibility of calibration for dynamic variation, but the linearity (and hence dynamic range) i poor due to the large dependence of MOS reitance on the commonmode operating voltage. 2. G m -C Filter The ARCF concept can directly be extended to the G m -C Filter (G m CF) approach by implementing the reitor uing on-chip tranconductance (G m ) element. The G m block can be implemented either by directly uing MOS tranitor biaed in aturation region, or uing an MOS- or Bipolar-input baed Operational Tranconductance Amplifier (OTA), depending on the input/output impedance requirement. The G m CF have the advantage over ARCF that they can be made calable by uing a control voltage or current. Thu, G m CF can poibly be compenated for both tatic and dynamic proce variation via cloed-loop compenation. Such a principle i known a automatic tuning, and two method of achieving the ame are hown in Fig..2 and.3. Fig..2 illutrate the indirect tuning mechanim for automatic tuning. Eentially, the main filter i indirectly tuned to achieve the deired frequency repone, while an auxiliary circuit i being directly tuned via a cloed-loop mechanim. It i important to undertand that the variou circuit element in both the main filter and the auxiliary block 22

35 are cloely matched on-chip. The auxiliary can either be a Voltage-Controlled Filter (VCF) (in Fig..3a) or a Voltage-Controlled Ocillator (VCO) (in Fig..3b) which i being tuned to an off-chip table reference frequency (f REF ) via a control ignal (V CTRL ). V CTRL i typically a low-pa filtered verion of the output of the Phae Detector and it cloe the auxiliary tuning loop. If thee filtering requirement neceitate large component and need to be placed off-chip, it defeat the purpoe of thi work. The choice of f REF i typically baed on the characteritic of the VCF, and it hould have high gain enitivity w.r.t. the quantity being compared (phae or magnitude) for locking the loop. Now, V CTRL contain harmonic (or pur) of f REF ince no realitic lowpa filtering can enure infinite attenuation. Thee harmonic can potentially impact the performance of the main filter, epecially if it ha high enitivity at N f REF. Thu, ideally, the main filter hould have zero enitivity at f REF and it harmonic, while the VCF hould be quite the oppoite. Keeping our reference Type-III filter under conideration, enuring the above by deign i not an obviou or traightforward propoition. Fig..3 illutrate the direct tuning mechanim for automatic tuning. The tuning mechanim i imilar to the VCF baed tuning decribed above and a reference generator i till required. The advantage of thi cheme i that the neceity for matching between the main filter and auxiliary circuit i completely eliminated, and hence better accuracy can be guaranteed. However, a replica filter i till required which i being tuned when the main filter i operational, and vice vera. Thi i done in order to prevent any interruption in the ignal proceing. Thu, care mut be taken to minimize witching 23

36 tranient when the tuning circuit i being witched from one filter to the other. Thi make the direct tuning mechanim rather unattractive, epecially for the application under conideration, where cloed-loop control (and tability) i required. It mut be undertood that the automatic tuning mechanim have their performance limitation in all the aforementioned cheme. In an example cae, a G m CF employing indirect automatic tuning will have the following drawback: a. Limited linearity and linear calability of the filter tranfer function acro PVT variation. b. Iue related to automatic tuning to compenate for filter variability: i. An external, table reference frequency generator i required leading to area and cot overhead. ii. Extra on-chip proceing circuitry i required in addition to the main filter, leading to area and power overhead. iii. Filter accuracy i limited by imperfect device matching of element preent in the main filter and the auxiliary circuit. In addition, it i not implitic to guarantee exactly the ame operating condition of the matched element being tuned in the auxiliary; and the main filter. iv. The tuning circuit non-idealitie can lead to the performance degradation of the main filter. A a reult, the deign complexity of the main filter may increae. Another conequence could be the placement of tuning circuit loop filter off-chip, which i highly undeirable. 24

37 (a) (b) Figure.2: Indirect automatic tuning cheme uing (a) VCF and (b) VCO. Figure.3: Direct automatic tuning cheme with no interruption in proceing. 25

38 3. Switched-Capacitor Filter Switched-Capacitor Filter (SCF) are eentially ampled-data filter, and much like G m CF, can be derived from their ARCF counterpart by replacing the reitor by an equivalent witching capacitor. It mut be undertood that the reitor approximation i only valid for frequencie much lower than the ampling rate of the SCF, and high frequency effect can introduce filter ditortion. Thu, SCF i not the preferred olution for high frequency (> 0 MHz ignal bandwidth) application, ince very high clock rate are required to enure a given overampling ratio for accurate filter realization. Now, ince the filter i ampling the input ignal, care need to be taken to enure that no aliaing ditortion occur in the filter. In addition, there can be inherent ampling delay in the SCF architecture, which i highly undeirable in a cloed-loop control application. Thee effect make SCF the mot difficult to yntheize out of the three aforementioned filter for the application under conideration. However, the SCF preent an important benefit of very low on-chip variability (< %), being highly tolerant w.r.t. both tatic and dynamic variation, completely eliminating the need for any trimming or tuning. The only requirement i the trimming of the ampling clock, which i generally enured by default in mot contemporary IC, and hence i not truly a deign overhead. The linearity of the filter i high if highly-linear capacitor are employed, while the dynamic range get limited mainly by the thermal noie aliaing (inide the Nyquit Bandwidth) and charge injection/clock feedthrough effect. 26

39 Table.3: Comparion of variou active filter topologie Performance Metric ARCF G m CF SCF Filter Variability High Moderate/High Low Compenation for variability Extenive Trimming Trimming/ Automatic Tuning Clock Trimming Linear Scalability None Low/Moderate High Noie Low Low/Moderate High Linearity High Low/Moderate Moderate/High Dynamic Range High Moderate Moderate Frequency Limit High Medium/High Medium To conclude, while there doe not exit a perfect integrated filter topology, the SCF ha the important advantage of being linearly calable (with clock/ampling frequency), enuring low on-chip variability w.r.t. PVT variation, without the need for any trimming or automatic tuning circuitry. In addition, SCF i well uited for medium-frequency and moderate dynamic range application, uch a the one under conideration. The ummary and comparion matrix for all the aforementioned filter i decribed in Table.3..3 Key Contribution In thi diertation, we have made the following key contribution:. We have explored a novel paradigm involving the ynthei of ampled-data (dicretetime) integrated analog filter baed Type-III compenation for voltage-mode control of fixed-frequency witched-mode Buck converter. 27

40 2. We have laid the theoretical foundation for the deign of uch a filter uing a witchedcapacitor filter embodiment. Potentially, the theory can be eaily extended to other ampled-data (dicrete-time) analog filter embodiment a well. 3. We deigned an integrated circuit prototype of the filter and were able to validate the propoed theory via both time- and frequency-domain experiment. 4. In imulation, we oberved that the analog (continuou-time) and the propoed (dicretetime) filter reult in negligible difference in the cloed-loop tranient repone, once deigned to have near-imilar open-loop frequency repone. 5. We have oberved that the propoed filter can combine the benefit of conventional analog and digital Type-III filter implementation, and ha the potential to outperform them in the future. 6. While the propoed filter i deigned for a witched-mode Buck Converter employing linear PWM control, the fundamental developed can be extended to other power converter topologie and control cheme a well..4 Organization of the Diertation Thi diertation ha been organized a follow: In Chapter 2, we will dicu the baic Switched-Capacitor Filter (SCF) theory. In Chapter 3, the frequency repone for the target filter will be evaluated for an example MHz Buck converter deign, uing the conventional analog filter. In Chapter 4, the theoretical challenge concerning the SCF-baed Type-III filter realization are dicued, and a fully-integrated frequency calable architecture i arrived at. In Chapter 5, the deign/implementation iue with the filter deign are 28

41 addreed, for a target Texa Intrument 0.36-μm BCD technology in the temperature range [-40, 25] C. In Chapter 6, we dicu the iue related to the filter clocking and interfacing circuitry for PWM control. In Chapter 7, we decribe a unified imulation methodology for acertaining the frequency repone of the Type-III SCF and Buck converter in realitic SPICE imulation. We will alo compare and dicu the cloed-loop tranient performance of the analog filter v. the SCF baed Buck converter. In Chapter 8, we preent the meaurement reult from the fabricated integrated circuit prototype. Chapter 9 give u the concluion and future work. 29

42 Chapter 2 2. Baic of Switched-Capacitor Circuit 2. Simplet Switched-Capacitor Network A baic witching capacitor circuit i hown in Fig. 2.. The non-overlapping phae witche, Φ and Φ 2, are derived from a Clock of time period T. The capacitor C i charged by the input voltage ource V IN during Φ, until t = NT τ. Here, τ repreent an infiniteimally mall time period before the clock falling edge before which Φ open and C top charging. Again, at the clock edge at t = NT, Φ 2 cloe and C hare charge with C 2 until t = NT + T/2 τ. In the next half clock cycle, the capacitor C again recharge back to V IN at t = NT + T τ. Here, if we aume that V IN ha much maller bandwidth compared to the clock frequency, and C 2 >> C, we can ay: QC ( t NT ) QC( t NT T ) C T 2 QC ( t NT ) CVOUT The average amount of charge that flow from the input ource V IN in one clock cycle (T) i given a: Q AVG Q T ( t NT T ) QC( t NT 2 C ) QAVG C VIN VOUT (2.) Thu, the average current flowing through the network i given a: V IN 30

43 Figure 2.: A baic witched-capacitor network with aociated clock phae. I AVG Q T AVG C T V IN V OUT (2.2) We can thu write the equivalent network impedance at low frequency (ince we have only calculated the average current): Z EQ V IN V IAVG OUT T C fsc R EQ (2.3) Hence, at frequencie much lower that the ampling frequency (f S ), a witching capacitor emulate a reitor, given by R EQ. Thi i indeed the fundamental concept behind lowfrequency architecture uch a the charge-pump for integrated power converion [4]. In addition, by chooing a low f S, it i poible to integrate on-chip reitor with very large 3

44 Figure 2.2: A baic witched-capacitor integrator with aociated clock phae. value (> MΩ) uing reaonable capacitance value (~ pf) [8]. 2.2 Switched-Capacitor Time-Contant Propertie Now, if the voltage node V OUT (Fig. 2.) i connected to the feedback node of an amplifier (V FB ) with capacitive-feedback, we arrive at a baic inverting integrator (Fig. 2.2). Thi integrator i indeed the building block numerou filter realization in the dicretetime domain [6], [8]. Auming, low input ignal frequency compared to f CLK, and hence a large Over-Sampling Ratio (OSR > 0), we can aume that the witched-capacitor i indeed a reitor. Hence, the integrator time contant i given a: 32

45 f C C C C 2 2 REQC 2 T (2.4) S Differentiating (2.4) we get, T T C C 2 2 C C (2.5) From (2.4) and (2.5) we can arrive at two extremely ignificant reult:. Frequency Scalability of Time-Contant From (2.4), it can be een that the time contant i directly proportional to the ampling/clock period. Thi eentially mean that if the filter clock i a derived verion of the witching converter clock, the realized filter would be a fundamentally frequency-calable. 2. Low on-chip variability of Time-Contant From (2.5), it can een that abolute variability of the time contant (τ) i a function of the abolute variability of the clock period (T) and relative mimatch of capacitor C and C 2. Now, the clock frequency of a fixed-frequency control baed witching converter i already trimmed to be highly accurate (< %). In addition, while the abolute inaccuracie of capacitor (ΔC/C) i large (~ 20 %) with Proce/Temperature variation, the relative mimatche between capacitor can be made extremely mall (< %) [6]. The total inaccuracy of thi time contant i ignificantly lower than that of a imple Active-RC integrator (~ 40 %), and thu a fully-integrated trimle filter deign i poible. 33

46 Figure 2.3: Block-diagram howing the ignal proceing concept in SCF. A a concluion, at the outet, it eem feaible to conceive fully-integrated, frequencycalable witched-capacitor filter architecture. However, till now, we have only conidered the low-frequency behavior of the witched-capacitor network and it i not ufficient to undertand the complete filter repone at high-frequencie. Thee will be dicued in the following two ub-ection. 2.3 Switched-Capacitor Filter Theory The Switched-Capacitor Filter (SCF) concept i hown in Fig. 2.3, in a contant-rate ignal proceing ytem. The analog input ignal (V IN ) i ampled by an impule train at a given ampling frequency (f S ) to generate a dicrete-time ignal V SAM. Thi ignal i then morphed by the impule repone of the SCF core to generate V SCF. Thi ignal, till in dicrete-time domain, i converted back to continuou-time domain by a Zero-Order Hold (ZOH) function to generate the final taircae-reembling output ignal, V OUT. Fig. 2.4 how the frequency-domain repreentation of the ignal proceing that take place in Fig The input ignal i aumed to be band-limited with a bandwidth of f B. The impule ampler ample the input at a rate f S > f B, repreented by a periodic impule 34

47 Figure 2.4: Frequency-domain repreentation of the ignal proceing in Fig train. Thee impule multiply with the input ignal in time-domain and convolve in the frequency-domain to generate a periodic pectrum of ampled data (V SAM ) [6]. At thi point, it i important to note that f S f B > f B, ele the adjacent pectra would merge and lead to aliaing ditortion. Once thi ditortion take place, it i difficult to recontruct the original ignal uing conventional cheme. In addition, any further ignal proceing on thi data 35

48 would reult in erroneou output. Hence, for a given f S, the maximum allowable input ignal bandwidth i f S /2. Thi i alo known a the Nyquit Bandwidth. Thereafter, the ignal i proceed by a dicrete-time calculator (SCF Core Block in Fig. 2.3), which contruct new output ample baed on the information contained in current/previou input/output ignal ample. In Fig. 2.4, we have depicted a high-/band-pa SCF repone. Finally, the ZOH eentially perform a time-domain convolution of V SCF with a unit-tep function at the ame frequency, f S. The frequency-repone of the unit-tep function i a inc function, which ha null at multiple of ampling frequency, f S. Finally, the pectrum of V OUT i a uperpoition of the V SCF and inc frequency repone a hown in Fig We will now briefly dicu the Anti-Aliaing Filter (AAF) deign requirement baed on the concept of Nyquit Bandwidth (f S /2). From Fig. 2.4, we can conclude that an ideal AAF would limit the input ignal (V IN ) to f B < f S /2, and any higher-frequency content would be rejected with infinite attenuation. Now, thee are clearly impractical deign pecification for the AAF, which can never be met. Intead, a more practical deign pecification for the AAF i that V IN i limited within the Nyquit Bandwidth in uch a way that the Signal-to-Noie Ratio (SNR) i > 40 db. Here, noie refer to all unwanted ignal that are preent both in-band and out-of-band. In-band noie i dominated by the thermal and flicker noie preent in MOS device, while out-of-band noie i dominated by the highfrequency witching noie preent on-chip. Finally, it mut be undertood that while the inc function ha a low-pa characteritic (notche at multiple of f S ), it cannot aid in meeting the AAF requirement for the SCF ampler. Thi i due to the fact that the input ignal ampling ha already taken place before the ignal goe through the ZOH (ee Fig. 2.3). 36

49 2.4 -z Tranformation Method In Section 2.2, we arrived at the Switched-Capacitor Integrator (SCI) time contant in Eq. (.9), by the reitor approximation of a witched-capacitor. However, a we learnt in Section 2.3, the SCI frequency repone cannot be appropriately repreented uing the analog frequency variable (ee Fig. 2.4). Thi i eentially due to the fact that the input ignal undergoe ampling and hence another variable z i introduced [6]. The two variable are related a follow: z T f e e (2.6) Here, T i the ampling interval and f S thu the ampling frequency. The mathematical derivation can imply be obtained from the Laplace Tranform of the impule ampling operation in time-domain [6]. In order to compute the frequency repone, we replace the variable by jω d, which i the dicrete-time frequency variable. Hence, z e jdt e j2tf d e f j2 f d e fd nf j2 f (2.7) where, n i an integer. Eqn. (3) give u a very important reult. The dicrete-time filter frequency repone would be periodic with f S. Thi i indeed depicted in the trace (iii) and (iv) of Fig At thi point, we mut dicu the poible way for a Dicrete-Time Filter (DTF) ynthei. One way to yntheize the DTF i from the Continuou-Time Filter (CTF). Traditionally, there ha exited ignificant knowledge in the CTF theory, and it i intuitive to realize a DTF a a derivative of the ame. For thi, we mut derive a mapping between the 37

50 Figure 2.5: Figure howing the area under the curve uing Trapezoidal Integration. and z plane. The only contraint that exit are that mapping function mut be rational and it hould enure the tability criteria when tranforming from one plane to the other [6]. In baic circuit theory, a CTF can be treated a a Linear Time-Invariant (LTI) ytem which can be repreented by the following et of t order differential equation [9]: dxit dt N M ajxj t) j k ( bkwk i [, N] (2.8) Here, x i the tate variable of the ytem of order N. There are M excitation ource in the ytem, and are repreented by the calar w. For example, an LC tank excited by a ingle voltage ource would have N = 2 and M =, and thu it repone can be completely analyzed by two t order differential equation. Now, it i poible to write Eqn. (2.7) in a more implitic form [6]: 38

51 dxi( t) dt gi( t) (2.9) Taking the definite integral of (2.8) in one ampling period from NT T to NT, we get, NT x i gi t) NT xint T NT T ( dt (2.0) Now, the RHS can be evaluated uing variou numerical integration method to calculate the area under the curve. We will conider the Trapezoidal Integration Method, which i one of the mot accurate method known for numerical computation. In thi method, the curve i approximated by a traight line (Fig. 2.5) and hence the area i jut a um of the triangle and the rectangle and can be given by: NT T gi( t) dt 2 NT T g NT gint T i x T 2 NT xint T gint gint T i (2.) Taking the z-tranform of the above difference equation, we get, T z Xi( z) z Gi( z) (2.2) 2 Now, taking the Laplace Tranform of Eqn. (2.8) in the analog domain, we get, a Xi( a) Gi( a) (2.3) Thu, by comparing Eqn. (2.) and (2.2), we can arrive at the following relation in the analog and dicrete-time domain variable: 39

52 40 2 z z T a (2.4) The above -z mapping i alo known a the Bi-Linear Tranformation (BLT). Now, we can equate a = jω a and z = exp(jω d T) for a relation between analog and dicrete-time frequencie: 2 tan T T j e e e e T e e T j d T j T j T j T j T j T j a d d d d d d 2 tan 2 T T d a (2.5) The above equation ha a very ignificant implication. It can be een that all analog frequencie in the range (-, 0] can be mapped onto the unit circle of dicrete-time Table 2.: Variou -z tranformation method Integration Scheme -z Mapping Forward Euler z z T a Backward Euler z T a Mid-point (Lole Dicrete Integration) 2 z z T a Trapezoidal (Bi-Linear Tranformation) 2 z z T a

53 frequencie in the range (-π, 0]. Thu, theoretically peaking, it hould be poible to realize any pole/zero with the frequency ranging from DC to f S /2. Another intereting reult can be oberved for low dicrete-time frequencie and hence high-osr. i.e. ω d << 2/T. In that cae, ω a ~ ω d, and hence there i little difference between the analog and dicrete-time frequency repone. An intuitive explanation of the above phenomenon can be explained by Fig It can be een that if the ampling period T i decreaed for a given ignal bandwidth (and hence increaed OSR), the approximation would become more accurate. Thi low-frequency reult i indeed valid for all the other -z tranformation a well (ee Table 2.). It i left a an exercie for the reader to conclude that the SCI circuit in Fig. 2.2 i an embodiment of the Forward-Euler -z tranformation cheme. With thee fundamental in mind, we can now proceed to deigning an SCF for Type-III compenation. 4

54 Chapter 3 3. Specification for the Type-III SCF Deign 3. Small-ignal Repone of the Buck Converter The baic linear PWM-baed voltage-mode control of fixed-frequency Buck converter wa dicued in Section. (ee Fig..6). For thi, any perturbation of the duty cycle (Δd) of the witching converter i aumed to have a linear repone to it output voltage (Δv OUT ). The linearity hold true for frequencie much lower than the witching frequency (~ f SW /0). Fig. 3. how a implified chematic of the Buck converter, with equal reitance aumed for High-Side (HS) and Low-ide (LS) witche, given by R SW. Figure 3.: Simplified circuit chematic of a witch-mode Buck converter. 42

55 The open-loop repone of thi circuit i well tudied, and i given in [6] a: G vd 2 N v ( ) d OUT V IN 2 RL D RSW R LC RC ROUT Q N 2 N L C R 2D OUT C R OUT LC I R C OUT R R SW OUT RCC 2 2 N 2 RC ROUT R L D RSW Now, typically, R OUT >> R L, R C, R SW, to minimize conduction loe for any given load 2 N current requirement. Hence, we can implify the above equation a: G vd ( ) V IN RCC 2 2 N 2 N (3.) LC R 2 OUT N (3.2) RC ROUT LC Q N L R OUT LCR C RC OUT R L D 2 R SW Now, ubtituting ω N from (23), we get, Q L R OUT R C R OUT LC 2 C L SW L 2 R D R CRC RL D RSW R OUT LC In practical converter deign, the following relation between the time contant hold: L R OUT R C R L D 2 R SW C 43

56 Thi i alo an indirect conequence of the aforementioned aumption on the variou reitance in Fig. 3.. Hence, C Q ROUT (3.3) L At thi point, we will analyze the Eqn. (3.) (3.3) in more detail. From (3.), we learn that G vd ha a 2 nd order repone, which i intuitive becaue of the preence of LC tank. The natural frequency of ocillation i indeed governed by the LC (Eq. (3.2)). The quality factor (Q) i directly proportional to the load reitance (R OUT ) a een in Eq. (3.3). Thi again i intuitive ince a light-load condition would reult i mallet lo in the LC reonant tank, and highet Q. Finally, it i important to note that there i a LHP zero preent due to the load capacitor ESR, which can potentially reult in a phae-boot. Now, referring to Fig..6, we can ee that the compenator output (V COMP ) i fed to a comparator which generate the PWM ignal containing the duty cycle information for the Buck Converter. Since the duty cycle, D lie from [0, ], the modulator ha attenuation equal to the height/amplitude of the awtooth ramp waveform. Hence, the complete open-loop tranfer function (excluding the compenator) i given by: GT( ) M ( ) G vd V ( ) V IN SAW RCC VIN G( ) 2 2 VSAW 2 N N (3.4) Here, M() i the modulator gain given by / V SAW. For the compenator deign, for now, we will conider V IN = V SAW and hence G T () = G(). A can be een from Eq. (3.4), G() i largely a function of the variou circuit parameter of the Buck converter. 44

57 3.2 LC Filter Deign A can be een in the previou ub-ection, the LC filter largely dictate the open-loop frequency repone of the Buck converter. It mut be undertood that the primary function of thi filter i to attenuate the high-frequency witching content on node V SW and provide a low-ripple DC output voltage (Fig. 3.). We will firt focu on the inductor deign. The inductor ripple at a given witching frequency f SW i [6]: 2 f il D SW L DVIN (3.5) where, D (= V OUT /V IN ) i the teady-tate duty cycle of the converter. The inductor current ripple i generally choen to be 0 20 % of the rated full-load current. The higher the choen ripple, lower i the inductor value (hence ize), but larger the RMS loe in the witche for a given load current. Other conideration include low R L (for reduced loe) and that I L + Δi L hould have ufficient room below the inductor aturation level. Now we hall focu on the output capacitor deign. Note that in Fig..6 and 3., we have ignored the capacitor ESL. Thi i due to the fact that ceramic capacitor are choen for low EMI and footprint requirement. Now, we aume that the inductor DC current flow through the load reitance, while the higher frequency ripple current flow through the output capacitor. While the capacitor integrate thi ripple current, it ESR will directly reflect it on top of the output voltage. Hence, minimizing R C i an important conideration while chooing the output capacitor. The total output voltage ripple i given by [6]: v OUT vout, C vout, ESR 45

58 Table 3.: Power-Stage deign for Buck Converter at f SW = MHz Switching Frequency (f SW ) Input Voltage (V IN ) Output Voltage (V OUT ) Full-Load Current (I OUT ) Inductor (L/R L ) Capacitor (C/R C ) Double-Pole Frequency (f LC ) ESR Zero Frequency (f ESR ) MHz 3.3 V.0 V.5 A μh/0 mω 30 μf/5 mω 29 KHz MHz v OUT il 8 fswc RCi L (3.6) We can thu calculate a range of realitic L, C and R C value from the ripple requirement and the witching frequency from Eqn. (3.5) and (3.6). 3.3 Type-III Analog Compenator Deign We decribed the baic Type-III filter tranfer function in Eq. (.6) in Section.2. However, we firt need to acertain the open-loop Buck converter tranfer function a given in Eqn. (3.) (3.4). For thi, we can imply pick a reference deign for our target application, uch a the one in [7]. In [7], an output voltage (V OUT ) of.5 V i provided for a full-load current rating of.5 A (I OUT ) from an input voltage (V IN ) in the range V. The Buck converter witche at a nominal frequency of f SW = MHz and ha a fully-integrated driver and MOSFET deign. At thi point, we will conider a nominal input voltage of 3.3 V (V IN ), to eae our LC filter and hence the compenator deign complexity. The LC filter deign i done 46

59 Figure 3.2: Snaphot of the iotool howing complete open-loop repone of Buck converter with Type-III compenation. for 0 % current and < % voltage ripple requirement, uing Eqn. (3.5) and (3.6). Table 3. ummarize the power-tage deign. With the above information, it i poible to deign a Type-III filter compenation for a cloed-loop Unity-Gain Bandwidth (f UGB ) of f SW /0 (~ 00 KHz). Thi can eaily be done uing the viual interface (iotool) provided the MATLAB a a part of the Control Sytem Toolbox [20]. It can be een from Fig. 3.2 that a cloed-loop bandwidth of 04 KHz i achieved with a phae margin of The LC double pole and ESR zero frequencie are indicated at the frequencie mentioned in Table 3.. It can be een that ince ESR zero i 47

60 Table 3.2: Type-III analog filter component for pecification in Table 3. C C 2 C 3 R R 2 R 3.4 nf 400 pf 20 pf Ω 5.6 KΩ 4 KΩ preent at a frequency 0 time higher than the cloed-loop bandwidth, it ha little contribution to the phae margin. In deign where the ESR zero i placed cloed to loop bandwidth by employing electrolytic capacitor, Type-II filter (Integrator + one pole/zero pair) baed compenation uffice. Referring to Type-III tranfer function in Eq..6, the integrator bandwidth i 50 KHz; the two zeroe are placed at 20 KHz and the two pole at 550 KHz. Correponding to thee filter pecification, the component value for the Type-III filter in Fig..9 are hown in Table 3.2 for a witching frequency, f SW = MHz. It i clear to ee from Fig. 3.2 that variou frequencie (or time contant) for the Type-III filter will cale linearly with f LC to enure tability. Now, a can be deduced from (3.6), f LC cale linearly with f SW to enure the ame V OUT ripple magnitude, if the capacitor ESR (= R C ) can be neglected for ceramic output capacitor. Thi i indeed the motivation for deigning a Type-III filter in which the variou time-contant cale linearly with the witching time-period of the Buck converter. With the deign pecification for the reference Type-III filter clear, we can now proceed to the SCF implementation of the ame. 48

61 Chapter 4 4. Theoretical Conideration for the Type-III SCF Deign 4. Propoed Strategy From the dicuion in Section 2. and 2.2, it i clear that the Type-III SCF cannot be realized imply by replacing reitor by Switched-Capacitor Network (SCN) in the analog filter of Fig..9. If ay, the reitor R wa replaced by an SCN, at the intant of witch diconnection, the network would ee infinite impedance looking into the left plate of C. Hence, no charge haring (and information) tranfer would be poible, rendering the circuit ineffective. Thi ituation alo hold true for the reitor R 3, and thu it replacement by an SCN i alo not poible. A a next tep, we firt break the Type-III filter of Fig..9 into an equivalent circuit wherein all the reitor are connected between a driven node, and the feedback node of the amplifier. It mut be noted that in Fig..9, only the reitor R 2 atifie thi criterion. Thu, we arrive at the circuit configuration in Fig. 4.. It mut be hereby undertood that thi equencing and partitioning of the Type-III tranfer function i the mot critical tep in the ynthei of the propoed Type-III SCF prototype. Thu, we arrive at a cacade of three t order filter. The tranfer function of thi 3-tage filter circuit i given a: H VCOMP3( ) ) HC( ) HC 2( ) HC ( ) (4.) VOUT( ) C( 3 The individual tranfer function are given a follow: 49

62 Figure 4.: Circuit chematic emulating the Type-III filter in Fig..9. H H H C C2 C3 ( ) ( ) ( ) V V OUT ( ) ( ) R 0C 0 0 COMP (4.2) V V COMP ( ) R ( ) R 2 R R 2 C C 2 2 COMP2 (4.3) V V COMP2 ( ) R ( ) R 22 2 R R 2 22 C C 2 22 R R COMP3 (4.4) It can be een that the t tage perform the integration function; while the latter two tage are t order high-pa filter. Thi filter can be ued a a reference for any SCF derivative that might arie out of the ame. Baed on the deign requirement outlined in Section 3.3, the following relation hold: R R 2 22 R 0 R R R rad / rad / 2 (4.5) (4.6) 50

63 rad / 2 22 (4.7) Now, we can replace each of the reitor by SCN, to achieve the aforementioned time contant given in Eqn. (4.5) (4.7). In addition, we hall arrive at fully-integrated frequency-calable filter architecture, baed on the dicuion in Section 2.2. However, before we do that, we need to undertand the impact of the choice of ampling rate for the filter which i critical for the ynthei of thi Type-III witched-capacitor filter. 4.2 Tradeoff in choice of Sampling Frequency (f S ) A we learnt in Section 2.4, by increaing the clock frequency (and hence the ampling rate) in an SCF, it OSR i increaed for an input ignal of fixed bandwidth. Thi ha a direct benefit of the eae of the deired filter realization ince the approximation become more accurate. In addition, a could be een from Fig. 2.4 in Section 2.3, it would alo eae-up the deign requirement for the Anti-Aliaing Filter (AAF). However, increaing f CLK (and hence f S ) ha it diadvantage a well. An expreion for the witched-capacitor time contant (τ) wa derived in Eq. (2.4) in Section 2.2. We hall rewrite it here for convenience: R EQ C 2 fs C C 2 C T C 2 It can be een that increaing f S would reult in a larger capacitor pread (= C 2 /C ) and hence increaed area. In addition, with a fater clock and higher capacitance to drive, the amplifier would need much higher bandwidth (and hence power) to fulfill it fater ettling requirement [2]. In addition, the witche need to made larger for fater witching peed. 5

64 Thi degrade accuracy and inject noie (clock feedthrough and charge injection) into the SCF. Finally, a fater clock would conume higher dynamic witching power and would require ophiticated circuitry for jitter control. To conclude, a high-peed clock i clearly a power, area and noie penalty for the filter. However, if a low-frequency clock i choen, the concern regarding accurate filter tranfer function realization and prevention of aliaing ditortion need to be taken care of. We will try to tackle thee iue in the next two ub-ection. 4.3 Bi-Linear Tranformation (BLT) In Section 2.4, we learnt the following relationhip between the analog and dicretetime frequency domain when uing the Bi-Linear -z Tranformation. a 2 dt d tan 2 fs tan T 2 2 fs f a T tan f f fs S d f dt tan (4.8) Now, we alo learnt that it i poible to realize any pole/zero frequency uing BLT (in the dicrete domain) in the range [0, f S /2). Hence, it i clear by examining Eqn. (4.5) (4.7) that the pole frequencie of 550 KHz given by (4.7) would be the limiting factor in chooing the ampling rate. Now, it would eem reaonable to chooe a ampling rate (f S ) of 2 MHz to realize thi aforementioned pole frequency. Indeed thi i the minimum realitic f S that can be targeted, and hould reult in the mot power and area efficient olution. However, with an OSR < 4 52

65 Figure 4.2: Switched-capacitor derivative of the analog filter hown in Fig. 4.. for the highet frequency pole, the reference analog filter frequency (f a ) would need to be pre-warped. A can be een from Eq. (4.8), with f d = 550 KHz and f S = 2 MHz, the correponding f a = 745 KHz. It mut be undertood that the pole/zero frequencie in Eqn. (4.5) and (4.6) do not need any pre-warping ince their OSR > 40. Finally, we mut add that we have only choen the ampling rate (f S ) which may or may not be equal to the clock frequency (f CLK ). Thi i becaue it i largely dependent on the circuit-level ynthei of every reitor (in Fig. 4.) by a Switched-Capacitor Reitor (SCR), which will be dicued in detail in Chapter 5. We thu get an equivalent circuit a hown in Fig Anti-Aliaing Analyi In the preceding ection, we choe a ampling frequency (f S ) for the SCF, which i effectively twice the witching frequency (f SW ) of the Buck converter. Now, the input to thi filter i the output voltage of the Buck converter (V OUT in Fig..6). Thi voltage pectrum conit of baeband content (up-to the LC filter cutoff frequency) and high frequency 53

66 Figure 4.3: Spectral content due to ampling operation in the SCF of Fig. 4.2 without any pre-filtering and f S = 2 f SW. witching harmonic. The tronget tone obviouly exit at f SW, and depend on the voltage ripple. The ituation i aptly decribed in the frequency domain (excluding the SCF repone) in Fig With the wort-cae ripple voltage of 5 %, we achieve a bet cae -26 db SNR. Clearly, thi doe not meet the -40 db SNR anti-aliaing requirement a dicued in Section 2.3. The ripple (and hence noie) power can be decreaed by placing tighter requirement on 54

67 Figure 4.4: Spectral content due to ampling operation in the SCF of Fig. 4.2 with analog integrator a an AAF and f S = 2 f SW. the LC filter deign, uch a low ESR, ESL and ufficiently low LC frequency. However, that would defeat the purpoe of our current approach ince we claimed in Section. that the linear PWM control i generally table with all LC filter deign (keeping in mind only 55

68 Figure 4.5: SCF architecture for f-calability with integrator a an AAF. the power-tage requirement). Thi wa lited a a ignificant benefit compared to the nonlinear control trategie (ee Table.), and thu cannot be compromied upon. Interetingly, while the cloed-loop tability would improve with a larger output capacitor ESR in Type-III compenation by increaing the phae margin (ee Fig. 3.2), it would increae the V OUT ripple and dirupt the functioning of the SCF in Fig In order to make the filter requirement independent of the LC filter deign, we can introduce ome ort of analog pre-filtering (lowpa/notch) to attenuate the ripple magnitude. However, thi pre-filter can potentially interfere with the deired Type-III filter repone, and epecially the phae repone. It mut be undertood that any phae degradation can everely impact the tability of the witching converter. An alternate olution to thi problem would be to make the integrator tage a fullyanalog deign. If the integrator bandwidth (/2πτ ) i placed at a maximum value of f SW /0, it 56

69 would provide an additional -20 db of attenuation to the witching and higher order harmonic, and would thu help meet the anti-aliaing requirement of the SCF tage that follow. Thi analyi i preented in Fig The problem that arie out of thi deciion i regarding the implementation of the integrator. We would till require an integrator that how low variability with Proce, Voltage and Temperature (PVT) variation, and can be tuned with the witching frequency. Clearly, an Active-RC integrator i not an option. Hence, we propoe a G m -C integrator configuration that can be tuned uing the ame configuration bit a the Buck converter clock, a hown in Fig Thee bit are uer-programmed which are generally ued to decide the operating frequency of the witching converter. The detail of the G m implementation for PVT inenitivity and linear calability will be dicued in Chapter SCF Cacading Problem The SCF architecture in Fig. 4.5 i a derivative of the analog Type-III filter in Fig. 4.. It can be een that there exit a continuou-time path from V OUT to V OUT3, a a reult of direct capacitive coupling. While thi topology i perfectly valid in the continuou-time verion, it i problematic in SCF. In low-pa SCF, it would reult in low top-band loe [22]. Thi effect i alo known a ignal leakthrough in SCF [23]. It wa oberved that in high-pa SCF, a i the current cenario, the impact of ignal leakthrough i more evere, and reult in aliaing ditortion of the lat-tage SCF repone. We have verified thi effect in two different imulator namely, Spectre-RF [24] and SWITCAP [25]. Although thi effect i reported in [23], a uitable explanation wa found lacking. Our explanation i a 57

70 Figure 4.6: SCF architecture for eliminating the SCF cacading problem uing SHA. follow: When the t tage SCF produce a tep output voltage V OUT2, it i coupled and amplified by C 2 and C 22 to produce V OUT3, ince the 2 nd tage SCF i a high-pa filter (HPF). Now, thi high-frequency content on V OUT3 will imply ditort the frequency repone of thi SCF due to aliaing. One way to reduce thi effect i to reduce the high-frequency content on V OUT2. Thi can be accomplihed by reducing the UGB of the amplifier driving V OUT2 and by increaing the witch reitance of the SCN in t tage SCF. However, thi make the frequency repone highly dependent on the witch reitance, which can vary by more than an order of magnitude over Proce, common-mode Voltage and Temperature (PVT) variation, and defeat the baic purpoe of uing an SCF. An alternate trategy a lited in [22] and [23] i to break the continuou-time path between the two SCF. Thi can be done by uing a Sample-and-Hold Amplifier (SHA) circuit operating at the ame ampling rate a the SCF. Hence, we get the SCF architecture a hown in Fig The frequency repone of an SHA operating at a ampling rate f S 58

71 Figure 4.7: SHA magnitude and phae repone for f S = 2 MHz. (=/T) i given by: H jdt 2 SHA( jd) Te in dt 2 dt 2 (4.9) The SHA repone i repreented uing the MATLAB plot a hown in Fig It can be een the SHA lead to magnitude degradation due to the inc effect, with null at multiple of f S. However, for f S = 2 MHz, the magnitude degradation at the deired cloed-loop 59

72 bandwidth, f C = f SW /0 = f S /20 (~ 00 KHz) i negligible ~ db and only ~ -0.9 db at 500 KHz. The SHA effect i more pronounced in term of phae degradation. The phae-lag i eentially that of T/2 in the dicrete-time domain. It can be een that the phae degrade by 9 at 00 KHz and by 45 at 500 KHz. Thi can everely impact both the phae and gain margin of the cloed-loop repone. The impact and workaround will be dicued in greater detail when we perform the complete SCF imulation in Chapter 7. 60

73 Chapter 5 5. Practical Conideration for the Type-III SCF Deign In thi ection, we will dicu the implementation detail of the variou block of the SCF architecture (Fig. 4.6) in Texa Intrument (TI) 0.35-μm BCD proce. Although thi proce offer variou tate-of-the-art active/paive, we have only ued the tandard BiCMOS option for wider acceptability. All deign are characterized in the temperature range [-40, 25] C, and temperature compenation ha been employed, wherever neceary. Finally, baed on the variou deign choice made keeping the power, area and peed tradeoff in mind, we alo how the gradual evolution of thi Type-III SCF architecture. 5. G m -C Integrator The integrator front-end in the SCF architecture i a crucial block that help implement both the Type-III filter and the AAF for the ucceeding SCF tage. Hence, it ha the following deign requirement:. Linear Scalability: Since we are targeting frequency-calable filter architecture, the linear calability of the integrator bandwidth with the witching frequency i eential. 2. Proce, Voltage and Temperature (PVT) Independence: For a fully-integrated deign, the integrator hould have little/no enitivity to PVT variation. 3. Input Common-Mode Range (ICMR): The ICMR requirement are placed due to the ofttart function in the Buck converter, which i eential for a afe tartup with controlled duty cycle (and hence inductor current). In oft-tart, the oft-tart ignal (V SOFT ) i 6

74 ramped up-to V IN in ~ m to allow the Buck converter to reach it teady-tate operating point lowly. Now, the bandgap voltage generator (V BGAP ) provide a fixed on-chip reference voltage, while the oft-tart ramp (V SOFT ) i provided externally. Thi ramp hould bypa V BGAP when V SOFT < V BGAP, while V BGAP dominate otherwie, to provide V REF. Thu, V REF = Min (V SOFT, V BGAP ). Thi operation can eaily be achieved in the analog domain by uing a 3-input buffer a hown in Fig. 5.. Clearly, for both the G m and it buffer tage, the minimum ICMR range between 0 and V BGAP. In-fact, thi requirement i true for all amplifier in the ignal chain. Figure 5.: SCF architecture incorporating the reference voltage elector for oft-tart of the converter. 4. Differential Linearity: Thi requirement i rather non-intuitive. The input ignal to the filter in Fig. 5. i the output of the Buck Converter (V OUT in Fig..6). During oft-tart 62

75 and line/load tranient, the V OUT voltage fluctuate above/below it teady tate value, given by V REF. Thi fluctuation i een by the G m -C integrator tage a a large input differential ignal, and can be about mv, if the cloed-loop tability i enured. Thu, in the wort-cae, the integrator hould enure it large-ignal linearity for atleat 200 mv of differential input ignal acro PVT variation. With the deign requirement firmly etablihed, we proceed to Fig. 5.2 which how the G m -C filter chematic. The buffer amplifier i neceitated by the need to drive the ucceeding SCF tage, and thu a fat tranient repone. It can be een that V COMP ha no DC feedback, but it operating point i et once the filter operate in cloed-loop configuration with the Buck Converter. The G m tage in feedback enure that the commonmode voltage on V FB doen t drift, which directly impact the cloed-loop Figure 5.2: G m -C integrator tage with buffer chematic. 63

76 Figure 5.3: PTAT current/voltage generation circuitry in a BiCMOS proce. regulation of the witching converter. The tranfer function for the above circuit can be calculated from the equivalent reitance of the tranconductor: R G G EQ RIN ROUT (5.) m m where, R IN /R OUT i the input/output impedance of the tranconductance amplifier, which can be made large (MΩ range). The equivalent integrator tranfer function i given by: HI( ) REQC 0 Gm C (5.2) 0 The aumption for the above are that the buffer amplifier ha bandwidth much larger than the integrator bandwidth, and that the capacitor C 0 i much larger than the paraitic 64

77 capacitance preent on the input of the buffer and tranconductance amplifier. Finally, a dicued in Section 4.4, the integrator bandwidth i targeted to be 00 KHz for f SW = MHz. We chooe a Bipolar-input baed tranconductor due to it excellent propertie of being linearly calable with the bia current. The mall-ignal tranconductance (G m ) of Bipolar i given a: G m IC kt, VT (5.3) VT q Here, I C i the collector current and V T i the thermal voltage. The G m i completely independent of any proce parameter, and depend only on the bia current. It can be een that V T i Proportional-To-Abolute-Temperature (PTAT). Thu, if we can make the collector current PTAT, the G m can be made temperature independent a well. A PTAT current ource i readily available from the bandgap reference circuit ued for generating the on-chip temperature-compenated reference voltage, V BGAP. Conceptually, thi i hown in Fig The PTAT current and voltage i given a: I PTAT VT RBG2 lnm, VPTAT VT lnm (5.4) RBG RBG where, m i the ratio of the emitter area of the PNP bipolar tranitor in Fig Now, keeping the mind the ICMR requirement, a PMOS input-baed folded-cacode amplifier would be a reaonable choice for an all-cmos deign [26]. However, a dicued before, we require a PNP-input baed tructure for linear calability, which ha the problem of finite input reitance (R IN ) [27]. Thi ha the advere effect of loading the G m tage in feedback, and impact the equivalent tranconductance of the filter (ee Eq. (5.)). Hence, we avoid the 65

78 Figure 5.4: A BiCMOS Operational Tranconductance Amplifier (OTA). PNP-input folded-cacode architecture and intead ue a level-hifter t tage (ourcefollower) with PMOS tranitor, to drive the 2 nd tage PNP tranconductor, a hown in Fig The 3 rd tage convert the differential current ignal into a ingle-ended voltage output (V OUT in Fig. 5.4). In addition, a cacoded output tage provide a large output reitance, a i required by Eqn. (5.). The voltage gain of the t tage mut be included to calculate the effective tranconductance of thi OTA. Since the firt two tage are fully-differential, we can perform the half-circuit analyi for a fully-differential input mall-ignal: G m, eff A Gm (5.5) A g mp r (5.6) 66

79 (a) (b) Figure 5.5: (a) Concept of a multi-tanh doublet. (b) G m compenation [28]. Here, g mp i the mall-ignal tranconductance of the t tage PMOS and γ i it bodyeffect parameter [26]. g mp can be expreed in term of the tranconductance parameter (K P = μ P C OX ) and the drain current I D = I PTAT : g mp 2KP ID 2KP IPTAT (5.7) The equivalent reitance at the output of t tage i the input reitance of the PNP given by r π. Thi reitance i related to the current-gain (β) of the BJT and it tranconductance (G m ): r V Gm I T C V I T (5.8) PTAT 2 Now, from Eq. (5.6), the factor g mp r π need to be made much larger than, to make A largely independent of the proce parameter decribed in Eq. (5.7) and (5.8). However, r π i dependent on β, which decreae with decreaing temperature. Hence, at low temperature (~ -40 C), the effective tranconductance (G m,eff ) decreae. Thi will reult in a light decreae 67

80 Figure 5.6: Propoed circuit to replace the G m tage in Fig. 5.5 (N = 2). of the open-loop bandwidth of the converter, and poibly an increae in the phae/gain margin. It mut be hereby undertood that enuring a contant large-ignal G m over PVT variation i a difficult propoition. In addition, the C 0 variation (ee Eqn. (5.2)) till need to be compenated via trimming. With the OTA being linearly calable, PVT compenated and meeting the ICMR requirement, we proceed to it differential linearity analyi. The large-ignal differential output-current (i) to input-voltage (v) characteritic of a BJT differential pair (uch a the PNP-baed G m tage in Fig. 5.4) i a tanh function [28]: i I C v 2V I v tanh 2V tanh PTAT 2 (5.9) T T The large ignal tranconductance can thu be given by: 68

81 (a) (b) Figure 5.7: DC repone howing differential (a) output current (b) tranconductance, with large-ignal differential input for the circuit in Fig. 5.6 for N = 4 cae. G I 2V v 2V PTAT 2 2 m, L ech (5.0) T T The large ignal tranconductance (Eq. (5.0)) for OTA in Fig. 5.4 degrade by more than 50 % in the ±0 mv range. In addition, a i een in Eqn. (5.9) and (5.0), the wort cae for linearity i at the lowet temperature = -40 C. Thi OTA linearity performance i not ufficient for the Buck converter tranient repone requirement, during oft-tart and line/load tranient. One way to improve linearity, while retaining the other performance benefit, i to ue the multi-tage tanh compenation a decribed by Gilbert in [28]. In thi 69

82 cheme, variou BJT-baed OTA are connected in parallel by hifting their DC characteritic by an offet voltage (Fig. 5.6a). The offet can built-in by uing aymmetrical device in each differential pair in a multi-tanh configuration. The offet voltage i thu given by: V OS A VT ln (5.) where, A i the emitter area ratio in the differential pair (Fig. 5.6a). The variou g m combine in parallel to reult in a flat-zone, reulting in high linearity (Fig. 5.6b). The problem with thi circuit i the exploion of area in cae the linearity need to be extended beyond ±00 mv. A an example, we deigned a quintet multi-tanh cell, having a linearity up-to ±00 mv differential ignal (at nominal temperature of 27 C), and already reached A = 55. Thi i clearly due to the logarithmic dependence of offet voltage (and hence the linearity range) on the ratio of the emitter area (Eq. (5.)). The olution we have adopted i a derived one from an all-cmos verion in [29]. Fig. 5.7 illutrate the baic circuit replacing the tranconductance tage in Fig It can be een that there are two PNP differential pair and one NPN differential pair. Thu, if there are N PNP-pair, correpondingly there will be N NPN-pair. It can thu be proved that the equivalent large-ignal tranconductance of thi configuration i given by: G 2 IPTAT 2 2 v ech 2N VT 2 2N VT m, L (5.2) Hence, the linearity performance of thi cell i improved by a factor of 2N. Thu, it i eventually a technique to divide the input differential voltage acro variou differential pair. The larger the value of N, the better will be the linearity and wore will be amplifier 70

83 Figure 5.8: SCF architecture including the integrator tuning cheme uing I DAC. offet. In our deign, we have choen a value of N = 4, which yield a 3σ offet of 2 mv in Monte Carlo Simulation acro PVT variation. Fig. 5.7 how the large-ignal differential output current and tranconductance at three different temperature of -40, 27 and 25 C for I PTAT2 = 2 27 C. In the wort cae at -40 C, the G m,l degrade by 28 % from it nominal value at a differential input of ±200 mv and lewing i prevented up-to ±700 mv. A we will ee in Chapter 8, thi performance i found to be acceptable for the Buck converter cloed-loop tranient repone. Another effect to be noted from Eq. (5.2) i the reduction of mall-ignal G m by a factor of 2N. Thi ha the important benefit of reduction of C 0 by the ame factor (Eq. (5.2)), and reult in ignificant area-reduction. It mut be undertood that the only way to reduce G m in a Gilbert cell (Fig. 5.5) i by reducing I PTAT2 to the na range (Fig. 5.4). However, thi can degrade the frequency repone of the integrator by introducing paraitic pole (mainly the 7

84 Figure 5.9: Circuit element for realizing BLT and it aociated witch phae. Figure 5.0: Improved BLT circuit element for ymmetry and reduction of paraitic. mirroring pole) at low frequency (~ f SW ). Thee pole can directly reult in a reduction of the phae margin at the converter cutoff bandwidth f C ~ f SW /0, and i highly undeirable. With the OTA architecture fully developed, it can be een from Eqn. (5.2) and (5.2) that the integrator bandwidth can be linearly tuned with a PTAT current baed current DAC (I DAC ). Thi obervation lead u to the updated SCF architecture chematic a hown in Fig

85 5.2 SCF # There are two major challenge to the circuit realization of the high-pa SCF # (Fig. 5.8). Thee are dicued in the following two ub-ection: 5.2. High-frequency pole implementation It wa concluded in Section 4.3 that uing a ampling rate f S = 2 MHz would help realize the high-frequency pole at 550 KHz uing Bi-Linear -z Tranformation (BLT). In [22], a witched-capacitor circuit element which could yntheize the BLT wa propoed, a hown in Fig. 35. It can be witching capacitor perform the ampling operation in both halfcycle of the clock and the ampling time period, T = /f S = /2f CLK. Hence, the ampling rate i doubled for a given clock frequency, and we can thu chooe f CLK = f SW = MHz. Now, the problem arie due to the bottom-plate capacitance (C BP in Fig. 5.9), which can be 5 0 % of the main witching capacitor. Thu, C BP interfere with the time contant being realized. A more evere problem occur due to aymmetry in the witching behavior can reult in puriou tone in the output pectrum at harmonic of the ampling rate of C BP, given by f SW. To alleviate thee problem, we propoe a imple fix in Fig. 5.0, in which both the circuit ymmetry and reduction of bottom-plate capacitance (by 50 %) i achieved. Now, we implement both SCR and SCR2 (Fig. 5.8) with the element hown in Fig. 5.0, to implement both the low-frequency zero and high-frequency pole. Thu, we get the circuit hown in Fig. 5., with the witch phae a hown. The SCF tranfer function can be evaluated uing the conervation of charge principle applied at the iolated node V FB2. We can aume that τ = 0 (Fig. 5.) for implicity. The initial charge of the ytem of 73

86 Figure 5.: SCF # circuit chematic with the witching phae indicated. capacitor at t = NT T (end of phae Φ 2 ) i given by: CCaV OUT NT TC2C2aV OUT NT T qi ( t NTT) 2 The final charge t = NT (end of phae Φ ) i given by: CCaV OUT NT C2 C2aV OUT NT q ( t NT) f 2 74

87 Equate the initial and final charge by the law of conervation of charge: C CaV OUTNT C2C2aV OUT2NT CCaV OUTNT T C2 C2aV OUT2NT T Rearranging like term for V OUT and V OUT2, we get, C CaV OUTNT CCaV OUTNT T C2 C2aV OUT2NT C2 C2aV OUT2NT T Take the z-tranform of thi dicrete-time difference equation to get: C Ca z C CaV OUT z) z C 2 C2a C 2 C2a V V H VOUT ( ) ( 2 z C z Ca z VOUT( z) C 2z C2a z VOUT 2( z) OUT 2 OUT ( z) ( z) C C 2 C C z Ca z z C2a z C C C C C C 2 z Ca z z C2a z a a SCF ( z) (5.3) 2a 2 2a z z z z It can be een that the tranfer function i indeed a bilinear tranformed pole/zero pair. We will rewrite Eqn. (4.3) - (4.7) here which are the reference equation for thi SCF deign in Eq. (5.3): HC 2 R ( ) R

88 rad / 3, rad / 2 The pole frequency ha been increaed from 550 to 745 KHz due to the effect of pre-warping in BLT (ee Section 4.3). Now, we can do the -z ubtitution uing Eq. (2.3) in H C2 () to get the reference tranfer function for H SCF (z): a 2 T z z 4 T SW z z where, T SW i the witching time period of the Buck Converter. Thu, H C2 R ( ) R 2 4 T 4 T SW 2 SW z z z z (5.4) For a DC gain equal to unity, we can chooe C a and C 2a to be unit capacitor (for target matching requirement). Finally, C and C 2 can be calculated by comparing (5.3) and (5.4) and performing coefficient matching. In our deign, we have choen C a = C 2a =.25 pf, C 2 = pf and C = 40 pf Effect of Finite Opamp Gain-Bandwidth In the foregoing analyi, we have aumed that amplifier i ideal with infinite gain and bandwidth uch that the feedback node i alway at virtual ground. However, a can een, the above pecification for the amplifier can never be met, and hence the filter deviate from it ideal repone. Thi i epecially true for high-pa filter, wherein the highfrequency amplification hould, intuitively, get limited by the amplifier Gain Bandwidth 76

89 Figure 5.2: A t order analog high-pa filter with finite Gain Bandwidth Opamp. (GBW). Thee effect and more are quantified in greater detail in thi ub-ection. Fig. 5.2 how the example of a t order high-pa filter with a finite GBW amplifier. Now, we can readily write the following relationhip for thi cae under conideration: Z R,2,2( ) ;,2 R,2C,2,2 The feedback factor i given a: B( ) B 2 0 ; 2 B 0 R R 2 (5.5) Now, with V FB no longer a virtual ground node, we can write the following uing KCL: V FB ( ) Vo( ) Vi( ) V Z 2( ) Z ( ) FB ( ) 77

90 78 However, the amplifier maintain it input/output characteritic. We alo aume a imple ingle-pole ( 0 ) model for the amplifier under conideration. 0 0 ) (, ) ( ) ( ) ( A A A V V o FB ) ( ) ( ) ( ) ( ) ( ) ( 2 A A Z Z V V o i Thu, we can now calculate the filter tranfer function in term of A() and B(): ) ( ) ( ) ( ) ( ) ( ) ( ) ( B A B A V V H i o (5.6) The above i a very fundamental relationhip. Now, we need to ubtitute A() and B() to evaluate H(). However, ince the expreion become too complex, we will olve for the numerator (N()) and denominator (D()) eparately ) ( ) ( ) ( B A B A N (5.7) ) ( ) ( ) ( B A B A D ) ( A B B B A B D

91 79 In the example HPF, the zero i located at a frequency much lower than the pole. Thu, τ >> τ 2. In addition, the amplifier DC gain i much larger than the DC feedback factor (A 0 >> B 0 ). Hence, we ue thee relation for approximation: ) ( B A B B A D (5.8) We can combine (53) and (54) to finally calculate H(), ) ( ) ( ) ( A B A B A B B D N H Now, we will ue the final approximation that the amplifier GBW i much larger than the pole frequency (/ τ 2 ): ; A B B A eff B A B B H _ ) ( (5.9) where, 0_eff i the effective GBW of the amplifier. The above i a 2 nd order under-damped repone characterized by the following parameter: ; B A B A N (5.20) There are everal important obervation from Eqn. (5.9) (5.20): i. The zero frequency i preerved and i the ame a / τ.

92 ii. The pole frequency i not preerved. The pole i now complex and i preent at the geometric mean of the amplifier effective GBW ( 0_eff ) and zero frequency (/ τ ). iii. The natural frequency of ocillation (ω N ) and the damping factor (ζ) are a function of A 0 0, B 0, τ and τ 2. Of thee parameter, B 0, τ and τ 2 are tightly controlled in the SCF realization of HPF in Fig. 38. However, A 0 0 (GBW of the amplifier) can vary over PVT variation. Thu, if we can enure that the filter meet the deign pecification for the wort-cae minimum amplifier GBW acro 3σ PVT variation. Since the amplifier GBW will only be greater than thi minimum value, the complex pole will have a higher frequency and damping factor a dictated by Eq. (5.20). Hence, the cloed-loop tability will be enured Opamp Deign Keeping the foregoing analyi in mind, we enured that the filter deign would be acceptable for a wort-cae Opamp GBW = 20 MHz. The firt tep for deigning thi Opamp would be to undertand the loading requirement. For the high-pa SCF hown in Fig. 5., the equivalent loading i C 2 + C 2a = 2.25 pf. Add to thi another pf of the ucceeding ample-and-hold tage, and we get 3.25 pf. Now, we deign thi amplifier for a wort cae loading, C L ~ 4 pf, thu giving ome deign margin. The Opamp chematic i hown in Fig It ha a differential folded-cacode input tranconductor pair for low ICMR requirement dicued in Section 5.. The cacoded output from the t tage alo help in enuring high DC gain (> 80 db). Finally, we chooe a floating cla-ab output tage which can adequately drive the load capacitance C L, without limiting the lew-rate [30]. The lew- 80

93 Figure 5.3: A folded-cacode amplifier with cla-ab output tage. rate i thu limited by the total compenation capacitance driven by the input tail current: SR CC CC 2 (5.2) IPTAT 3 The dominant pole i preent at the output of t tage (V OUTMA,B ) ince it ha the larget output impedance (R OUT ). In addition, compenation capacitor C C and C C2 undergo miller multiplication by the 2 nd tage in mid-band frequencie to preent a large effective capacitance at V OUTMA,B. The target GBW of thi amplifier i given by: m GBW (5.22) 2 CC CC 2 G where G m i the differential mall-ignal tranconductance of the input pair. Thi expreion i obtained clearly by uing a ingle-pole approximation for the amplifier. However, there 8

94 Figure 5.4: Monte-carlo output for AC repone imulation of Opamp in Fig

95 Figure 5.5: Monte-carlo output for tep repone imulation of Opamp in Fig lie a non-dominant pole at the output node (V OUT ) driving a large capacitor (C L ). The location of thi pole i given by: G C 2 C C G C m 2 C m 2 P 2 K ; P 2 L PAR L GBW (5.23) where G m2 i the mall-ignal tranconductance of the output tage, and C PAR i the total paraitic capacitance preent on V OUTMA,B. Now, it can be een the non-dominant pole frequency i extended by K time uing thi compenation cheme compared to what would have been feaible with the tandard Miller compenation [26]. Thu, in miller compenation, 83

96 Figure 5.6: SHA implementation a a cacade of two THA. typically a RC compenation i ued to non-dominant pole cancellation by a LHP zero to extend the amplifier GBW, and achieve ufficient phae margin (45 90 ) for local tability. However, ince the RC time contant can vary by ±40 %, the miller-compenated amplifier can require either external compenation component or trimming. With thi cheme, ince both the load and compenation capacitor are of the ame type (Poly Oxide - Poly2 capacitor), they tend to track each other over PVT variation. Finally, a PTAT bia current ource i ued to compenate for variation in variou MOS tranconductance over the entire temperature range (ee Eqn. (5.22) and (5.23)). Fig. 5.4 how the output for Monte-Carlo imulation (abolute and relative proce variability) for the open-loop AC repone of the Opamp in Fig. 5.3 at three different temperature of -40, 27 and 25 C. It can be een that the wort-cae tability i enured with -3σ Phae Margin (PM) of 50. In addition, the wort-cae Unity-Gain Bandwidth (UGB: ame a GBW) of the amplifier i 20.6 MHz. Fig. 5.5 how the repone of the amplifier to a 0.5 V input voltage tep (in n), under the condition jut decribed. The 84

97 Figure 5.7: A rail-to-rail amplifier with cla-ab output tage. amplifier ettle well within the half witching period (T SW /2 = 500 n). To enure a nice lewing repone, C C2 (< C C ) i ued, which act a high-frequency bypa and improve the large ignal repone. It i alo important to undertand here that the large ignal repone would improve for maller and lower tep input, which would be a more realitic operating condition for thi Opamp. Finally, it mut be mentioned that thi performance for the amplifier i achieved by conuming only 00 μa of tatic current at nominal temperature (27 C). 5.3 Sample-and-hold Amplifier (SHA) The Sample-and-Hold Amplifier (SHA) i really a cacade of two Track-and-Hold Amplifier (THA), operating on the complementary phae of a clock. While there exit everal poible implementation for the SHA [8], we have choen the one in Fig. 42 for it implicity and the fact that it i able to hold the ignal for the entire half clock-cycle. It mut 85

98 Figure 5.8: Monte-carlo output for AC repone imulation of Opamp in Fig

99 Figure 5.9: Monte-carlo output for tep repone imulation of Opamp in Fig be noted that the SHA tage need to have rail-to-rail input/output common-mode voltage requirement, in order to maximize the dynamic range of the filter, and prevent any undeirable amplifier aturation. Thi make the SHA deign inherently power hungry. In addition, a dicued earlier, the SHA operate at f S = 2 f SW = 2 MHz, and thu each THA amplifier need to ettle ufficiently within 250 n. While THA # can take thi much time for ettling, we would prefer THA # 2 to take minimum amount of time for ettling ince we want to minimize the delay beyond T/2. Thu, it would be preferred if it GBW i maximized. One limit to maximizing the GBW i the large capacitance een by THA 87

100 Figure 5.20: Baic concept of T-network approach (Star-Delta tranformation). # 2 due to the ucceeding SCF tage. From Section 5.2., we can conclude that the loading would be 4.25 pf, which i extremely large, and can reult in huge power diipation in A THA2. We have tackled thi iue in deign of SCF # 2 in the next ection, and were able to reduce thi value down to ~ 8 pf. We have employed the rail-to-rail amplifier topology hown in Fig. 5.9 for implementing the two THA amplifier in Fig Thi topology enure rail-to-rail input/output voltage operation for wide dynamic range. In eence, folded-cacode baed complementary NMOS/PMOS input pair can provide rail-to-rail ICMR. The wort cae for tability i during mid-rail, when both the pair are turned On. On the other hand, the wort cae for GBW i at high/low rail, when only one of the pair i On. Thi i auming that the NMOS/PMOS input pair are ized to have the ame tranconductance for a given bia current. In uch a cenario, the wort cae GBW i exactly half of the mid-rail GBW. The wort cae GBW requirement can be calculated from the 5τ (= 250 n) ettling requirement of the THA # 2. Hence, fgbw 3. 2 MHz 2 (5.24) 88

101 Figure 5.2: Propoed chematic of SCF # 2 and it aociated witch phae. In Fig. 5.8, we how the mid-rail monte-carlo imulation reult for the THA # 2 amplifier deign acro PVT variation, to check for wort-cae tability. It can be een that the GBW i enured to be more than 2 MHz for mid-rail input common-mode condition, and hence more than 6 MHz at high/low rail. Thu, we are able to enure by deign that the condition in (5.24) i atified acro PVT variation. It mut be added that the amplifier lewing i not 89

102 included in the ettling requirement. Thi i a reaonable aumption for cla-ab output tage baed amplifier, even when they experience large-ignal tranient. Fig. 5.9 how the 0.5 V tep repone monte-carlo imulation reult for mid-rail condition for the amplifier under conideration. 5.4 SCF # 2 The large capacitance C (in Fig. 5.) arie from the fact that C a need a minimum ize in order to meet the matching requirement and to enure low variability in paraitic-enitive SCF architecture. Thu, if we can find a way to realize a lower (effective) C a, we can lower the value of C, for the target ampling rate and zero time contant requirement. A T-network baed integrator for yntheizing very large time contant i propoed in [3]. The underlying concept i hown in Fig We can write the following relationhip for the ame: C C C C C C C C C C C C C a 2b 2c A, CB, CC ; C (5.25) 2b 2c 2a 2a 2b 2c Now, conider the Double-ampling T-network baed witched-capacitor HPF, a hown in Fig The double-ampling input network i needed to upport the BLT output network, operating on both clock phae. Hence, thi lead to duplication of the T-network, and the two operate on complementary phae. We mut alo mention that the two network are ymmetrical and hence, C 2a,b,c = C 2a,b,c2 = C 2a,b,c. Now, it can be een that in phae Φ 2, capacitor C 2a,b,c are reet to the common mode voltage given by V REF, while in phae Φ, thee capacitor are connected to the SCF 90

103 input voltage (V SH ) to hare charge with the reet of the ytem via the iolated net at V FB3. The equivalent capacitor that hare charge i given by C B in Eq. (5.25). Uing the expreion for C B and the principle of charge conervation, we can evaluate the tranfer function of SCF # 2, a given in Eq. (5.26). H SCF 2 C ( z) C 2 22 C C 2a 2 C. C 2b. C C C C 2c 2b 2c 22 22a C C z. z 2a 2c. z (5.26) It i clear from the above equation that thi i a hybrid methodology for zero and pole realization. Now, we can chooe the value of C 2a,b,c to achieve the deired zero frequency. For the target zero frequency (20 KHz) and a ampling rate of 2 MHz, we get the following value of capacitance: C 2 = 5 pf, C 2a = 3.5 pf, C 2b = pf and C 2c = 0 pf. Thu, we get a total capacitance of 34 pf, which i not a ignificant reduction from the previou cae of 4.25 pf. Ofcoure, the value of capacitor C 22 and C 22a are unaffected. Uing Eq. (5.25), we get C A = 2.4 pf, C B = 0.25 pf and C C = 0.69 pf. Thu, the benefit of the T-network approach i the dramatic reduction in the loading of the previou tage (V SH ) and given by C A + C B + C 2 = 7.65 pf compared to 4.25 pf in SCF #. Thu, we can achieve a fat THA # 2 amplifier tage (ee Fig. 5.6) without burning too much power. 9

104 5.5 Gain Stage A direct conequence of reduction in the effective witching capacitor value i the reduction in DC gain, if C 22a i unchanged. Hence, a non-inverting gain tage i required to compenate for thi reduction, to meet the filter pecification a outlined in Figure 5.22: Gain-Block amplifier followed by a RC low-pa filter. Section 4.. Thi can eaily be accomplihed uing the circuit in Fig The tranfer function i given a: HGB( ) AGB( ) B (5.27) 0 Here, A GB () i the ingle-pole amplifier tranfer function and B 0 i DC feedback factor. 92

105 ; ) ( 0 R R B A A GB ) ( B A B A A HGB ) ( A B B HGB (5.28) Hence, it can be een that the cloed-loop ytem ha a pole at the ratio of the amplifier UGB and the DC gain ( + B 0 ) of the ytem. Thu, the amplifier deign need to make ure that thi paraitic pole i well outide f SW (= MHz) to avoid any degradation in phae margin. Finally, we Low-Pa Filter (LPF) the output voltage (V COMP4 ) to provide a clean compenation (V COMP ) ignal to the PWM comparator (ee Fig..6). Figure 5.23: Final propoed Type-III SCF architecture.

106 Thu, with the change incorporated in the Type-III SCF architecture in Section , we preent the finalized chematic in Fig We have now repreented the SCR implementation to be driven by f SW a a reult of double-ampling technique employed. 94

107 Chapter 6 6. Practical Conideration for the Interfacing Circuitry The Type-III SCF decribed in the previou ection need to be interfaced with auxiliary circuit to produce the final Pule-Width Modulated (PWM) ignal for cloed-loop control of the Buck converter (ee Fig..6). Thee will be dicued in the following ubection: 6. Double-ampling SCF conideration For SCF employing doubling-ampling technique, it i important that the mimatch between the two ampling path i minimized [32]. The impact of mimatch i more evere in the cae of SC-HPF, ince any puriou high-frequency content get implicitly amplified. The mimatch can arie from two ource: a. Sampling Capacitor Mimatch The mimatch between the ampling capacitor can lead to unequal charge haring in the two double-ampling path. Thi can firtly be minimized by chooing a given unit capacitor ize, which i already conidered for the accuracy of the time contant being realized. In our deign, a matching accuracy of better than % i enured. In addition, a wa decribed in Section 5.2, we have enured ymmetric bottom-plate paraitic ince the SCF deign i paraitic-enitive. Finally, careful layout i required in order to make the two path highly ymmetric. b. Clock Duty-cycle Mimatch 95

108 The effect of mimatch in the clock duty-cycle in a double-ampling SCF architecture i imilar to the path mimatch error occurring in the two half-cycle of the clock. Thi effect i known a non-uniform ampling [32]. We were able to model thi effect in imulation, by introducing a fixed duty-cycle mimatch, and were able to enure the robutne of the propoed architecture for up-to 2 % mimatch. A decribed in Section 6.3, we have enured by deign that thee deign requirement are met via the propoed SCF clocking cheme. 6.2 DC Coupling Effect The witched-capacitor network behave like a reitor at DC (and at frequencie much lower than the ampling rate), which wa alo concluded in Section 2.. Baed on thi, we can deduce that the propoed Type-III SCF i equivalent to the circuit in Fig. 6. at DC (and low frequencie). Here, we have excluded the SHA tage for the ake of implicity. Figure 6.: Equivalent Type-III SCF architecture at low frequencie. 96

109 It can be een from Fig. 6. that the t tage (integrator) i AC coupled to V OUT. Thu, V COMP can aume any voltage within the rail for any given value of V OUT (and hence V REF ince V OUT follow V REF in cloed-loop configuration). Now, it mut be een that V COMP i DC coupled to V COMP, and indirectly alo to the intermediate voltage V COMP2 and V COMP3. Thu, at teady-tate, the variou filter voltage are directly dictated by V COMP ignal, which i dependent on the awtooth waveform and the duty cycle value. Now, the following relation hold, auming zero offet amplifier in the ignal chain: V V V R3V R32V R3 R32 COMP3 COMP REF (6.) R R 2 COMP2 VREF VREF VCOMP3 (6.2) R R 22 COMP VREF VREF VCOMP2 (6.3) 2 It can be een from (6.) (6.3) that if V COMP deviate too far from V REF, the variou voltage can get aturated to either the poitive or negative rail. Thu, it would be bet if V COMP follow V REF, and it would alo be the cae during oft-tart condition a well. Another way to view thi ituation would be by conidering that there i only a given range of V COMP that can be accommodated within the rail without aturating one or more amplifier in the ignal chain (at any given V REF ). While we are auming a DC operating point for thi cae, we mut alo undertand that V COMP will fluctuate above/below the teady-tate value during line/load tranient and oft-tart. In addition, the ituation i exacerbated by the fact that the amplifier and the PWM comparator will have offet. Thee effect can everely limit the 97

110 Figure 6.2: Propoed clocking cheme for the Type-III SCF architecture. dynamic range of the propoed Type-III SCF. To alleviate thi problem, we have carefully deigned the awtooth waveform generator and PWM comparator in the following ubection. 6.3 Propoed Clocking Scheme The clocking cheme for the propoed SCF i hown in Fig Firtly, a dicued in Section 6., we have tried to enure that the duty cycle mimatch i minimized for the double-ampling SCF architecture. For thi, we have generated a mater clock operating at frequency 4 f SW, having a duty-cycle given by R OS C OS. Thereafter, the mater clock i divided-by-2 to generate the SHA clock (2 f SW ). The SHA clock i further divided-by-2 to 98

111 Figure 6.3: Variou clock and awtooth waveform for the cae f SW = MHz. generate the SCF clock operating at f SW. It mut hereby be undertood that it i very difficult to directly generate a clock having low duty-cycle mimatch, and hence dividing a higher frequency clock i a very effective mechanim for enuring thee pecification. Thereafter, the only duty-cycle mimatch arie due to the jitter preent in the mater clock, which can be typically < % for clock in the MHz range. We were able to confirm via imulation by 99

112 Figure 6.4: PWM Comparator Block and it aociated waveform. introducing a hard jitter, that thi i indeed a ufficient criterion to enure a afe operation for the SCF. A can be een from Fig. 6.2, the mater clock ha relaxation ocillator architecture, which can be configured to operate at either 2 MHz or 4 MHz baed on the configuration bit given by B TUNE_F = [0, ]. The mater clock architecture can be extended to 00

113 generate the awtooth waveform generator for enuring a fixed feed-forward gain given by: V IN / V SAW = 8/7, which i implicitly enured for both configuration of B TUNE_F. In addition, we have alo enured a near rail-to-rail awtooth waveform generator to provide wide dynamic range for a robut SCF operation (a dicued in Section 6.2). Finally, the variou waveform are hown in Fig. 6.3, auming zero delay for both the comparator and onehot in Fig PWM Comparator Block The PWM comparator block ha two important deign requirement:. We need to ynchronize the PWM pule with the awtooth ramp tart, in order to eliminate the impact of the lave awtooth (ee Fig. 6.3) one-hot time contant variation (4 R OS C OS ) from the target V COMP value. While the aynchronou PWM comparator delay can alo impact the target V COMP value, thi delay i not a ignificant. In addition, it can be preciely controlled by chooing PTAT biaing current for the comparator. The propoed PWM comparator block and the aociated timing waveform are hown in Fig A can be een from the waveform, the D Flip-Flop (DFF) ynchronize the PWM pule with the awtooth ramp, and hence V COMP ~ 7/8 V REF. In addition, the DFF alo enure that there i no puriou witching during the entire witching cycle. Thu, thi provide a robut olution with low jitter and controlled EMI performance. It i alo important to notice that the propoed circuit can allow duty-cycle from almot 0 to, thereby facilitating a good load tranient repone for the cloed-loop ytem. 0

114 2. A rail-to-rail ICMR for the aynchronou PWM comparator front-end need to be enured in order to accommodate the near rail-to-rail awtooth waveform, a decribed in Section 6.3. The circuit chematic for thi comparator i hown in Fig A can be een it ha complementary NMOS/PMOS input pair acting a tranconductance element umming current onto the node V OUTP and V OUTM. For the NMOS input pair, the load i a diode-connected low-v THP PMOS option available in the technology. Thi allow ICMR to go beyond the V DD rail. The high ICMR can be given a: V CM, H VDD VTHN, B VTHP, L VDSAT (6.4) Here, V CM,H i the high ICMR of the comparator, V DD i the upply rail, V THN,B i the threhold voltage of the input NMOS pair (with body-effect), V THP,L i the threhold voltage of the low-v TH PMOS load tranitor and V DSAT i it overdrive voltage. Under nominal condition, V THN = 0.7 V, V THP,L = V, and V DSAT = 0.2 V. Hence, even without the input NMOS pair body-effect: V, H VDD 0. V (6.5) CM 2 For the PMOS input pair, the low ICMR i given by: V CM, L VTHN VTHP, B VDSAT (6.6) Here, V THP,B i the input PMOS threhold voltage with body-effect. Under nominal condition, V THP = V. Thu, even without input-pair PMOS body-effect: V CM L 0 V, (6.7) The bigget motivation for uing uch a tructure compared to a folded-cacode tructure for ICMR enhancement i that the latter can everely limit the peed of the comparator, 02

115 by introducing extra biaing tranitor. Thi tructure, with fewer tranitor offer fater ettling time for a given current conumption. To increae the peed further, we have employed local negative feedback in the t tage of the comparator. Thi feedback limit the voltage wing on the t tage during poitive or negative lewing event, thereby allowing it to repond fater to the tranient. However, care mut be taken during deign to enure that it doe not interfere with the operation of the final tage of the comparator acro PVT variation. We were able to achieve ~ 20 n of delay at f SW = MHz and nominal condition uing thi tructure, while conuming 35 µa of bia current. Figure 6.5: Rail-to-rail ICMR aynchronou PWM Comparator. 03

116 Chapter 7 7. Simulation Reult In thi ection, we will preent and dicu the imulation reult of the propoed Type-III SCF. We will firt how the frequency repone of the propoed filter and compare it with the deired filter repone. In addition, we will compare the tranient tep repone performance of the propoed Type-III SCF with it analog counterpart. 7. Open-Loop Frequency Repone The frequency repone of the SCF cannot be directly imulated uing tandard technique of mall-ignal AC analyi about a DC operating point. The reaon i that the SCF doe not have a teady-tate operating condition. Intuitively, thi i becaue an SCF i a witching circuit having an operating point which i periodic in time. The period i really equal to the ampling time period of the filter. Hence, the imulator firt calculate the teady-tate operating point of the SCF uing Period Steady-State (PSS) analyi in SpectreRF (by Cadence) [24]. Thereafter, mall time-varying ignal are applied on top of thi operating point to evaluate the frequency information from the ame. Thi imulation i a part of the Periodic AC (PAC) analyi [24]. Clearly, in order to obtain high-frequency information from PAC, the PSS would have to calculate maller time tep information. The PSS/PAC imulator ha an advantage over other imulator like SWITCAP [25] that it can be ued to imulate tranitor model, which can be ued to model the variou PVT variation. In addition, everal non-idealitie like Opamp finite gain-bandwidth/lewing, 04

117 Figure 7.: Simulation etup for characterizing the DUT. effect of paraitic, mimatche between variou charge-tranfer path and nonlinearity/charge injection of witche can all reflect themelve upon the frequency repone. Hence, thee imulation reult are extremely realitic. Finally, it mut be added that PSS/PAC analyi can be applied to any witching circuit with a periodic operating point uch a RF mixer and ocillator. Hence, it i alo applicable to witching power converter, which can be part of the ame imulation environment, giving u a unified imulation trategy. Fig. 7. how the complete imulation etup for the characterization of the propoed Device Under Tet (DUT), which i the Type-III SCF and the PWM modulator. Thu, the 05

118 (a) (b) Figure 7.2: Simulation of Fig. 7. howing reult for (a) PSS (b) PAC (V SH ). DUT i a SPICE-level netlit that contain only the model from TI 0.36-μm BCD proce. In addition, we have a reference deign in the ame proce for DRMOS (Driver and MOSFET) from I LOAD =.5 A part. Finally, the LC filter and the load are modeled by ideal SPICE component. Thi etup i conitent with the fact that only the LC filter i realized by uing dicrete component for our target application (ee Section.). Now, the PSS/PAC analyi i conducted in open-loop configuration for the cae f SW = MHz (Fig. 7.2 and 7.3). The feedback loop i broken at the input to the compenator 06

119 (a) (b) Figure 7.3: Simulation of Fig. 7. howing PAC reult for (a) V COMP (b) V OUT. (indicated by the red cro in Fig. 7.). At thi point, a tone at a frequency of 00 KHz i injected with DC voltage equal to the V OUT value (= V REF ) at.5 V a a reference cae. A can be een from the PSS reult in Fig. 7.2a, the imulation converge with a time period of 0 μ. In thi time, both the low and high frequency content i captured. It can be een that although the intermediate SCF ignal (V COMP,2,3 and V SH ) have ome high-frequency witching tranient, the final V COMP (topmot trace) ignal i quite clean. Thi i important if the witching jitter need to be minimized for the Buck converter. 07

120 Figure 7.4: Simulation of Type-III SCF howing PAC reult B TUNE_F = [0, ]. The PAC reult for the V SH ignal i hown in Fig. 7.2b, which mut be compared with the V COMP2 ignal in Fig..9. It can be een that the DC gain i lower than the expected value. Thi i becaue of the fact that the integrator need to be made loy in order for it to have a table DC operating point in open-loop configuration. However, the integrator bandwidth and the zero frequency are a expected. A dicued in Section 5.2.2, the pole ha now become complex. It can alo be oberved that the ample-and-hold effect produce null at multiple 08

121 of f S (= 2 f SW = 2 MHz) in the magnitude repone, but ha little effect in the edegradation i omewhat compenated by the extra degree of freedom we have with the T-network in SCF # 2. Thu, we adjut the DC gain and zero frequency of SCF # 2 to get the repone a hown in Fig. 7.3a. A can be een from the final open-loop repone (output of Buck) in Fig. 7.3b, a phae margin of 55 and a Unity-Gain Bandwidth of 08 KHz i achieved at nominal condition of proce and temperature. To check the calability of the Type-III tranfer function w.r.t. the witching frequency (f SW ), we have checked the PAC reult for the two configuration of B TUNE_F = [0, ], correponding to f SW = 0.5 and MHz, repectively. The reult are hown in Fig. 7.4 for nominal condition, and we can ee that the filter tranfer function cale linearly. Once again, the gain degradation at low frequencie (and DC) i attributed to the integrator made loy to tabilize the DC operating point of the filter operating in open-loop configuration. 7.2 Cloed-Loop Tranient Repone The ame etup in Fig. 7. i ued for evaluating the cloed-loop load tranient tep repone for three different cae: In the firt cae, we have ued the conventional analog Type-III filter a hown in Fig..9. In the econd cae, we have ued the cacaded verion of the continuou-time analog Type-III filter a decribed in Fig. 4.. In the third and final cae, we have employed our propoed SCF baed Type-III compenation (Fig. 5.23). In all cae, we have employed amplifier with limited GBW (= 20 MHz), and no lewing ditortion. In addition, the feedforward gain i made unity for all cae (V IN = V SAW ). All thee meaure are undertaken to compare truly linear ettling repone of all the three filter under 09

122 Table 7.: Open-loop frequency repone of variou Type-III filter embodiment Type-III Filter Topology Bandwidth Phae Margin Gain Margin Conventional ARCF 8 KHz db Cacaded ARCF 4 KHz db Cacaded SCF 2 KHz db conideration. Finally, a can be een in Table 7., the three filter are deigned for nearimilar cloed-loop frequency repone for a given Buck Converter power tage (f LC = 29 KHz and f ESR = MHz) at a given witching frequency, f SW = MHz. It can be een that compared to the conventional Type-III filter, both the continuou- and dicrete-time filter, implemented via cacaded ection, have lower phae and gain margin. Thi can be directly attributed to the preence of paraitic complex-pole in the filter tranfer function. Thi effect wa oberved and quantified in Section The cloed-loop load tep (0.5 A) repone of the conventional ARCF, cacaded ARCF and cacaded SCF (with near-imilar frequency repone) are hown in Fig , repectively. It can be een that the cacaded filter (both ARCF and SCF) how light degradation in underhoot/overhoot compared to the conventional ARCF, which can be directly attributed to their lightly degraded frequency repone. It i intereting to oberve that while the SCF ha a ample-and-hold delay, it impact i completely modeled by it analog frequency repone, and ha little impact on the cloed-loop tranient. It mut be alo be undertood here that thi ampled-data (dicrete-time) analog filter i part of another ampled-data ytem (witched-mode buck converter), whoe ampling rate i lower (half) than that of the compenation filter. Thu, the ampling preent in the compenation filter ha 0

123 Figure 7.5: Simulation of load tep repone for conventional ARCF in Fig..9.

124 Figure 7.6: Simulation of load tep repone for cacaded ARCF in Fig

125 Figure 7.7: Simulation of load tep repone for cacaded SCF in Fig

126 little impact on the performance of the complete ytem, being compenated via a lowfrequency (cutoff frequency at f SW /0 f SW /5) linear control methodology. Thu, we can conclude that the propoed filter theory can have a wide applicability. 4

127 Chapter 8 8. Meaurement Reult 8. Power and Area Summary The power conumption of variou component of the propoed Type-III SCF i hown in Table 8.. It can be een that the total current conumption i ~. ma from a 3.3 Table 8.: Nominal current conumption of the Type-III SCF Deign Block G m C OTA Stage G m C Buffer SCF # Amplifier SCF # 2 Amplifier THA # Amplifier THA # 2 Amplifier Gain Block Reference Selection Buffer PWM Comparator Mater Ocillator Aociated Bia Circuitry Bandgap Reference Total Static Current Static Current 30 μa 05 μa 0 μa 05 μa 0 μa 20 μa 60 μa 90 μa 35 μa 40 μa 240 μa 60 μa 05 μa V upply voltage. Thi current conumption i lower than both the analog and digital implementation of thi filter (ee Section.2). The on-chip area conumed by thi filter i a trong function of the total on-chip capacitance. In Table 8.2, we how the value of the variou capacitor required to realize the propoed SCF in Fig The total capacitance i 5

128 Table 8.2: Capacitor value and area of the Type-III SCF Capacitor Value C 4 pf 40 pf C SCR.25 pf C 2 pf SCR2.25 pf C 2 5 pf SCR2 29 pf C 22 pf SCR22.25 pf Total SCF Capacitance 90 pf Capacitance Area (C PP2 ) 0.35 mm 2 ~ 90 pf. Thi capacitance i implemented uing the highly-linear Poly2-Dielectric-Poly layer on the chip (available in mot tandard CMOS procee), and ha a denity of ~.5 ff/µm 2. Thu, the area conumed i ~ 0.35 mm 2. However, it mut be added that a coniderable amount of area i alo conumed due to the preence of everal active element in the propoed architecture. Fig. 8. how the micrograph of the fabricated die in Texa Intrument 0.36-µm BCD proce. The filter active area i ~ 0.4 mm 2 while the controller total active area i ~ 0.65 mm 2. It mut be mentioned here that ince the SCF architecture i paraitic-enitive employing double-ampling technique, the layout mut be carefully handcrafted in order to:. Minimize paraitic on the charge-haring node of the witching capacitor to minimize inaccuracie and mimatch. 6

129 Figure 8.: Die photo of the propoed Type-III controller IC. 2. Shield the feedback node of the SCF amplifier from clock ignal (having high dv/dt) in order to prevent any tray charge injection via coupling. 3. For double-ampling SC-HPF#2, enure that the two ampling path are ymmetrically laid-out to minimize any mimatch in paraitic in order to prevent any puriou tone in the output pectrum. It mut be mentioned here that the focu of thi work wa to build a firt working prototype and hence we did not pay pecial attention to power and area optimization. A can be een from Table 8., a lot of tatic current i diipated in the aociated bia circuitry for the 7

130 Figure 8.2: PCB photo for teting the propoed controller IC with Buck converter power tage. analog block. Hence, the area and power performance can be improved further via imple deign and layout optimization. 8.2 Meaured Reult We deigned and laid-out a 4-layer FR4 PCB for teting the functionality of the filter. The chip wa bonded to a 32-pin QFN package and directly oldered onto the Printed Circuit 8

131 Figure 8.3: Meaured waveform howing the load tep tranient at f SW = 0.5 MHz. Board (PCB). Fig. 8.2 how the PCB photo with the controller, high- and low-ide driver and MOSFET IC indicated. We alo included the Over-Voltage Protection (OVP) to prevent any damage to the MOSFET, and indirectly alo prevent any aturation of the inductor. The SPM6530T low-dcr inductor and ceramic capacitor were ued to enure a high quality factor output LC filter. We teted the compenation for two programmable witching frequencie f SW = 0.5 and MHz. For thi, we caled the LC filter almot linearly to enure the ame V OUT ripple magnitude (< 0.5 % in our prototype). The low V OUT ripple i enured epecially for the cae when low-esr ceramic output capacitor are employed. The ripple magnitude will be higher 9

132 Figure 8.4: Meaured waveform howing the load tep tranient at f SW =.0 MHz. and the limit of AAF teted for the SCF when ESR value are higher. However, it mut be noted that the higher ESR will alo provide additional phae boot and tability i improved even further a long a the SCF repone doe not experience ditortion. A dicued in Section 4.4, our deign take care of thi even for a wort-cae ripple magnitude of 5 %, yielding a truly univeral Type-III compenation prototype. Fig. 8.3 how the meaured load tranient tep repone at f SW = 0.5 MHz, V IN = 3.3 V and V OUT =.0 V from 0.5 A (and vice vera) at 0.3 A/μ. A voltage underhoot of 80 mv i oberved for with a ettling time of ~ 50 μ. The ignal capture bandwidth for thi 20

133 Figure 8.5: Meaured loop repone of the complete ytem at f SW = 0.5 and.0 MHz. meaurement i 20 MHz. Fig. 8.4 how the meaured load tranient tep repone at f SW =.0 MHz, under exactly the ame condition decribed for the previou cae. A voltage underhoot of 80 mv i oberved for with a ettling time of ~ 20 μ. The ettling time of a truly linear ytem cale with the unity gain bandwidth of it open-loop frequency repone. In Fig. 8.5, we how the open-loop frequency repone of the ytem captured by a network analyzer (AP 200 [33]), for both cae of f SW. It can be een that the filter tranfer function cale linearly with f SW, and no ditortion i oberved, even at frequency limit cloe to the Nyquit bandwidth of the SCF (= f SW ). At higher frequencie, cloe to f SW, we can oberve light gain peaking in the magnitude repone, followed by a notch, due to the ample-andhold effect of the fixed-frequency PWM control cheme. A can be inferred from Fig. 0, the 2