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1 Thi document i downloaded from DRNTU, Univerity Library, Singapore. Title A circuit baed behavioral modeling of ContinuouTime Sigma Delta modulator Author() Leow, Yoon Hwee; Zhang, Fan; Teh, Li Lian; Siek, Liter Citation Leow, Y. H., Zhang, F., Teh, L. L., & Siek, L. (009). A circuit baed behavioral modeling of ContinuouTime Sigma Delta modulator. In proceeding of the th International Sympoium on Integrated Circuit: Singapore, (pp.09). Date 009 URL Right 009 IEEE. Peronal ue of thi material i permitted. However, permiion to reprint/republih thi material for advertiing or promotional purpoe or for creating new collective work for reale or reditribution to erver or lit, or to reue any copyrighted component of thi work in other work mut be obtained from the IEEE. Thi material i preented to enure timely diemination of cholarly and technical work. Copyright and all right therein are retained by author or by other copyright holder. All peron copying thi information are expected to adhere to the term and contraint invoked by each author' copyright. In mot cae, thee work may not be repoted without the explicit permiion of the copyright holder. Thi material i preented to enure timely diemination of cholarly and technical work. Copyright and all right therein are retained by author or by other copyright holder. All peron copying thi information are expected to adhere to the term and contraint invoked by each author' copyright. In mot cae, thee work may not be repoted without the explicit permiion of the copyright holder.

2 A Circuit Baed Behavioral Modeling of Continuou Time Sigma Delta Modulator Yoon Hwee LEOW Diviion of Circuit & Sytem Univerity Fan ZHANG Diviion of Circuit & Sytem Univerity Li Lian TEH Diviion of Circuit & Sytem Univerity Liter SIEK Diviion of Circuit & Sytem Univerity Abtract In evaluating ContinuouTime Sigma Delta (ΣΔ) Modulator, the generation of highly accurate reult require long imulation time due to the nonlinear nature of the ytem. In mot cae, a compromie ha to be made to trade off preciion for peed []. Thi paper preent a circuitbaed high level model implemented in the MATLAB SIMULINK environment o a to achieve a fater peed of imulation. Deigned in a differential manner, the model provide good viualization of the actual circuit at the early tage of deign. To maintain imulation accuracy, circuit nonidealitie uch a ytem clock jitter, integrator noie, opamp finite gain, bandwidth and lew rate a well a the digital to analog converter (DAC) mimatche are included in the model. For demontration purpoe, a th order CT modulator with NRZ (NonReturn to Zero) architecture i implemented. With the propoed model, key deign pecification for the functional building block are derived. Index Term Analogtodigital (A/D) converion, behavioral modeling, continuoutime (CT), igmadelta (Σ ) modulation I. INTRODUCTION Sigma Delta (Σ ) Modulator had been extenively ued in application where a high reolution i required over a moderately mall ignal bandwidth. Claified broadly a overampling converter, there are in general two clae of Σ modulator, namely the dicrete time (DT) witched capacitor (SC) and the continuou time (CT) family. In recent year, the CT Σ modulator ha been gaining popularity, attributing mainly to characteritic uch a it inherent antialiaing property and the poibility of achieving lower power conumption a a reult of le tringent requirement on the peed of the CT integrator []. Due to the non linear nature of the ampling proce at the internal quantizer, the analyi of CT Σ modulator i a tediou proce. Thi often tranlate to lengthy time domain imulation epecially when evaluating high performance CT modulator. It i therefore neceary to have a high level model that can be ued to determine the performance of the modulator under the influence of circuit level nonidealitie. In the aim to improve the peed of imulation, the accuracy of imulation i often acrificed. Thi work propoe a high level circuit baed fully differential model for the CT Σ modulator implemented entirely in the MATLAB SIMULINK environment. In preerving the accuracy of the imulation, detailed modeling of circuit level nonidealitie i included. The model allow comprehenive time domain analyi of the modulator nonlinear ytem at a much fater rate compared to SPICE imulation. The paper i organized a follow. Section II decribe the modeling concept for the individual block with nonidealitie. In ection III, the implementation of the th order CT Σ modulator i dicued. Section IV dicue the imulation obtained before concluding the paper. II. MODELING CONCEPTS A. MATLAB Phyical Domain Modeling In SIMULINK, it i poible to place phyical component uch a reitor and capacitor for imulation. Thee component reide in the phyical domain. For implementation purpoe, the baic reitor and capacitor required in the propoed model i taken from the SIMULINK SimPowerSytem toolbox []. An interface ha to be inerted between the normal SIMULINK data ignal domain and the phyical domain. Thee interface are required when ignal propagate to and fro the two domain. A controlled voltage ource i required when moving from the ignal to the phyical domain. Converely, traniting in the revere direction from the phyical domain back to the ignal domain need a voltage meaurement block. Fig. illutrate the propagation of ignal between the two domain. inp inn V S Phyical Signal Phyical Figure. Tranition of data between the ignal and phyical domain B. Σ Modulator Nonidealitie A typical ingle loop ingle bit CT Σ modulator may conit of a continuou time RC integrator a the firt tage, tranconductor (gmc) cell a the ubequent tage, a quantizer and a ingle bit feedback digitaltoanalog converter (DAC). Thi ection focue on the modeling of nonidealitie V out 09 ISIC 009 Authorized licened ue limited to: Univerity. Downloaded on March 0,00 at 0:09:9 EST from IEEE Xplore. Retriction apply.

3 of the functional block within the CT Σ modulator. The main nonidealitie that are conidered include the following:. Sytem Clock Jitter;. Thermal and Flicker noie of firt integrator;. Finite gain and bandwidth of firt opamp;. Slew rate of firt opamp; 5. Linearity and ditortion of firt opamp; 6. Saturation voltage of firt opamp; 7. DAC mimatche. C. Sytem Clock Jitter Clock jitter ha alway been the fundamental performance limitation for CT Σ modulator. Variation from ideal clock edge vary the feedback pule length and hence the total effective feedback charge. Thi behavior increae the noie floor acro the frequency band. Thi phenomenon i epecially critical when occurring at the feedback DAC. It i becaue thi noie cannot be haped by the ytem when injected at that point. Independent clock jitter approximation i the mot widely ued model for performance prediction in high level imulation. In thi approach, clock jitter i modeled a an additive timing error on the ideal clock edge. A SIMULINK model ha been propoed by []. Alternatively, phae noie modulation can be applied to an ideal clock. However, uch approache produce time domain imulation that are extremely time conuming due to mall timing variation. A more efficient method would be to tranform pule width variance to pule amplitude variation. In [5], the author propoed a jitter model pecifically for NRZ feedback pule. A jitter model for the NRZ feedback pule i hown in Fig.. Z Figure. Jitter Model for NonReturn to Zero (NRZ) Implementation It i to be mentioned here that the amplitude modulation only enure firt order accuracy ince pule poition jitter i not conidered. However, ince pule poition variation i at leat firt order noie haped, it effect i relatively inignificant. Specifically peaking, for feed forward tructure, only one feedback path i ued, thu thi model i particularly uitable for FF implementation. D. Thermal and Operational Amplifier Noie The dominant noie ource in an active RC integrator compried of the white noie contributed by both the input and feedback reitor in addition to the input referred amplifier noie which conit of input flicker (/f) noie, wide band thermal noie and amplifier dc offet. Thee value are obtained through SPICE imulation. Subequently, all the individually input referred noie power pectral denity attributed to all the noiy device are ummed together before integrated acro the ignal bandwidth in concern. According to [], the total inputreferred noie power i given by equation (): 8KTfBne, th 8K f ne, th f = B Vnoie 6KTfB( Rfb) ln () g m, OTA CoxWL fu The total RMS noie voltage, V noie i uperimpoed to the input ignal leading to equation (): V out ( t) = V ( t) V n( t) () in noie where n(t) denote a Gauian random proce with unity tandard deviation. Equation () can be implemented by the SIMULINK model hown in Fig.. v v u zero() pole() Figure. Firt RC nonidealitie modeling including opamp /f noie, reitor thermal noie, finite opamp linearity, finite dc gain and GBW, lew rate and aturation voltage E. Operational Amplifier and it Nonidealitie The integrator circuit implementation deviate from the ideal behavior due to everal non ideal effect uch a the finite opamp gain and bandwidth, lew rate and aturation voltage. To make it a realitic a poible, an amplifier with a two pole and one zero tranfer function ha been adopted. The non dominant amplifier econd pole and amplifier zero are choen uch that it reult in a practical amplifier with a phae margin of approximately 60. Modeling of uch a real integrator with all non idealitie i hown in fig.. The finite gain bandwidth product (GBW) of the opamp can be model a ome form of leakage whereby only a fraction of the previou output i added to each new input ample. Hence, the tranfer function of a real op amp i given by equation (): AV AV H ( ) = () ω Z ω ω where A V denote the op amp dc gain; ω, ω, ω,repreent the firt, econd amplifier pole and zero repectively. y Authorized licened ue limited to: Univerity. Downloaded on March 0,00 at 0:09:9 EST from IEEE Xplore. Retriction apply.

4 Rfbn Noie Modeling Cint Exce Loop Delay Modeling Clock generator Sine p in n Single to differential converion Rfbp Random No. Vnoie in Voltage Converion Vgt U fcn V Control voltage ource Amplifier Nonideal OpAmp Modeling gm Cb Cb gm Cc Cc gm Cd VI Cd Summing reitor V in S/H Quantizer Tranport delay Dout Linearity Modeling Cint Switch Current () I v I Current () in Single to differential converion Jitter Z ZOH Random No. f Clock Jitter Modeling Figure. Entire differential model for the th Order NonReturn to Zero (NRZ) CIFF CT Σ modulator The opamp lew rate limitation and the aturation level are modeled in SIMULINK uing the lew rate and aturation block, placed in erie with the integrator a hown in Fig.. According to [6], the rd harmonic ditortion of the Σ modulator i given by equation (), ^ g vin HD = () 6g R fb Uing the quarelaw model of a MOS tranitor, the nonlinear tranconductance of the opamp input pair can be derived from tranitor operating in the trong inverion a given region by equation (5): GT D GT m D ID g m I g g = = ; g = = (5) V 8V 6I where V GT i the effective gateource voltage and g m i the tranconductance of the input tranitor. F. Tranconductor (gmc) Modeling In the deign of higher order CT Σ modulator, the more power efficient tranconductor (gmc) tructure i uually conidered from the econd integrator onward. The Sdomain tranfer function for a generic tranconductor baed integrator (gmc) i given by H()=gm/C. Fig. 5 illutrate the model for the gmc cell. V S Figure 5. Tranconductor (gmc) cell Model The input voltage ignal i converted into a current ignal that charge the load capacitor. Since the nonidealitie of the integrator beyond the firt do not generate ignificant degradation in the performance of the CT Σ modulator, [5], [6], it nonidealitie are often neglected when conidering the high level model. III. IMPLEMENTATION EXAMPLE To illutrate ome key deign inight and to validate the modeled nonidealitie, thi ection demontrate the deign of a th order CT Σ modulator in the NRZ (NonReturn to Zero) architecture. A uch, the top level deign target pecification for the implementation example are ummarized in Table. I. TABLE I. DESIGN SPECIFICATIONS SUMMARY Deign Parameter Deign Summary for NRZ Implementation Architecture Cacade Integrator Feed Forward (CIFF) Order Input Signal Bandwidth 5kHz Overampling Ratio (OSR) 6 Peak SNR 85dB The propoed modeling technique will be ued to imulate for the key functional block requirement for thi fourth order CT Σ modulator needed to fulfill the above pecification. The RC integrator i choen for the firt integrator for linearity reaon. The econd, third and fourth integrator are realized with tranconductor (gmc) tructure o a to conerve power. The modeling i done in a fully differential fahion, hence allowing a cloer viualization of the actual circuit. In particular, the firt integrator deign pecification will be fully derived. A. NonReturn to Zero (NRZ) Implementation In the NRZ implementation, the DAC feedback pule are held contant for each entire ampling period without being returned to the common mode voltage a like the Returnto Zero (RZ) cae. The coefficient for the loop filter are ued to calculate for the phyical deign value of the reitor and charge toring load capacitor. Fig. how the tructure for the NRZ architecture. The feed forward output current from the gmc cell are ummed acro a reitor a accordance to the CIFF tructure. Thi technique i een in Authorized licened ue limited to: Univerity. Downloaded on March 0,00 at 0:09:9 EST from IEEE Xplore. Retriction apply.

5 [7] to convert the current back into a voltage ignal for comparion by the inglebit voltage comparator. The exce loop delay i compenated by having a direct path acro the loop filter. In order to model thi compenation feedback path, it hould be noted that the path can be thought of a a inglebit feedback DAC that feed back a caled current ignal back into the umming reitor whoe value i decided by the quantizer output ignal. Each key component pecification wa then imulated againt the deign requirement to find out the leat tringent value neceary. IV. RESULTS The implemented modulator wa imulated to evaluate the maximum tolerance of the architecture on the modeled nonidealitie while fulfilling the pecification preented in ection III. Table II ummarized the minimum functional block requirement needed to achieve the targeted pecification with the nonidealitie modeled. TABLE II. MINIMUM DESIGN REQUIREMENTS Modulator Nonidealitie Value Input referred noie 50µVrm Linearity (HD) with Vgt of the opamp input device 0.V Finite gain bandwith (GBW).9MHz Finite DC gain 75dB Slew rate (poitive & negative lew).v/µ Saturation voltage ±0.5V Clock jitter 0.005%T Exce loop delay T Fig.6 how the PSD plot for the implemented modulator. The input frequency i choen to be at 7 khz for the imulation o that the third harmonic fall within the ignal bandwidth. To evaluate the peak Signal to Noie Ratio (SNR), the input range wa wept acro the entire dynamic range. A plot of the SNR wa then plotted againt the input value a hown in Fig PSD [db] PSD of a th order Sigma Delta Modulator Fully differential modulator with nonidealitie (SNR = 87.dB; ENOB =.8) Ideal modulator (SNR = 9.dB; ENOB = 5.8) Frequency [Hz] x0 5 Figure 6. Power Spectral Denity (PSD) plot SNR [db] Input Dynamic Range of th order Sigma Delta Modulator Fully differential modulator with nonidealitie Ideal modulator Input Amplitude [db] Figure 7. Input dynamic range Plot V. CONCLUSION In thi paper, a high level circuit baed fully differential model for the CT ΣΔ modulator implemented in SIMULINK ha been propoed. To enure accurate imulation, variou nonideal effect have been dicued and incorporated into the propoed model. The fully differential tructure enable realitic and intuitive modeling. A th order CT ΣΔ modulator wa implemented uing the propoed modeling. Reult indicating the minimum requirement for the functional block were preented. Thi modeling technique can be included a a high level evaluation tep within the deign flow and hence improving the deign time for CT ΣΔ modulator. REFERENCES [] M.Ortmann, F.Gerfer, Continuou time igma delta A/D converionfundamental, performance limit and robut implementation, Springer, Netherland, 006. [] M. Lanirinne and K. Halonen, SSDSIM a very fat and veratile imulator for SDmodulator, in Proc. ECCTD 99, Sept. 999 [] Inc. The mathwork. Matlab 007a and Simulink 6.6. The MathWork, Inc. Natick, MA(007) [] P. M. Chopp and A. A. Hamoui, Analyi of ClockJitter Effect in ContinuouTime Σ Modulator Uing DicreteTime Model, IEEE Tran. Circuit and Sytem I, Regular Paper, vol. 56, no. 6, June 009. [5] L. Hernández, A. Wiebauer, S. Patón, A. Di Giandomenico, Modelling and optimization of lowpa continuoutime igmadelta modulator for clock jitter noie reduction, Proceeding of the 00 International Sympoium on Circuit and Sytem, vol. [6] Lucien L.Breem, Eric J.van der Zwan and Johan H.HuijingDeign for optimum performancetopower ratio of a continuou time igma delta modulator. Proc.Eur.Solid State Circuit Conf. 8, September, 999. [7] Paton, S., Di Giandomenico, A., Hernández, L., Wiebauer, A., Pötcher, P. and Clara, M., A 70mW 00MHz CMOS continuoutime igmadelta ADC with 5MHz bandwidth and bit of reolution. IEEE J. SolidState Circuit. v9 i Authorized licened ue limited to: Univerity. Downloaded on March 0,00 at 0:09:9 EST from IEEE Xplore. Retriction apply.