Fast & Accurate Algorithm for Jitter Test with a Single Frequency Test Signal

Transcription

1 Fat & Accurate Algorithm for Jitter Tet ith a Single Frequency Tet Signal Minhun Wu 1,2, Degang Chen 2, Jingbo Duan 2 1 Xi an Jiaotong Univerity, Xi an,. R. China 2 Ioa State Univerity, Ame, IA, USA Abtract A fat and accurate algorithm for jitter tet i preented. The propoed method ue a ingle tet ith a high frequency input ine ave. Elimination of the need of a 2nd lo frequency tet required in the IEEE tandard tet offer ignificant aving on both hardare and data acquiition time. The ne method i computationally efficient ince it require only one FFT together ith ome imple time domain computation. Furthermore, there are no nonlinear operation involved, avoiding error inherently aociated ith uch operation. Theoretical analyi, extenive imulation reult, and experimental reult validated the computational efficiency and tet accuracy. The ne algorithm i alo hon to be robut ith repect to harmonic and non-harmonic ditortion. The algorithmic implicity and the relaxed hardare requirement make the ne method ell uited for built-in elf tet. Index Term Fat Fourier Tranform (FFT), jitter, pectral teting. I. INTRODUCTION The jitter i an important pecification of Analog-to- Digital Converter (ADC) or other ampling circuit, hich characterize the random variation in the ampled intant caued by the variation in the ampling clock or ampling circuitry itelf. Thi parameter i of pecial importance a the ignal frequency and data rate become more and more high. In ome application, the jitter ha become the ultimate limit of ytem performance. The reference [1] ho that, becaue of the uncertainty in the ampling intant due to jitter, the reolution of ADC fall by about 1 bit for every doubling of the ampling rate at ampling rate ranging from 2 MS/ to 4 GS/. Many jitter meaurement method have been preented in prior ork uch a in IEEE tandard 157 [2][3], Analog Device Inc. [4], and Texa Intrument Inc. [5] and o on. And thee method have been erving community ell, epecially in characterization tet. A common characteritic in the method mentioned above i that all of them require both a lo frequency and a high frequency ignal tet, and the to frequencie hould have ufficient eparation. A it ell knon that ADC tet need ome expenive ATE (Automated Tet Equipment), high-preciion yntheizer, high performance ignal generator, etc [6], compared ith a ingle frequency tet, the dual frequencie tet increae the tet cot greatly. Furthermore, for on-chip tet, dual frequencie tet ith ufficient frequency eparation can be many time more than a ingle frequency tet becaue the lo frequency on-chip tet need large capacitor and inductor hich conume large die area. Therefore, the dual frequencie tet method are challenging to be built on chip. In order to reduce tet cot and make on-chip jitter tet poible, a fat and accurate algorithm for jitter tet i propoed in thi paper. The propoed method require only a ingle tet ith a high frequency input ine ave. Compared ith the conventional dual frequencie tet, the ne method cut the tet time by 1/2. In the propoed method, the ADC output data i collected ith a given high frequency input ignal. Then FFT i ued to etimate the fundamental, harmonic, inter-modulation ditortion and DC component. The error equence i obtained by removing the fundamental, harmonic, inter-modulation ditortion and DC component from the original data. Then the error equence i orted into to et according the identified fundamental phae. Finally, the root mean quare (RMS) jitter i etimated from the difference beteen the to et. The propoed method require only a ingle tet ith a high frequency input ine ave. Both hardare and data acquiition time are aved ignificantly due to the elimination of the need of 2 nd lo frequency tet required in IEEE tandard tet, ADI and TI method. Compared to the method in the reference [7] hich require a ingle frequency ignal tet, the ne method i computationally efficient ince it require only one FFT together ith ome imple time domain computation. Furthermore, there are no nonlinear operation involved, avoiding error inherently aociated ith uch operation. Thereby the propoed method i robut to harmonic and nonharmonic ditortion. It hould be treed that the meaurement reult of the propoed method, imilar to IEEE tandard method, TI and ADI method, include the jitter of the ampling clock generator, the jitter of input ignal generator and the ADC internal aperture jitter. The jitter of any one of thee element can be accurately meaured a long a the jitter introduced by the other to element i ubtantially loer than that of the element under tet, ince jitter combine on an root-um-

2 quare (r) bai [8]. Furthermore, the propoed method i not only limited to ADC jitter tet, but it i alo uited to tet the jitter in other ampling circuit, uch a a Sample and old (S/) circuit (folloed by a analog ignal digitizer) or any other clocked ampling element that i ubject to jitter. The ret of thi paper i organized a follo. In the next ection, the fat and accurate algorithm for jitter tet i propoed, hich require only a ingle tet ith a high frequency input ine ave. The imulation and experimental reult that validate the propoed algorithm are reported in Section III and IV repectively. Finally ome concluion about the preented ork are extracted in Section V. II. FAST AND ACCURATE JITTER TEST In thi ection, a fat and accurate jitter tet method i propoed in detail. Let Vin(t) denote the input ignal of an ADC. The output of the ADC i a equence of ample x n ith length M, given by x = V ( nt + δt ) + V ( nt ) + V ( nt ) n in n hd im + V ( nt ) + V ( nt ), n=,1,2,3,..., M-1 noie q In (1), T repreent the ideal ampling period for the ADC, δt n i a random timing variable repreenting the total jitter, V hd (nt ) repreent the harmonic ditortion component, V im (nt ) repreent the inter-modulation ditortion component (ometime the inter-modulation beteen input ignal and the ampling clock ignal may exit, it can be een from the latter experimental reult in Section IV), V noie (nt ) repreent the equivalent input noie of ADC hich include the internal noie in ADC and the noie carried by the input ignal, V q (nt ) repreent quantization error of ADC. Our goal i to identify the technique to etimate the variance of the random variable δt n. According to Taylor formula, equation (1) can be eaily converted to dvin xn Vin ( nt ) + δtn dt (2) + V ( nt ) + V ( nt ) + V ( nt ) hd im here V ( nt ) = Vnoie ( nt ) + Vq ( nt ). From (2) e can ee that the jitter δt n i modulated by ignal lope hen it i converted to noie. For ine ave input, V ( ) in(2 ) in t A π ft + ϕ (3) In (3), A, f and φ are the amplitude, frequency, and initial phae of ine ave repectively. The lope of the input ignal i given by dv in 2π faco(2 π ft + ϕ) (4) dt From (4) e can ee that ignal lope depend on frequency, amplitude and time. Subtituting (3) and (4) into (2), e get (1) x Ain(2 π fnt + ϕ) n + 2π faco(2 π fnt + ϕ) δt + V ( nt ) + V ( nt ) + V ( nt ) hd im In (5), the determinitic component are the fundamental and harmonic, inter-modulation ditortion component, hich can be identified ith reaonable accuracy. The component V i expected to remain at the ame poer level regardle the ignal level. The jitter related term ha a coefficient depending on the fundamental phae. From FFT of the ra data x n, the fundamental, harmonic and inter-modulation ditortion component can be etimated ith reaonable accuracy. Subtracting the etimated fundamental, harmonic, inter-modulation ditortion component from the ra data x n, e can get the error equence e n e x Aˆ in(2 π fˆ ( n 1) T + ˆ ϕ) Vˆ Vˆ n n hdi imj n (5) (6) In (6), Â, ˆf, ˆϕ, V ˆhdi and V ˆimj are the etimated value of A, f, φ, the i-th harmonic component V hdi and the j-th intermodulation ditortion component V imj repectively. Combining (5) and (6), e get e 2π fa ˆˆ co(2 π fnt ˆ + ˆ ϕ) δ + V ( nt ) (7) n tn Equation (7) quantifie the ell-knon concept that hen an ADC i ampling a inuoidal input, the contribution of it jitter i much more pronounced hen the ampling intant coincide ith the zero-croing of the input (here co(2 π fnt ˆ + ˆ ϕ) i large), and ha very little impact on the output noie hen the ampling intant coincide ith the top or bottom of the input ine ave (here co(2 π fnt ˆ + ˆ ϕ) i mall). Therefore, e can make ue of thi concept in jitter tet. Let θ be the fundamental phae θ = 2π fnt ˆ ˆ + ϕ (8) Then the phae of the zero-croing of the input are given by π π { θ } = { θ + iπ θ + iπ, i =, ± 1, ± 2, ± 3,...} (9) 4 4 The phae of the top or bottom of the input are given by π 3π { θl} = { θ + iπ < θ < + iπ, i =, ± 1, ± 2, ± 3,...} (1) 4 4 Note that {θ } and {θ L } are to equal et ith length M/2, thu {e n } i orted into to equal et { } and {n } ith length M/2 according to the identified fundamental phae. e 2 ˆˆ n π faco( θ ) δtn + V (11) e 2 ˆˆ Ln π faco( θl ) δtn + V (12) Note for all e n in { }, the abolute value of the coefficient co(θ ) i larger than1/ 2, and for all e n in {n }, the abolute value of the coefficient co(θ L ) i le than or equal to 1/ 2. A a example, Fig. 1 illutrate that {e n } i orted into { } and {n } according to the identified

3 fundamental phae. The loer one ho that a 9-bit ADC output code in time domain. It hould be pointed out that he input ignal frequency i near Nyquit frequency. The upper one ho that {e n } i orted to ditinguihed et { } and {n }. Then the poer of and n can be derived a folloing ( ˆ ˆ ) e = 2π f A + σδ t + σ + ε (13) 2 π ( ˆ ˆ ) e = 2π f A L σδ t + σ + ε L (14) 2 π 2 2 Where σδ t i the variance of jitter δ tn, σ i the poer caued by the noie and quantization error, ε and ε L are due to the reidual harmonic and inter-modulation component error preent in and n repectively. ε and ε L can be eliminated if e only conider the poer coming from the noie floor in FFT of { } and {n }. Additionally, it i obviou that i larger than. From (13) and (14), e can get the total jitter variance 2 e el σ δ t = (15) ˆˆ 2 8 π ( fa) Therefore, the RMS total jitter i e el σ δ t = (16) ˆˆ 2 8 π ( fa) here e and are eaily obtained by computing the variance of of { } and {n } repectively = VAR{ e } (17) e el e n = VAR{ e } (18) The procedure of the fat and accurate algorithm for jitter tet can be outlined in the folloing ix tep. a) With given input and clock ignal, collect data x n ith record length M (even). b) Ue FFT to etimate fundamental, harmonic, intermodulation ditortion and DC component. c) Subtract the etimated fundamental, harmonic, intermodulation ditortion and DC component from data x n to form error equence e n. d) Ue identified fundamental phae to ort e n into to equal et ( and n ) ith length M/2. e) Compute e and Ln uing equation (17) and (18) repectively. f) Compute RMS jitter uing equation (16). In the propoed method, only a ingle tet ith a high frequency input ine ave i required. Compared ith IEEE tandard method, TI and ADI method hich require another lo frequency tet, the propoed method ave on both hardare and data acquiition time. In the ne method, the only FFT on data x n may be required for computing other dynamic parameter, uch a SNR (Signal-to-Noie Ratio), e n (LSB) ADC output code Time index of the ADC output code 4 2 n Time index of the ADC output code Fig. 1 {e n} i orted into {} and {n} according to the identified fundamental phae TD (Total armonic Ditortion), SFDR (Spuriou Free Dynamic Range), SIAND (Signal-to-Noie-and-Ditortion Ratio), ENOB (Effective Number of Bit), etc [9]. In the introduced method, no nonlinear operation i involved and the harmonic and inter-modulation ditortion component are excluded. So it i accurate and robut to harmonic and nonharmonic ditortion. Therefore, the propoed method i coteffective and computationally efficient, and it i potential to be built on chip. n III. SIMULATION RESULTS In order to validate the theoretical analyi preented in Section II, ome imulation in MATLAB ere developed, here a knon amount of jitter i taken into account. Specifically, the imulation environment i et up a follo. ADC i modeled a a et of tranition level. It nonlinearity error i choen to be a Gauian random variable ith zero mean and a given tandard deviation σ DNL. Three ADC are imulated in the imulation. The firt one i a 9- bit ADC ith σ DNL =.7 LSB (leat ignificant bit); the econd one i a 12-bit ADC ith σ DNL =.2 LSB; the third one i a 14-bit ADC ith σ DNL =.8 LSB. The input of ADC i a pure ine ave hoe amplitude a et at 96% of the full cale range of the converter. The additive meaurement noie i introduced at the input node of the ADC under tet. And it i a Gauian ditribution ith zero mean and a tandard deviation σ noie =1 LSB. A ine ignal generator i ued to generate a high frequency pure ine ave. The jitter i a random error added to the ideal ampling time. It i a Gauian ditribution ith zero mean and tandard deviation σ δt. Table I ho the etimated RMS jitter by the propoed algorithm under different cae. In Table 1, N repreent the reolution of the ADC, f clk i the frequency of ampling clock, f ig i the frequency of input ignal. In each cae, the number of collected data x n i 496 and the data i coherent. A expected, from Table 1 e can ee that the etimated RMS jitter i very cloe to the ideal RMS jitter. Fig. 2 ho the pectrum of the imulated 14-bit 2 MS/ ADC output hen the frequency of input ignal i

4 Mz. In Fig. 2, the to larget bin are the ignal aliaed into Nyquit zone. The noie floor i about -88 db, hich eem not conitent ith that of a reaonable 14-bit ADC. In general, the noie floor of a reaonable 14-bit ADC hould be about -12 db hen the number of collected data x n i 496 [2]. The rie of the noie floor i due to the jitter. Becaue the frequency of input ignal i much higher than Nyquit frequency, the jitter i very large. The pectrum of and n are hon in Fig. 3. The upper one and the loer one are the pectrum of and n repectively. From Fig. 3 e can ee that the noie floor of i larger than that of n. The reaon i that correpond to many zero-croing ampling point, here the input ignal lope i very teep. A e have knon that the jitter i modulated by the ignal lope hen it i converted to noie. So the noie floor of i large. Therefore, the imulation reult ho that the propoed algorithm requiring only a ingle tet ith a high frequency input ine ave can etimate the jitter accurately. Normalized output relative to full cale (db) oer pectrum denity (db) oer pectrum denity (db) Signal tone The frequency of input ignal i about 364 Mz The ampling frequency i 2 Mz Fig. 2 The pectrum of imulated 14-bit ADC output Fig. 3 The pectrum of imulated and n TABLE I. TE COMUTED RMS JITTER UNDER DIFFERENT CASES N/bit f clk /Mz f ig /Mz Ideal σ δt /p Computed σ δt /p IV. Experimental Reult The propoed method ha been implemented on a commercial 9-bit 8 MS/ time-interleaved pipeline ADC. In jitter tet ith a ingle frequency tet ignal, the ampling frequency i generally et for the maximum alloable and the frequency of input ignal i alo et high, here the effect of clock and aperture jitter on the ADC output error are noticeable. Depending on the ADC, the frequency of input ignal may be a high a Nyquit frequency. In thi tet, the ampling frequency i 8MS/. The input i a ine ave ith full cale amplitude and it frequency i about 399Mz, hich i near Nyquit frequency. The collected data x n i coherent ith a data record length of The ADC i actually made of to 4MS/ time-interleaved ADC together to achieve 8MS/. For the timing ke beteen the to channel of the combined ADC caue non-harmonic error that are not due to jitter, e prefer to ue one of the time-interleaved ADC rather than the combined ADC for jitter tet. Therefore, the collected data x n a broken into to eparate ubet: the firt one contain the odd numbered ample, and the econd one contain the even numbered ample. The propoed algorithm i then implemented on one of the to ubet (8192 ample). According the procedure of the propoed method in Section II, firtly, FFT i performed on one of the to ubet, then the fundamental, harmonic, inter-modulation ditortion and DC component are identified. After that {e n } i obtained by removing the identified fundamental, harmonic, inter-modulation ditortion and DC component. Then {e n } i orted into to equal et { } and { n } ith length of 496 according to the identified fundamental phae. The computed and are and repectively. It hould be pointed out that the value of e and are relative to the FS (full cale) of ADC, here FS i equal to 2. A the identified the fundamental amplitude by FFT i.9442, the identified fundamental frequency i Mz, in the end, uing equation (16), the etimated RMS jitter i.424 p. In order to verify the reult obtained by the propoed algorithm, ADI method i implemented on the jitter tet by adding a lo frequency input ignal meaurement in our experiment. ere, the input ignal i et about 2 Mz. The etimated RMS jitter by ADI method i.48 p, hich i cloe to the reult computed by the propoed method. In fact, the etimated RMS jitter by the propoed method i maller than that of the latter. In the propoed method, the harmonic component are excluded. Therefore, the difference of the to value reult from puriou component, hich could be inter-modulation ditortion component, definitely not be harmonic component. Indeed, if the puriou component are excluded manually in ADI method, the etimated RMS jitter i.438 p, hich i more cloe to the reult etimated by the propoed method. The comparative reult by different method are ummarized in Table II. e

5 Fig.4 ho the pectrum of commercial 9-bit ADC output hen the frequency of input ignal i about 399 Mz. From Fig.4 e can ee that the output of ADC comprie many ignificant harmonic and non-harmonic component. Fig.5 ho the pectrum of and n. The upper one and the loer one are the pectrum of and n repectively. From Fig.5 e can ee that the average poer pectrum denity of i larger than that of n, hich validate the previou derivation in Section II. From the experiment e can ee that only a ingle tet ith a high frequency input ine ave are performed in the propoed method. Elimination of the need of 2nd lo frequency tet required in IEEE tandard tet, TI, and ADI method make the propoed method ave on both hardare and data acquiition time ignificantly. Furthermore, the experimental reult ho that the propoed method i robut to harmonic and non-harmonic ditortion, and i more accurate and fater than conventional to frequencie jitter tet method. TABLE II. TE COMUTED RMS JITTER BY DIFFERENT METODS Number of frequencie Efficiency cot Etimated jitter ADI method to lo high.48 p ADI method ith puriou to lo high.438 p excluion ropoed method one high lo.424 p Normalized output relative to full cale (db) Signal tone armonic tone The frequency of input ignal i about 399 Mz The ampling frequency of ub-adc i 4 Mz Spuriou tone Signal tone armonic tone Fig. 4 The pectrum of commercial 9-bit ADC output oer pectrum dentity (db) oer pectrum denity (db) n V. CONCLUSIONS In thi paper, a imple algorithm for jitter tet i developed, jutified theoretically, and validated by mean of both imulation and experimental reult. In particular, the propoed method require only a ingle tet ith a high frequency input ine ave. Compared ith IEEE tandard method, TI, and ADI method hich require another lo frequency tet, the introduced method ave on both hardare and data acquiition time. Since FFT i performed only once and only ome imple time domain computation i involved, the ne method i computationally efficient. Robutne to harmonic and non-harmonic ditortion i alo built into the algorithm. The experimental reult have hon that the propoed method i more accurate and fater than the ADI method. Therefore, the preented method i cot-effective and potential to be built on chip. REFERENCES [1] Robert. Walden, Analog-to-Digital Converter Survey and Analyi, IEEE Journal on Selected Area in Communication, vol.17, No.4, pp , April [2] IEEE Standard for Digitizing Waveform Recorder, IEEE Std. 157TM-27, April 28. [3] Shahram Shariat-anahi, Francico André Corrêa Alegria, Antoni Mànuel, " IEEE 157 Jitter Tet of Waveform Recorder", IEEE Tran. Intr. & Mea., vol.58, No.7, pp , July 29. [4] Walter Keter, The Data Converion andbook, Analog Device,Inc, pp , December 24 [5] Mark Burn, McKiney, David Ta-ei Kao et al., US patent B1, Method and Apparatu to Meaure Jitter, iued [6] Joey Doernberg, ae-seung LEE, David A. odge, Full-Speed Teting of A/D Converter, IEEE Journal of Solid-State Circuit, vol.c-19, No.6, Dec [7] D.M. ummel, Wahid Ahmed, F..Iron, Meaurement of Random Sample Time Jitter for ADC, IEEE International Sympoium on Circuit and Sytem,vol.1, pp , April [8] Mituru Shinagaa, Yukio Akazaa, Tutomu Wakimoto, Jitter Analyi of igh-speed Sampling Sytem, IEEE Journal of Solid- State Circuit, vol.25, No.1, Feb [9] Joey Doernberg, ae-seung LEE, David A. odge, Full-Speed Teting of A/D Converter, IEEE Journal of Solid-State Circuit, vol.c-19, No.6, Dec Fig. 5 The pectrum of actual and n