Design of hybrid continuous-time discrete-time delta-sigma modulators. Kwan, HK; Lui, SH; Lei, CU; Liu, Y; Wong, N; Ho, KL

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1 Title Deign of hybrid continuou-time dicrete-time delta-igma modulator Author() Kwan, HK; Lui, SH; Lei, CU; Liu, Y; Wong, N; Ho, KL Citation Proceeding - Ieee International Sympoium On Circuit And Sytem, 28, p Iued Date 28 URL Right 28 IEEE. Peronal ue of thi material i permitted. However, permiion to reprint/republih thi material for advertiing or promotional purpoe or for creating new collective work for reale or reditribution to erver or lit, or to reue any copyrighted component of thi work in other work mut be obtained from the IEEE.

2 Deign of Hybrid Continuou-Time Dicrete-Time Delta-Sigma Modulator Hing-Kit Kwan, Siu-Hong Lui, Chi-Un Lei, Yanong Liu, Ngai Wong, and Ka-Leung Ho Department of Electrical and Electronic Engineering, The Univerity of Hong Kong Pokfulam Road, Hong Kong {kwanhk, luip, culei, yliu, nwong, Abtract Recent attention ha been drawn to the hybrid Delta-Sigma ( ) tructure featuring the integration of continuou-time (CT) and dicrete-time (DT) tructure in the loop filter. It combine the accurate loop filter characteritic of a DT modulator and the inherent anti-aliaing of a CT modulator. We preent a deign methodology for building a CT-DT modulator via the tranformation from a DT modulator prototype. We alo demontrate the tradeoff of applying thi tructure to cacaded Delta-Sigma modulator compared to pure CT or DT implementation. Index Term Sigma-Delta modulation, overampling, ADC, deign methodology R I. INTRODUCTION ecent attention ha been drawn to the hybrid tructure featuring the integration of initial tage() of continuou-time (CT) integrator() and ubequent dicrete-time (DT) integrator in the loop filter [1], [2], e.g., Fig. 1. Such mixed-mode modulator ha everal merit over conventional modulator uing only DT loop filter [1]: 1) The initial CT integrator() can provide inherent anti-aliaing filtering to the input ignal. Hence, the anti-aliaing filter preceding the modulator can be removed or the requirement to the anti-aliaing filter i relaxed to reduce the complexity and power conumption. 2) Since there i no ampling of the input voltage prior to the loop filter, ignal-dependent charge injection, clock feed-through and ampled noie do not exit in the firt tage. The ampling take place within the loop filter where thee noie are haped and uppreed. 3) Any ignal-dependent glitche coupled to the input of the modulator are averaged out over the clock period by the CT integrator, thereby harmonic ditortion due to the coupling are attenuated. 4) When there i no feedforward path from input to the econd and ubequent tage, the input impedance of the firt-tage integrator i purely reitive, and no electromagnetic interference (EMI) i emitted back to the input pin. Meanwhile, a ingle-loop CT-DT modulator till poee mot of the advantage of a witched-capacitor (SC) ingle-loop DT modulator, uch a accurate and robut loop filter characteritic againt proce variation, and inenitivity to clock jitter etc., a the ubequent integrator (in majority) are till contructed by DT SC circuitry. The timing control loop in [1] ha ignificantly increaed the inenitivity of the CT tage integrator againt modulator clock jitter, and hence ha coniderably reduced thi dominant error ource [3] affecting the initial CT tage of a CT-DT modulator [4]. Thi alo remove the need of other mean to increae the clock jitter immunity of the CT tage, which in turn greatly implifie the deign while maintaining a high ignal-to-noie ratio (SNR). Depite the potential advantage of a CT-DT modulator over it purely DT counterpart, little ha been reported for the proper modeling and deign of the former. Subequently, we propoe an analytical framework to ytematically deign a CT-DT modulator with an arbitrary number of initial CT integrator tage baed on the tranformation from a DT modulator prototype. Our main innovation and contribution lie in the matching of a DT modulator to a CT-DT tructure for actual realization. In particular, it will be hown that the propoed deign flow produce a tep-invariant CT-DT modulator a compared with the DT modulator prototype. Extenion to other waveform-invariant deign follow imilarly. In the final part of thi paper, the application of thi DT-CT tructure on the cacaded topology i propoed and invetigated. It i hown that the DT-CT implementation of cacaded modulator can provide the ame level of anti-aliaing a a CT cacaded modulator, which ha alo attracted much attention in recent work [5], [6], [7]. II. CONTINUOUS-TIME INTEGRATOR AND INHERENT ANTI-ALIASING We begin by analyzing the DT model of a CT integrator at the input of a CT-DT modulator. Referring to the upper half of Fig. 2, we tart from the CT relationhip of a 1t-order CT modulator [8], t, (1) yt () ( xt () vt ()) dt where xt () i the input ignal, yt () i the output of the firt CT integrator, and vt () i the CT DAC feedback ignal. Auming a non-return-to-zero (NRZ) feedback waveform out of the CT DAC, an equivalent model can be found (lower half of Fig. 2) which i decribed by the difference equation yn ( ) yn ( 1) x ( n 1) vn ( 1), (2) where ( n 1) T 1 T nt repreent a x ( n) x( ) d ( g x)( n) Fig. 1. An example CT-DT modulator. zero-order-hold (ZOH) ampled value with g 1/ T, -T t () t., otherwie Taking the z-tranform of (2), the CT integrator can be modeled a the tep-invariant tranform of 1/, /8/$ IEEE 1224 Authorized licened ue limited to: The Univerity of Hong Kong. Downloaded on June 3, 29 at 4:7 from IEEE Xplore. Retriction apply.

3 G ( ) Fig. 2. DT modeling of the firt-tage CT integrator. 1 z yz ( ) [ x ( z) vz ( )] 1, (3) 1 z a in Fig. 2. The pre-filter G ( ), with the impule repone g () t, etablihe a complete tate value equivalence between the CT integrator and the DT model for an arbitrary input xt (). The pre-filter G ( ) alo account for the inherent anti-aliaing effect of the CT firt tage: the Fourier tranform of g () t reult in G T T ( ) in( ) /. Under an overampling rate M, it 2 2 2M 1 2M 1 provide an attenuation of in( ) /( ) to the frequencie that 2M 2M alia into the paband band edge. Thi level of attenuation i approximately the ame a that of a 1t-order Butterworth anti-aliaing filter with cutoff at the paband edge, but the inherent anti-aliaing roll off much fater than the latter between ( 2 M 1 ) f and f 2 M. Moreover, in G ( ), zero at the multiple of f provide a firt-order nulling to the frequencie aliaing into the DC. Therefore, if one tage of CT integrator i ued, the order of the anti-aliaing filter preceding the modulator can be reduced by at leat one. Inherent anti-aliaing effect of a group of initial CT tage can be found by conidering the correponding prefilter [8] Loc () G (), (4) Lod ( z) z e where Loc () and Lod ( z ) are the tranfer function of thi group of CT tage and it equivalent DT model tranfer function, repectively. III. DESIGN METHODOLOGY We propoe a general deign flow to contruct a CT-DT modulator a ummarized in Fig. 3. Starting with a precribed pecification, we firt build a DT modulator prototype. A DT initial model i ued becaue there exit rich literature and oftware tool for deigning conventional DT SC modulator [9], [1]. With the equivalence between the DT prototype and the final CT-DT modulator thu deigned, we can perform analyi on the DT model which would carry over to the CT-DT modulator. Moreover, the modulator tability and integrator overloading condition can be analyzed eaily on the DT model. The requirement of the anti-aliaing filter can alo be pecified at thi tage. A rule of thumb of the minimum attenuation required i, B Amin 2log( ), (5) where B i the effective number of output bit in the analog-to-digital converter (ADC) to be deigned [11]. In the early tage of the deign proce, the effective number of bit of a ADC can be etimated from the approximated dynamic range equation, (2L 1) 3 2N (2L 1) OSR DR 2, (6) 2L 2 where OSR i the overampling rate, L i the order of the modulator and N i the number of the bit of the internal quantizer [12]. Fig. 3. Flowchart for the propoed CT-DT modulator deign flow. Next, the tranfer function of the portion of the DT prototype loop filter that need to be implemented by CT circuitry i written up. It i then converted into a CT counterpart by the z-domain to Laplace domain ( z ) tep invariant tranform. Deigner can decide the portion of DT tage to be converted to CT tage according to the inherent anti-aliaing filter wanted. Baically, for every integrator implemented with CT, the order of the anti-aliaing filter preceding the modulator can be reduced by at leat one. When there i no negative real pole in the DT loop filter tranfer function, the z tranform i unique and well-defined, e.g., ee 1 [13], and can be done by either: a ZOH pole mapping of z1 e T that map the z-domain pole z 1 to a -domain pole 1 ; the d2c command in Matlab; or imple table lookup (e.g., Table 2 of [14]). Thi tranformation aume a NRZ CT DAC feedback waveform; however, any CT DAC feedback waveform of duration le than one clock period i acceptable with an extra tep: increae the CT DAC T feedback coefficient by a factor of T / v() t dt, where vt () i the internal CT digital-to-analog-converter (DAC) feedback waveform. The Laplace domain tranfer function obtained i then mapped to CT integrator circuit. Cacading the CT circuitry and the portion of untranformed DT circuitry reult in the final hybrid CT-DT tructure with initial CT integrator tage and feedback DAC, which ha a tep repone matched to that of the DT prototype. Ref. [2] ue a SC DAC intead of a CT DAC for further reducing the enitivity to clock jitter. Our propoed methodology i alo applicable to the deign of thi pecific CT-DT modulator. Finally, the inherent anti-aliaing of CT tage i aeed according to (4) at frequency ( 2 M 1 ) f, the 2 M frequency at which ignal with frequency component higher than thi would alia into the paband. If the attenuation to the aliaing ignal by CT tage i ufficient, the order of the anti-aliaing filter preceding the modulator can be reduced or the filter can be removed accordingly. IV. DESIGN EXAMPLES AND SIMULATION RESULTS We validate the propoed deign methodology by applying it to different DT modulator prototype. The firt example i a 4th-order DT prototype from [15] a hown in Fig. 4(a). It i converted into a CT-DT modulator with two initial CT tage and two ubequent DT tage. The tranfer function of the DT portion to be tranformed (urrounded by dotted line) i expreed a X( z) ( ) U( z) [( ) ( )] Y( z). (7) z 1 z 1 z 1 Taking the CT DAC waveform a NRZ, via any method mentioned in Section III, the equivalent CT model of the two initial tage can be found to be X () ( 2 ) () ( 2 ) () ( ) T U T ( T ) T Y. (8) 1225 Authorized licened ue limited to: The Univerity of Hong Kong. Downloaded on June 3, 29 at 4:7 from IEEE Xplore. Retriction apply.

4 (a) Open-loop tep repone Dicrete-Time loop filter prototype Deigned equivalent CT-DT loop filter (b) Fig. 4. (a) DT modulator prototype. (b) Deigned CT-DT modulator. Input to quantizer Fig Time() x 1-4 Output plot howing the equivalence of the DT and CT-DT modulator by the open-loop tep repone. -2 Power Spectral Denity Deigned equivalent CT-DT modulator Dicrete-Time modulator prototype Fig. 5. Simulink etup for validating the propoed deign methodology. -4 Thi portion of the tranfer function i implemented by CT circuitry and cacaded with the untranformed portion of the prototype to give the final CT-DT modulator a hown in Fig. 4(b). The loop filter of the prototype and the deigned CT-DT modulator are verified to have identical tep repone in the Matlab Simulink environment Fig. 5 how the etup up for verifying another deign. The DT -14 modulator in the upper part of the figure i another initial prototype -16 deigned with an overampling rate M 64 to further verify our deign flow. The DT prototype i alo converted to it CT-DT frequency (normalized to ampling frequency) equivalence in the lower part of Fig. 5 according to the propoed Fig. 7. Output plot (power pectral denity) ubject to an aliaing noie tone. deign flow. Due to the high ampling rate, the anti-aliaing filter for Power Spectral Denity the DT modulator i deigned to be a 1t-order Butterworth lowpa filter. Fig. 6 how the open-loop tep repone of the DT and the Deigned equivalent CT-DT modulator Dicrete-Time modulator prototype CT-DT modulator, repectively. The two curve how that, when -2 driven by a unit tep input, the open-loop CT-DT and DT loop filter -4 produce the ame input value to the quantizer at the clocking intant. Thi demontrate the equivalence of the CT-DT and DT -6 modulator. To demontrate the inherent anti-aliaing feature of the CT-DT -8 modulator, we clock the modulator equipped with 4-bit internal -1 quantizer at 256kHz and digitize a 1kHz -3dBV ignal tone added with a -13dBV noie tone at 255.5kHz. Thi noie tone will alia into the -12 paband. Without any anti-aliaing filter, the CT-DT modulator -14 achieve a SNR of 64dB, while the SNR of the DT prototype equipped with an additional 1t-order Butterworth filter i jut 51dB. From frequency (normalized to ampling frequency) Fig. 7, the inherent anti-aliaing of the CT-DT modulator provide Fig. 8. Output plot (power pectral denity) ubject to ampling a further 13dB attenuation on thi aliaing tone. nonideality. Another tet i performed to highlight the inenitivity of the prototype i only 78 db, a hown in Fig. 8. Thi difference can be CT-DT modulator againt ampling error, uch a equated to a gain of about 2.5 effective number of bit (ENOB). ignal-dependent charge injection, clock feedthrough and ampled coupling harmonic in a mixed-ignal environment. Since a modulator i a cloed-loop ytem, the DAC feedback ignal follow the input ignal quite cloely. We aume the ignal to the integrator, V. MULTI-STAGE CASCADED CT-DT MODULATORS i.e. difference between the input and DAC feedback, ha a flat power So far, mot cacaded modulator in the literature ue DT SC pectrum a the quantization noie. We model all the ampling noie by a -12dB additive white noie at the poition where the CT ignal i ampled into a DT ignal, namely, at the input of the 1t DT integrator of the DT prototype and the 1t DT integrator of the circuit in their implementation. CT cacaded modulator are proved feaible, but are till uncommon. Baed on our deign methodology, we propoe to implement cacaded modulator with hybrid CT-DT circuitry. Fig. 9 (a) and (b) how a cacaded DT prototype and it CT deigned CT-DT modulator. In thi imulation, the CT-DT equivalent, repectively. Fig. 9 (c) and (d) how the CT-DT modulator achieve a SNR of 93dB, while the SNR of the DT implementation deigned by our approach, with one and two 1226 Amplitude(dB) Amplitude(dB) -6 Authorized licened ue limited to: The Univerity of Hong Kong. Downloaded on June 3, 29 at 4:7 from IEEE Xplore. Retriction apply.

5 Table 1. Comparion between different implementation of cacaded 2-2 modulator. DT CT-DT (1 CT-DT (2 CT CT CT integrator) integrator) Anti-aliaing uppreion (db) Max. SNR lo due to circuit mimatch (db) Fig. 9. (a) DT cacaded modulator prototype. (b) CT equivalent. (c) Deigned CT-DT modulator with 1 CT integrator. (d) Deigned CT-DT modulator with 2 CT integrator. integrator implemented by CT circuitrie, repectively. Monte Carlo imulation on thee four topologie are carried out and the reult are ummarized in Table 1. The maximum SNR lo due to circuit mimatch i obtained by running 1 imulation auming: (i) the DT circuit i implemented with SC circuit and the tandard deviation of capacitor mimatch i le than 1%, a it i in the.18 m CMOS proce; (ii) the CT circuitry i implemented by RC integrator, in which the tandard deviation of the RC product mimatch i 1% (The abolute RC value can vary in the order of 2% in practice [7]). From the imulation reult, we can ee that one of the CT-DT tructure, the cacaded 2-2 modulator with firt tage econd order modulator implemented with CT circuit and a econd tage modulator implemented with DT circuit (Fig. 9 (d)), can achieve the ame level of anti-aliaing uppreion a a cacaded 2-2 continuou-time modulator (Fig. 9 (b)) derived from the ame DT cacaded prototype. Anti-aliaing filter can be omitted if the ADC i targeted at reolution equal to or le than 8 bit. Although it i more prone to circuit parameter mimatch than DT cacaded prototype (Fig. 9 (a)), it i till more robut againt proce variation than the cacaded 2-2 continuou-time topology, and the mimatch problem can be olved with uitable digital correction cheme, e.g. [16]. Furthermore, the DT-CT cacaded topology with only one CT integrator (Fig. 9 (c)) how a clear tradeoff between the inherent aliaing filtering in complete CT cacaded topology and the inenitivity to mimatch in complete DT cacade topology. All thee obervation open up new poibility to deign high-order modulator with inherent anti-aliaing feature by hybrid CT-DT cacaded topologie. VI. CONCLUSION A framework ha been propoed to ytematically deign a CT-DT modulator baed on the tranformation from a conventional DT modulator prototype. Starting with a precribed DT prototype, the methodology give rie to a CT-DT modulator with a tep-invariant repone. Our method greatly reduce the deign effort and the CT-DT modulator thu deigned i readily realizable with conventional circuitry. Simulation have confirmed the efficacy of the CT-DT implementation. The novel idea of implementing cacaded topologie by hybrid DT-CT tructure ha alo been explored, which how promiing performance and deign tradeoff. REFERENCES [1] K. Nguyen, R. Adam, K. Sweetland and H. Chen, A 16-dB SNR hybrid overampling analog-to-digital converter for digital audio, IEEE Journal of Solid State Circuit, vol. 4, no. 12, pp , Dec. 25. [2] B. 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