2.1 Circuit transform CHAPTER FDSM 2.0

Transcription

1 2CHAPTER 2. Circuit tranform CHAPTER The firt-order FDSM 2. Thi chapter tart by tranforming the conventional DSM into a non-feedback equivalent whoe new propertie are dicued. The firt-order FDSM principle i then derived from which three different FDSM variant are preented, imulated and compared to the traditional DSM. 2. Circuit tranform From now, it will be convenient to have an exact mathematical definition of the quantizing function. For a practical DSM, where the number of quantizer output level i retricted, the level placement mut be properly choen to accommodate the input ignal range due to the feedback. In thi dicuion, the number of level i aumed to be large, and therefore, the level placement will not be critical. The unity-gain quantizing function q(x) with quantizing threhold integer multiplie of l will therefore imply be defined a qx () x mod l () x. (2.) Compared to the quantizing function illutrated in Fig.., q(x) i hifted down by /2 a illutrated in Fig. 2.. The quantization error e n will now be retricted to the interval <-,], but by conidering q(x) output level quantization error threhold x Fig. 2. The q(x) quantizer function it new mean value a a bia in the input ignal, it RMS value will be the ame a for the former ued quantization function, and all the theoretical reult will therefore till be valid for q(x). 5

2 Chapter 2 The firt-order FDSM The Z-tranformed repreentation of a conventional dicrete-time firt-order DSM i hown in Fig In thi circuit, the ADC or quantizer i repreented by the complex quantization function Q, X(z) _ z U(z) Q( ) Y(z) Fig. 2.2 Z-tranformed repreentation of the traditional firt-order DSM defined by Q(U(z)) Z{q(u n )}. The output may then be expreed a Yz () Q z. (2.2) z Xz () z Yz () In appendix A it i proven that for the general equence f n and g n, the quantization function Q poe the property z QFz ( () P G() z ) QFz ( ()) P G() z if qg ( n ) g n (2.3) i.e. if the equence g n i already quantized. In thi tatement, P i a general complex polynomial on the form z -a /(-z - ) b where a and b are poitive integer. Βy uing thi property, which will be referred to a the reolving property, the Y(z) term of Eq. (2.2) may be reolved from the quantizer function, and the equation may be expreed a Yz () ( z )Q z (2.4) z Xz () But Eq. (2.4) i an expreion decribing a different circuit with the ame mathematical behavior, and it may be ketched by Fig The correponding time domain repreentation will be given by n y n q x i q x i. (2.5) i i Thi new circuit reveal the imple principle of the firt-order DSM. Except from the unit delay, the modulator operate by firt integrating the ignal, then quantizing it, and finally differentiating the ignal and the quantization error to retore the ignal. Since the quantization error i not integrated, it n X(z) z - Q( ) z - z - - Y(z) Fig. 2.3 Equivalent firt-order DSM will be differentiated, and the quantization noie will be hifted up in frequency and out of the ignal band. By conidering the quantization error a uncorrelated with the input ignal, the ignal will pa unchanged except the unit delay. To achieve a better undertanding of the firt-order -Σ noie haping principle we may think of the modulator a a cacade of a continuou-time integrator and derivator. Their equivalent gain will 6

3 2.2 The firt-order FDSM principle be repective /T and T. In between, the quantization noie i entering the circuit a illutrated in e x ( )dτ /T T d ( ) dt y Fig. 2.4 Another look at the firt-order -Σ noie haping principle Fig In thi circuit, we have two different mechanim which both reduce the output in-band SQNR. Firt of all, by letting the error enter between the integrator and the derivator, the output noie will, a we already have een, be formed by the derivative of the error. Thi mechanim hape the noie by uppreing the low frequency in-band error component. The next noie uppreing effect follow from the fact that the error enter between the two complementary gain factor /T and T which cale up the ignal compared to the error by a factor /T for all frequencie. By doubling the ampling frequency /T, we actually double the magnitude of the input ignal compared to the magnitude of the error, and thi give a 6dB increae in SQRN. It i further a well known reult that by ampling a ignal mixed with white noie, the in-band SNR decreae with 3dB for each doubling of the ampling frequency. Together thi two factor explain the increae in SQNR by 639dB for each doubling the ampling frequency in the traditionally DSM. 2.2 The firt-order FDSM principle By conidering the theoretical circuit in Fig. 2.3, we have no feedback and thu no DAC, and thi eliminate all problem due to miplaced DAC output level. A the output of the quantizer i digitally differentiated, all baeband noie introduced by miplaced quantizer threhold will be heavily uppreed. Thi two feature open up for traight forward multi-bit quantization. The drawback i however that due to the lack of feedback, all inaccuracy in the integrator will add directly to the ignal. The modulator SNR will therefore be retricted to the SNR of the integrator, which for high SQNR operation mut be very accurate. In addition, without feedback, a conventional accumulator will ooner or later aturate, and thi i why the FM repreentation oignal become intereting. By modifying the traditional FM expreion given in reference [], the ideal logic level FM ignal may be expreed a fm() t V dd V gn( in [ θ() t ]) dd, (2.6) 2 2 where the gn function i defined a gn() x ; x ; x <, (2.7) and the intantaneou normalized angle θ(t)/2π i given by θ() t ( f. (2.8) 2π c kx() τ ) dτ t In thi expreion f c repreent the carrier frequency, and k the frequency enitivity to the modulating ignal x(t). From Eq. (2.8) we notice that the FM ignal or more exactly the frequency modulator 7

4 Chapter 2 The firt-order FDSM ource by it angle θ(t) i an integrator with repect to the modulating ignal x(t). Thi property do alo follow from the fact that the FM carrier may be conidered a a phae or angular modulated carrier where the modulating ignal i pre-integrated. The frequency modulator may be very ueful a an DSM integrator in application where the feedback i removed. It will never aturate a it may be conidered a a modulo integrator where θ(t) x(t) θ(t) frequency modulator fm(t) θ n/ 2π detector θ n /2π q( ) z - _ y n Fig. 2.5 A general firt-order FDSM repreent a rotating phaor with the angular peed modulated by the input x(t). The integrator SNR will correpond to the SNR of the FM ignal may be high depended of the architecture of the frequency modulator. The frequency modulator i however a continuou-time integrator, and by exchanging the dicrete-time integrator in Fig. 2.3 with a frequency modulator a illutrated in Fig. 2.5, the reulting FDSM will be mathematically equivalent to a conventional DSM with a continuou-time loop integrator and input T (f c kx(t)) (ee Appendix A). But for a high OSR we may from Eq. (2.8) approximate θ n /(2π) a θ n ( 2π) T ( f c kx i ), (2.9) i and the FDSM overall operation may principally be decribed by applying thi ampled FM variable directly to the quantizer. Since there i no unit delay, the output will from Eq. (2.5) be y n q T ( f c kx i ) q T ( f c kx i ), (2.) i and by repreenting the quantizer by the additive noie e n, we have n n n i y n T ( f c kx i ) e n T ( f c kx ) i e n T ( f c kx n ) e n e n. (2.) i n i A we ee, the modulating input ignal x i i jut caled and biaed, while the quantization error i differentiated. The overall circuit will therefore, except from the caling and biaing factor, provide equivalent Σ noie-haping with repect to x(t). We may alo conider it a delta modulation [] with repect to θ n /2π ince the ubcircuit handling the FM ignal actually i a delta modulator. Buried in the output bit or word tream, the effective output ignal range will be SR o 2 f, (2.2) where f i the maximum frequency deviation caued by the input ignal range SR i. A oppoed to the traditional DSM, the FDSM integrator gain i unaffected by the ampling frequency. Therefore, by conidering Fig. 2.4, we realize that by doubling, we will not have the traditional 6dB increae n T k SR i 8

5 2.3 The baic modulo-2n FDSM in SQNR ince the input ignal caling i not affected. The 3dB increae due to the overampling effect will however be preent. In FD application the input ignal will already be given a a FM carrier i.o. the frequency modulator i implemented in the ignal ource. For thee application, the FDSM ytem mut be conidered to include the ignal ource integrator even if it i implemented a an ocillating enor or a a traditional frequency modulator everal mile away in a radio tranmitter. In thee application, the integrator SNR i already given by the SNR of the received FM ignal. Any noie introduced to the FM ignal, including noie generated by the θ n /2π detector, will be firt-order haped a the FM ignal i the integral of x(t). Due to thi high noie immunity of the FM ignal, the accuracy requirement of the θ n /2π detector will be very low. 2.3 The baic modulo-2 n FDSM A in the traditional DSM, the ADC threhold placement and pacing may be varied, but in the FDSM ytem, we will ee that the implementation will be particularly imple by locating the quantization threhold to integer value by letting the module l of q(x) equal. θ n /2π detection By looking at the ampled FM variable θ n /2π, the quantizer input may be expreed a θ n p, (2.3) 2π n ϕ n p n- ample p n p n θ n p n 2π2πϕ n 2πϕ n fm(t) ϕ n 2πp n Fig. 2.6 The plitted angle repreentation where p n i an integer repreenting the number of received FM period or riing FM edge at time nt, and ϕ n [,> repreent the phae difference between the previou riing FM edge and the ampling edge caled by /2π a illutrated in Fig The modulator output may now be expreed y n q θ n -----, (2.4) 2π q θ n π qp ( n ϕ n ) qp ( n ϕ n ) By the ue of integer quantization threhold, p n and p n- will be already quantized, and according to the reolving lemma (Appendix A), the output will be equivalent to y n p n p n q( ϕ n ) q( ϕ n ). (2.5) But ince ϕ n i retricted to the interval [,> and we are uing integer quantization threhold, the quantization error will be -ϕ n, and the output from the quantizer function will alway be zero which let u reduce Eq. (2.5) to y n p n p n. (2.6) 9

6 Chapter 2 The firt-order FDSM Thi i imply the received number of riing FM edge during the ampling interval T. From thi dicuion we realize that the mot traight-forward firt-order FDSM may be implemented imply a a frequency modulator followed by a count and dump FD converter (Fig. 2.7). To put it in another way, we have hown that by introducing overampling and proper decimating in the traditionally count and dump AFD ytem, we achieve multi-bit -Σ noie haping with repect to the modulating ignal. x(t) θ(t) frequency modulator fm(t) reet period counter count reg y n Fig. 2.7 The mot traight-forward firt-order FDSM realization Since the quantization error i -ϕ n, the output from thi FDSM may from Eq. (2.) alo be expreed a y n T ( f c kx i ) ϕ n ϕ n. (2.7) A an -Σ AFD converter, the SQNR will from Eq. (2.2) and Eq. (.6) be SQNR 2 k -- SR i π log. (2.8) f max log 36 f A we ee, thi expreion i identical to the traditional DSM expreion, except from the caling of the input ignal by k/. Since multi-bit quantization i inherent in the FDSM concept, a ignificantly higher SQNR may be achieved in the FDSM by the ue of a high k value. A high k value may be obtained either by the ue of a high carrier frequency and/or a high f/f c ratio. A the non-linearity of the frequency modulator normally will increae with the f/f c ratio, the ue of a high carrier frequency may be the right way to go. If the frequency modulator i already implemented in the ignal ource, we may from Eq. (2.2), more eaily expre the SQNR of the FD ubcircuit by SQNR 2 f π log f max log. (2.9) 2 36 f It will, of coure, be poible to increae the dynamic range by counting both riing and falling FM edge. Thi will directly correpond to letting p n in Eq. (2.3) repreent the received number of halve period at time nt, and ϕ n [,>, the phae difference between the lat FM edge and the current ampling edge caled by π. Since the quantization error RMS value will be unchanged while the ignal range i doubled, an increae in SQNR of 6dB will reult. Probably, the mot practical implementation may then be by the ue of a eparate poitive and negative edge triggered counter and imply add their output. The firt objection may be that an accurate FM ignal duty-cycle of 5/5 may be required, but imulation how minor SNR degradation for minor FM duty-cycle diverion. Thi i reaonable ince the dynamic range i independent of the duty cycle while the quantization error range will increae from [,> to [,2> when the duty cycle approach / or /. By reducing the duty-cycle to / or /, the 6dB increae in SQNR will therefore gradually be lot. 2

7 2.3 The baic modulo-2n FDSM The modulo-2 n counting principle The counter reetting operation will be a limiting factor for high peed operation. According to Eq. (2.6) and by conidering the count and dump circuit a an ideal counter with no upper limit followed by a digital differentiator, the ideal counter may be realized a a modulo-2 n counter (Fig. 2.8). x(t) θ(t) frequency modulator fm(t) modulo-2 n counter reg n-bit reg _ n-bit output word-tream Fig. 2.8 The baic modulo-2 n FDSM with it poitive ignal edge triggered modulo-2 n counter By diregarding the borrow bit from the differentiator, the modulator output will be equivalent to the output from the modulator in Fig. 2.7 uppoed that the maximum number of received riing FM edge during T i maller than the module of the counter. In mot application, non-varying bia component in the meaured ignal have no information content. In the FDSM, the carrier will normally be of no interet, and by uing modulo-2 n arithmetic, the only retriction on the ize of the module i that it have to be larger than the maximum variation in the number of received riing FM edge during T to avoid ignal aliaing. The counter may therefore pa trough everal cycle during the ampling interval a long a the maximum difference in it outcome i le than 2 n. Thi property let u reduce the internal word-length in the modulator without looing any information about the ignal itelf. By uing a maller module than the maximum number of received riing FM edge during T, the modulator output will be repreented in modulo-2 n arithmetic. In reference [] it i hown that an efficient way to implement the firt tage of the decimator may alo be done in modulo-2 n arithmetic. Therefore, if a decimator where the firt tage are baed on modulo-2 n arithmetic i choen, no interfacing i required. The modulo-2 n output word-tream may alo eaily be converted to a tandard repreentation by adding a proper bia and diregarding the carry bit. The minimum number of received riing edge during T / will be the integer part of (f c - f)/. If (f c f)/ i not an integer, which i only of mathematically interet, the maximum number of received riing edge will, a illutrated in Fig. 2.9, be the integer part of (f c f)/ a the ampling period may be hifted in time. If / i cloe to an integer multiple of /f c, the minimum variation in the counter outcome may therefore even for very mall ignal range be 3. For the baic modulo-2 n FDSM, the module may in general, be choen to be the mallet integer larger than f int c f f int f c f f f int int( SR o ) 2, (2.2) where int(x) i the integer part of x. The minimum internal word-length will then be log 2 ( int( SR o ) 2), (2.2) and the output bia component due to f c will be clipped down to mod-2 n (f c / ). For low output ignal range the hortet internal word length will therefore generally be two bit. No counter reetting i needed, and the ampling peed may be coniderably higher than by uing the traditional count, dump and reet converter. 2

8 Chapter 2 The firt-order FDSM a) fm(t) /(f c - f) 2 3 / /(f c f) b) fm(t) / Fig. 2.9 a) Minimum number of received riing FM edge during /. b) Maximum number of received riing FM edge during / Counter readout The counter reading operation may be conidered a a data tranfer between two independently clocked ytem a the counter i aynchronou to the ret of the ytem. When a multi-bit word i to be tranferred between two uch ytem, great care mut be taken to avoid ituation when the receiving ytem trie to read the data at the ame time a more than one bit change. In that ene, the binary data repreentation i not well uited, and if a binary counter i to be ued, a eparate ynchronizing circuit mut be applied (e Chapter 5). There are however other way to overcome thi problem, and one way i the ue of Gray code, either by a modulo-2 n Gray code counter or a binary counter followed by a binary to Gray code converter. Both olution will require ome more logic, and a Gray to binary converter mut alo be applied. Another olution may be uing a ring-counter followed by a binary encoder. If the counter length i large thi olution will however require a large encoder and a lot of wiring. Sytem-level imulation To verify the theory, and imulate the ideal behavior, everal ytem level imulation have been carried out. Detail of the imulator are given in Appendix B. There are everal more or le ophiticated way to etimate the output power pectral denity (pd) from the imulated word-tream y k (reference [2,3]). Throughout thi thei, the mot traight-forward and commonly ued FFT technique where the pd i etimated by the periodogram etimator [3] given by I( ω) N w NU k y k e j k, (2.22) i ued. In thi expreion, N i the number oample, w k a properly choen window and U a caling contant which compenate for the window gain. To better illutrate the SNR, the caling factor U will throughout thi thei, be choen to let db repreent the maximum input ignal amplitude. When working with high SNR -Σ output pectrum, a high window idelobe uppreion factor will be deirable, and a 6-term Blackman-Harri-Hodie window (Appendix B), which i pecially uited for high SNR analyi i therefore ued in all computation. In Fig. 2., the etimated output pd for a baic modulo-2 2 FDSM where 2MHz, f c MHz and the input i a ingle inuoid with maximum amplitude and frequency Hz i hown. The maximum input ignal amplitude i defined a the amplitude that produce a maximum intermediate frequency deviation of ±%. By thi choe of circuit parameter, the modulator SR o will from Eq. (2.2) be 2 6 /2 6, which i the ame a for the traditional firt-order DSM imulation in Chapter. The reult in Fig. ωk 2 22

9 2.3 The baic modulo-2n FDSM 2 Normalized amplitude (db) Fig Frequency (Hz) A 2 8 point FFT analyi of the ideal baic modulo-2 2 FDSM output. Max ignal amplitude, ignal frequency Hz, 2MHz and f c MHz 2 2 Normalized amplitude (db) Normalized amplitude (db) Frequency (Hz) Frequency (Hz) a) b) Fig. 2.2 Two 2 8 point FFT analyi of the baic modulo-2 2 FDSM output for 5MHz and f c 22MHz. a) Max ignal amplitude, ignal frequency.7khz. b) Signal amplitude. Max, ignal frequency 4KHz 2. may therefore directly be compared to the reult in Fig..6a. A we ee, the two pectrum are quite imilar with the ame 2dB/decade lope, and the -Σ noie-haping behavior of the FDSM i confirmed. Compared to Fig..6a, the FDSM pectrum i mother with le pattern noie. Thi i only a conequence of the different quantization level location. For the traditional DSM imulation, the inuoidal input ignal have it peak value equal to the quantization level. The ignal will then, for a longer period, be in the large pattern noie end-peak ection, illutrated by Fig..3, than the FDSM output ignal which have it integer quantization level in the middle of it output ignal range of [4.5,5.5]. 23

10 Chapter 2 The firt-order FDSM For the FDSM, a higher SQNR may be obtained by increaing the enitivity k of the frequency modulator. In Fig. 2.2a, an example illutrating the gain in SQNR achieved by the ue of a higher carrier and ampling frequency i hown. The carrier frequency where et to 22MHz and to 5MHz, and the SQNR hould theoretically from Eq. (2.9) be increaed by 4dB. By increaing and keeping the ame N we mut compenate for the decreaed bin-with and we hould expect the FFT noie-floor to be lowered by 4- log(5/2) 27dB. By looking at Fig. 2.2a, thi agree with the imulated reult. In Fig. 2.2b, the input ignal frequency i raied to 4KHz and the ignal amplitude i decreaed by a factor of.. A we e, the modulator repond a expected. In a ideal noie free imulation like thi, the high frequency quantization noie pectrum will break down when the input ignal amplitude i decreaed, and for zero input ignal amplitude, only ome part of the pattern noie will remain. Thi will however not be the ituation in a practical noiy environment where power upply, tranitor and ubtrate noie will act a a dither ignal and maintain mot of the noie pectrum (e Chapter 6). 2.4 The D flip-flop FDSM From the previou dicuion, by uing a module le than the maximum received number of FM edge during T, the minimum FDSM internal word-length will, in general, be two bit. But if the maximum received number of FM edge during T i maller than two, we may without riking ignal aliaing ue modulo-2 arithmetic. Thi follow from the fact that the maximum difference in the counter outcome will be two, which will be accommodated by modulo-2 arithmetic. By uing modulo-2 arithmetic and diregarding the borrow bit from the ubtractor, the ubtractor may be implemented imply a a XOR gate. A one-bit modulo counter will, in addition, eaiet be implemented a a double edge counter, ince a one-bit modulo counter triggered by both riing and falling edge i equivalent to a D flip-flop. The entire FDSM may therefore be implemented a a frequency modulator connected to a D flip-flop followed by a one-bit regiter and a XOR gate a illutrated in Fig x(t) θ(t) fm(t) D CK Q reg output bit-tream frequency modulator Fig. 2.3 The D flip-flop FDSM The operation of the D flip-flop FDSM may alo be conidered a a frequency modulator connected to a ynchronizer or direct bit-tream converter a illutrated in Fig From thi dicuion we notice the cloe relationhip between the FM repreentation oignal and the firt-order -Σ noie-haped bit-tream. By riing the /f c ratio a illutrated in Fig. 2.4b, the bit-tream will directly approach an exact repreentation of the analog information which in the FM ignal i given by the zero croing or edge poition. In that ene, the firt-order -Σ noie-haped bit-tream may alo be conidered a a quantized FM ignal. Since the D flip-flop FDSM i counting both riing and falling edge, it SQRN will be given by k SR SQNR 2 i π log f max log, (2.23) f 2 36 f and if the frequency modulator i already implemented in the ignal ource, we may for FD applica- 24

11 2.4 The D flip-flop FDSM a) FM out b) FM out Fig. 2.4 The D flip-flop FDSM intermediate/output ignal. a) Modet /f c ratio. b) High /f c ratio tion, put it a SQNR 2 f π log f max log. (2.24) 36 Compared to the traditional DSM, the output ignal range in the D flip-flop FDSM will for a high /f c ratio be very mall, and by locating the output ignal range well away from the main pattern noie peak illutrated in Fig..3, we may achieve a lightly higher SQNR than the theoretical value ince the pattern noie problem in thi way may be eliminated. Sytem-level imulation A high-level D flip-flop FDSM imulator have been made (for detail, ee Appendix B), and by following the ame procedure a in the previou ection, the pd i etimated by FFT analyi of the ideal output bit-tream. Several imulation have been carried out, and in Fig. 2.5a, the etimated output pd i hown for a D flip-flop FDSM with MHz, f c 4MHz and a maximum frequency deviation of ±%. A we ee, the noie pectrum i haped according to the theory with a lope of 2 2 Normalized amplitude (db) Normalized amplitude (db) Frequency (Hz) Frequency (Hz) a) b) Fig. 2.5 A 2 8 point FFT analyi of the D flip-flop FDSM output for max input ignal amplitude, input ignal frequency 343Hz MHz and f c 4MHz. a) 5/5 FM duty-cycle. b) 35/65 FM duty-cycle 2dB/decade. There are ome high-frequency pattern noie, but for low and medium frequencie, the pectrum i quite mooth. Compared to the baic modulo-2 2 pectrum hown in Fig. 2., the SQNR will from Eq. (2.9) and Eq. (2.24) be increaed by 35dB, and we hould expect the noie floor to be lowered by 35- log(/2) 8dB. A we ee, the noie floor i further lowered by 25

12 Chapter 2 The firt-order FDSM almot db, which i a conequence of the ignal range location in the quantization level interval and the low ignal range. To illutrate the effect of duty-cycle diverion, the ame imulation where done with a FM duty cycle of 35/65, and a we ee from Fig. 2.5b, the noie floor i jut lightly raied. 2.5 The pointer-fdsm 3 2 Fig. 2.6 The different tate of a 3-inverter ring ocillator In ome application the frequency modulator may be implemented a a ring ocillator, where the propagation delay of each inverter i modulated by the input ignal. Dependent on the architecture, the modulating ignal may be given either a current or a voltage or even a a directly meaured phyical parameter. Example are: Current controlled bipolar ring ocillator [4], acceleration modulated ring ocillator, and for a particular application, Schlumberger-Geco-Prackla made a preure modulated ring ocillator where the inverter where located on a ilicon membrane. A particularly imple voltage controlled ocillator (VCO) may alo be implemented by tandard CMOS inverter connected in ring where the frequency i modulated by the inverter power upply voltage. Although the exact relationhip between the power upply voltage and the loop frequency i quite complex, Spice imulation indicate that the loop frequency i a urpriingly linear function of the power upply voltage over a large range (Fig. 2.7). In uch a VCO, there will be no power upply noie in the traditional ene. By conidering the ring ocillator itelf a a modulo-m counter, we may both implify the FDSM, and increae the reolution. The ring ocillator node value may be conidered a a cycling binary tate vector with 2m different tate where m i the number of node or inverter (Fig. 2.6). The operation of the ring ocillator may be decribed by a tranition flank running trough all inverter in equence, and by looking at the tate diagram, we realize that at a given intant, all neighboring node will, apart from the two at each ide of the flank, have their complementary value. The logical XNOR or equivalence function between each neighboring node will therefore provide a active high pointer output which will run trough all node in equence with a loop frequency twice the overall ring ocillator frequency (Fig. 6). By ampling the node value by D flip-flop, and generating the logical XNOR between each neighboring node, the m bit pointer vector coniting of one and m- may be fed to a imple binary encoder, providing a ampled modulo-m repreentation of the tate of the ocillator (Fig. 2.8). The output may then be differentiated to form a modulo-m repreentation of the number of pointer hift during T. Compared to counting each riing FM edge, the pointer-fdsm will therefore, in addition, provide quantized phae information by counting 2m time for each overall FM period and thereby increaing the reolution. The maximum number of pointer hift during T will be T /(τ -τ δτ) where δτ i the maximum diverion in propagation delay relative to the unmodulated propagation delay of one inverter τ. Together with the minimum number of pointer hift T /(τ τ δτ) the effective output ignal range 26

13 2.5 The pointer-fdsm 4 x 6 2 Frequency (Hz) Fig. 2.7 The frequency of a 5-inverter CMOS ringocillator a a function of the inverter power-upply voltage imulated by Spice. The traight line i fitted to the meaured data by linear regreion will be Input (Volt) SR o T T τ ( δτ) τ ( δτ) 2δτ , (2.25) τ ( δτ 2 ) and for δτ<< it may be implified to SR o 2δτ τ. (2.26) A we ee, the SR o i proportional to the maximum relative propagation delay diverion, and inverely proportional to the ampling frequency and the unmodulated inverter propagation delay. From Eq. (2.26) we alo notice that for a given inverter propagation delay, the reolution of the pointer-fdsm i independent of the number of inverter. The minimum number of inverter or module mut however till be larger than int(sr o 2) to avoid ignal aliaing. The ring ocillator carrier frequency may be expreed a f c , (2.27) 2τ m and ince the maximum relative frequency deviation f/f c will be equal to δτ, we may alo expre the output ignal range a 4m f SR o , (2.28) which i 2m time larger than for the baic modulo-2 n FDSM. Since the number of inverter m in a ring ocillator mut be odd, the output of the binary encoder can not be repreented in modulo-2 n arithmetic, and a tandard binary ubtractor can not be applied. 27

14 Chapter 2 The firt-order FDSM To overcome thi obtacle, ome extra logic i required. By uing 2 n - inverter, and two binary ubtractor a illutrated in Fig. 2.8, we achieve a modulo-m repreented output difference, and by finally adding a proper bia modulo-2 n to the reult, we arrive with a tandard repreented output. The binary encoder 4-bit reg borrow _ 4-bit _ 4-bit modulo-5 output word-tream Fig. 2.8 A 5-inverter pointer-fdsm. The outer ring ymbolize the individual D flip-flop and XNOR unit modulo-m ubtraction may probably be implemented in a impler way, but thi propoal jut illutrate the principle. In a practical implementation there will be proce dependent diverion amongt the different inverter delay and within the D flip-flop threhold. Such error may be conidered a phae offet and will a duty-cycle diverion be ytematic error. Simulation indicate that the effect of phae offet will, in the overall SNR, correpond to the effect een by duty cycle diverion in the D flip-flop FDSM, and will thu be of le ignificance. If the unmodulated and maximum inverter delay i given, the SQNR of the pointer-fdsm will be SQNR 2 τ π log f max log. (2.29) τ 2 36 f If the ring ocillator carrier frequency and max frequency deviation i given we have SQNR 2 m---- f 2 π log f max log. (2.3) 36 For the ame f c and f, we notice that the dynamic range i increaed by m compared to the D flip-flop FDSM. Sytem-level imulation Several ytem-level imulation have been carried out to verify the theory and the ideal behavior of the pointer-fdsm. In Fig. 2.9a, the etimated pd for a 5-inverter pointer-fdsm output i hown. A 3.33n inverter propagation delay i choen which will provide a carrier frequency of MHz. The input i a ingle inuoidal ignal with maximum amplitude and a frequency of Hz. To match the imulation to the meaured reult in Chapter 6, the maximum frequency deviation i et to 5%. A we ee, the pectrum i haped according to the theory. Compared to the baic modulo-2 n FDSM pectrum in Fig. 2., the noie floor hould from (2.9) and (2.3) be lowered by 24dB which i approximately the imulated reult. In Fig. 2.9b, the ame imulation i carried out for randomly choen phae offet in the range [,> rad. A we ee from the figure, the noie floor i inignificantly raied, and due to the dithering effect it i lightly mother than for the ideal imulation. 28

15 2.6 Reference/differential realization 2 2 Normalized amplitude (db) Normalized amplitude (db) Frequency (Hz) a) b) Fig. 2.9 A 2 8 point FFT analyi of an ideal 5-inverter pointer-fdsm output. Max input ignal amplitude, input ignal frequency Hz, f c MHz and 2MHz. a) Ideal modulator. b) Modulator with randomly choen phae offet in the interval [,> An application example Frequency (Hz) For the pecific Schlumberger-Geco-Prackla preure enor, the pecification are: SNR2dB, ignal bandwidth eimic bandwidth:4hz, maximum power conumption 5mW, maximum ampling frequency 2MHz and f/f c 5-%. For the above imulated FDSM where f/f c i et to 5, the SQNR will from Eq. (2.3) be 22dB, and from the imulated reult in Fig. 2.9a we may conclude that thi ring ocillator will jut provide the neceary reolution. By decreaing the inverter propagation delay and/or riing f/f c to %, a ufficient margin will be provided. A the FD part of the converter i excluively digital, the power conumption will be well below the 5mW requirement Reference/differential realization To reduce the impact from common mode noie, differential DSM architecture are widely ued. In the FDSM ytem, a differential realization eem to require two independent frequency modulator, and the ingle FDSM output may then be implemented by ubtracting the output from the original counter from the reference counter output. The new quantization error will then be the difference between the original quantization error and the reference ignal quantization error. Since there are no correlation between the two quantization error, the new quantization error pdf will have triangular hape panning from - to, and it RMS value will be 2 e 2 rm ( ref) 2e 2 rm. (2.3) e 2 rm ( tot) e rm If a differential mode i choen, the output ignal amplitude will be doubled and the reult i a net SQNR gain of 3dB. On the other hand, if the reference ocillator i not modulated, a lo of 3dB will reult. 29

16 Chapter 2 The firt-order FDSM 2.7 Feature and performance characterization of the firt-order FDSM ytem In the following ection the different feature of the firt-order FDSM ytem will be compared to the traditional DSM. Pattern noie A we have een, the FDSM i mathematically equivalent to a traditional DSM where the input ignal i caled and biaed. Therefore, the pattern noie propertie will be the ame a in the traditional DSM. For the baic modulo-2 n and the pointer-fdsm, the output ignal RMS value may however, due to multi-bit quantization, be large compared to the pattern noie. For the D flip-flop FDSM, the output center value will be f c /, and by locating thi value well away from the main DC pattern noie peak, the pattern noie problem may be eliminated for mall ignal range. DAC output level Due to the abence of a DAC, problem due to miplaced DAC output level will be eliminated, and multi-bit quantization i traight-forward. ADC threhold In the FDSM, the counter value mut be conidered a a quantized analog value a the counter i aynchronou. By ampling the counter value, both quantization and ampling have been executed, and an equivalent AD converion have been carried out. In the baic modulo-2 n FDSM, the ingle counter threhold which i ued to decide if the FM ignal i high or low, may be placed anywhere it will be convenient from a digital conideration. In the D flip-flop and the pointer-fdsm, there will in a practical implementation, be ome duty-cycle and phae diverion from the ideal. Thee diverion may be conidered a miplaced ADC threhold, but due to the differentiation, the baeband noie will be heavily uppreed. A oppoed to the traditional DSM, thee error will be very little correlated with the input ignal, and a the imulation indicate, have le practical ignificance. Such error hould however be minimized a large offet may lightly degrade the overall SNR. ADC overloading Since the ADC i implemented by a counter and the number of output level may eaily be choen larger than the output ignal range require by increaing the internal word length, ADC overloading will not be a problem. Integrator error In a frequency modulator, there will be no leakage, charge injection and lew-rate limitation, and for the FDSM, the only limiting factor for high ampling peed, and thu high OSR operation may be the decimating filter. The main problem i however the fact that all frequency modulating noie in the frequency modulator will add directly to the ignal. Dependent on the architecture of the frequency modulator and the application, harmonic ditortion may be a problem. By reducing f/f c, the maximum non-linearity of a frequency modulator will normally decreae, and due to the high reolution of the -Σ modulator, a low f/f c may be utilized to reduce harmonic ditortion. If the frequency modulator i already implemented in the ignal ource, the FDSM concept may therefore be ued to improve harmonic ditortion in a FD ytem by enabling the ue of a lower f/f c ratio. External noie In the FDSM ytem a in the traditional DSM, everal external noie factor will be preent. A we have both the ignal and it integral analogue repreented in the circuit, we may differ between noie that affect the ignal (frequency modulating noie) and noie that affect the integral of the ig- 3

17 2.7 Feature and performance characterization of the firt-order FDSM ytem nal (phae modulating noie). In general, phae modulating noie will due to the differentiation be firt-order noie haped, and will normally be of no ignificance compared to the quantization error. In thi category we have ampling clock jitter, power upply noie in the θ n detector/quantizer and digital/tranmiion noie deteriorating the intermediate FM ignal. Frequency modulating noie will however directly add to the ignal, and mut be carefully conidered. In thi category, we may, depended on the architecture, have power upply noie in the frequency modulator, and low frequency noie caued by the frequency modulator enitivity to temperature drift. By uing a reference frequency modulator, the impact from uch factor may be ignificantly decreaed. Another noie ource that hould not be overlooked, i frequency modulating noie in the ampling clock ocillator. By uing an intermediate FM ignal, the ampling clock frequency mut be conidered a a reference ignal, and a frequency table clock ocillator mut be ued. By uing a reference modulator we convey the tability requirement from the clock ocillator over to the reference input ignal. The integrator-differentiator combination A in a conventional DSM, by uing an analog loop filter, the frequency repone of the continuou-time integrator - dicrete-time differentiator combination i not contant. To examine thi effect, the impule repone of a continuou-time integrator i given by H i (jω)/jω, and in the frequency interval ω <2π /2, the Fourier tranform of the ampled impule repone equence i Y(e jωt ) H i (jω). Together with the accumulator frequency repone H a (e jωt )(-e -jωt ), the overall frequency repone will be and the magnitude will be ( ) H i ( jω)h a e jωt f ( ) ( e jωt ) ω < πf, (2.32) jω in( ω ( 2f ( ) 2 )) ω < πf. (2.33) ω Due to the ingle pole at zero, the maximum in band ignal uppreion will be een for the maximum ignal frequency, and the low pa filtering effect will be mot noticeable for ytem with a low OSR. But a an example, for MHz and f max 2KHz which correpond to an OSR a low a 25, the maximum ignal amplitude diverion in the paband will be H() He ( j2πf max T ) 45dB, (2.34) A we ee, the continuou-time integrator - dicrete-time differentiator combination caue no practical problem. Implementation He jωt He jωt The implementation of a FDSM ytem i very different from the implementation of a traditional DSM, and the frequency modulator may, dependent on the application, be implemented in everal way. If the input ignal i already given a a FM carrier, the neceary extra implementation will be purely digital. The CMOS pointer-fdsm where the carrier frequency i modulated by the inverter power upply voltage, i an example which illutrate an AD converter build excluively by digital component, and a tandard digital CMOS proce may be ued. By uing only a few digital component, a low power upply voltage operation and a reduced power conumption i poible. 3

18 32 Chapter 2 The firt-order FDSM