Published in: 2009 IEEE 6th International Power Electronics and Motion Control Conference, IPEMC '09

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1 Topology comparion and deign optimiation of the buck converter and the ingle-inductor dual-output converter for ytem-in-package in 65nm CMOS Haizoune, F.; Bergveld, H.J.; Popovi-Gerber, J.; Ferreira, J.L. Publihed in: 9 IEEE 6th International Power Electronic and Motion Control Conference, IPEMC '9 DOI: 1.119/IPEMC Publihed: 1/1/9 Document Verion Publiher PDF, alo known a Verion of Record (include final page, iue and volume number) Pleae check the document verion of thi publication: A ubmitted manucript i the author' verion of the article upon ubmiion and before peer-review. There can be important difference between the ubmitted verion and the official publihed verion of record. People intereted in the reearch are advied to contact the author for the final verion of the publication, or viit the DOI to the publiher' webite. The final author verion and the galley proof are verion of the publication after peer review. The final publihed verion feature the final layout of the paper including the volume, iue and page number. Link to publication General right Copyright and moral right for the publication made acceible in the public portal are retained by the author and/or other copyright owner and it i a condition of acceing publication that uer recognie and abide by the legal requirement aociated with thee right. Uer may download and print one copy of any publication from the public portal for the purpoe of private tudy or reearch. You may not further ditribute the material or ue it for any profit-making activity or commercial gain You may freely ditribute the URL identifying the publication in the public portal? Take down policy If you believe that thi document breache copyright pleae contact u providing detail, and we will remove acce to the work immediately and invetigate your claim. Download date: 18. Jul. 18

2 Topology Comparion and Deign Optimiation of the Buck Converter and the Single-Inductor Dual-Output Converter for Sytem-in-Package in 65nm CMOS F. Haizoune 1, H.J. Bergveld, J. Popovi -Gerber 1, J.A. Ferreira 1 1 Electrical Energy Converion, Delft Univerity of Technology, The Netherland Mixed-Signal Circuit and Sytem, NXP Semiconductor, The Netherland Abtract- Portable electronic device, uch a laptop computer and peronal portable electronic device are battery-powered and need power-electronic converter a an interface between the battery and the load. To enure a long battery life, it i important that the power-electronic converter operate at high efficiency. The volume available for power electronic i limited which neceitate the ue of integration technologie to achieve high-power-denity converter. Integrating paive component in ilicon make monolithic integration of power converter in ytem-on-chip difficult and hybrid integration in the form of ytem-in-package where paive component are implemented in alternative technologie and integrated in the package eem to be a more feaible option at preent. High operating frequencie, neceary for the reduction of the paive component ize reult in the increae of witching loe in the power emiconductor which negatively influence the efficiency. Furthermore, power emiconductor loe are directly dependent on the chip ize which in turn influence the cot of the converter. Alo, the loe are dependent on the time waveform of electrical current and voltage which in turn depend on the choen circuit topology. The paper preent a topology comparion and a deign optimization procedure for the implementation of a DC-DC converter (V in 3V 4.V from Li-ion battery, V out.6v 1.V, load current< everal 1mA). It i aumed that the active part of the converter i implemented in 65nm CMOS technology. A high-level topology evaluation baed on everal criteria uch a efficiency, cot, technology feaibility and ize i preented. The deign procedure for maximum integrated DC-DC converter efficiency by mean of finding optimum tranitor width i preented and illutrated on two topologie. I. INTRODUCTION Current trend in portable conumer electronic demand progreively lower voltage upplie. Portable electronic device, uch a laptop computer and peronal portable electronic device are battery-powered and need powerelectronic converter a an interface between the battery and the load. The number of feature implemented in mobile deviceincreae dramatically leading to a large number of different upply voltage, all of which need to be generated from a ingle battery voltage. To enure a long battery life, it i important that the power-electronic converter operate at high efficiency. Furthermore, the volume in the device available for power electronic i normally very limited which neceitate the ue of integration technologie to achieve mall volume and high power denitie of power electronic. Integrating paive component in ilicon make monolithic integration of power converter in ytem-on-chip difficult [1] and hybrid integration in the form of ytem-in-package (SiP) where paive component are implemented in alternative technologie [], [3] and integrated in the package eem to be a more feaible option at thi point in time. In order to make the integration of paive component in the package poible they have to be reduced in ize, which i achieved by operating the converter at high witching frequencie and thu reducing the volume of paive component required for energy torage. However, the witching frequency increae reult in the increae of witching loe in the power emiconductor, which negatively influence the efficiency. Furthermore, the power emiconductor loe are directly dependent on the chip ize which in turn influence the cot of the converter. Alo, the loe in all component are dependent on the time waveform of electrical current and voltage, which in turn depend on the choen circuit topology. All thee factor need to be taken into account in order to come to an optimum deign that fulfill the high-efficiency, mall-ize and low-cot requirement. In thi paper, a deign procedure for achieving highet efficiency for a choen topology will be preented. Firtly, a literature tudy on feaible converter topologie wa carried out and the topologie were evaluated on the bai of everal criteria. The topology choice will be limited to inductive topologie due to their ability to enable good control of the output voltage over input voltage and output-load variation by mean of controlling the duty cycle of the power witche uing fewer paive component than capacitive converter. Two mot promiing topologie, namely the conventional buck converter and the ingle-inductor dual-output converter, will be conidered and the two-tep deign procedure for achieving the 95

3 highet efficiency will be demontrated on thee two topologie. It i aumed that the active part of the converter i implemented in 65nm CMOS technology with the intention to integrate the load and converter in the later tage. II. TECHNOLOGY PLATFORM The available technology largely influence the topology choice in particular concerning the integration of paive. In thi work, the proprietary ilicon-baed proce Paive-Integration Connective Subtrate (PICS TM ) that provide a platform for the integration of reitor, capacitor and inductor [4][5] i ued. It offer everal advantage for realizing integrated DC-DC converter. Firt, it achieve large capacitance denitie by utilizing trench-mos capacitor. The typical value ued in demontrated prototype i 8 nf/mm [][6] and the recent reult go a high a 4 nf/mm [7]. Secondly, an 8- m thick copper top-metal layer available in thi technology in addition to the firt aluminium metal layer enable the deign of piral air-core inductor with reaonable performance. Figure 1a how a two-die SiP approach. The driver and power tranitor are implemented in a CMOS die. The paive component, on the other hand, are realied on a Active CMOS die a. Air core inductor PICS die, which i connected to the CMOS die by mean of flip-chip older bump. Figure 1b how a technology demontrator howing the feaibility of thi concept on an integrated DC-DC down converter []. The figure how the active die flip chipped onto the paive die containing the planar nh air-core inductor and input and output capacitor. The realized SiP converter fit inide a tandard QFP64 package. The boundary condition of thi technology and the SiP approach will be ued a input to the deign optimization procedure. The deign with both an air core inductor and a magnetic core inductor will be invetigated and compared. III. FIRST LEVEL TOPOLOGY SELECTION The pecification of the choen cae tudy DC-DC converter are: input voltage 3V 4.V from a Li-ion battery, output voltage.6v 1.V, load current up to everal hundred of ma. The primary election of topologie wa baed on the reult of the previou development made in the field of integration of low-power converter including the author knowledge and literature. Thee topologie were then qualitatively evaluated on the bai of everal criteria: efficiency, ize, cot, tranient repone and technological feaibility. The detail of the topologie are available in the literature and will not be given here [8]-[14]. A weighing factor wa aigned to each criteria depending on how important the criteria i for thi application. The total core i not intended to give an abolute reult of which topology i the mot optimal, but rather to help eliminate the wort coring topologie. Table 1 how the reult of the evaluation with ome explanation to jutify the core. Baed on the reult of the evaluation two topologie were evaluated further, the buck (in CCM and DCM) and the Single Inductor Dual-Output (SIDO) converter. IV. CIRCUIT TOPOLOGIES AND LOSS MODEL The ynchronou buck converter i widely ued in indutry due to it implicity and low number of component. Both Continuou-Conduction Mode (CCM) and Dicontinuou-Conduction Mode (DCM) of operation will be modelled and compared. b. Figure 1a. Two die SiP approach: paive PICS die and CMOS active die b. SiP DC-DC converter demontrator (input 1.8V, output 1.1V@1mA, 8MHz) TABLE 1 FIRST LEVEL TOPOLOGY EVALUATION Criteria FoI Synchronou Interleaved Cla- E Inductor Single Inductor Buck Buck Multiplier Dual-Output Efficiency 3 /3 (integr. 3/3 /3 (circulating current in re. 1/3 (loe almot X that /3 (additional witche) inductor) tank) of off-chip inductor) Size 3 3/3 /3 (multiple tage) 1/3 (multiple converion tage) 3/3 3/3 Cot 3 3/3 /3 (add. control circuitry) 1/3 (large ilicon area) 3/3 3/3 Tranient Repone 3/3 3/3 /3 (ize of RF input inductor) 1/3 (ripple cancellation) /3 (regulation of different output) Feaibility 3 3/3 3/3 3/3 3/3 3/3 Total 39/4 36/4 5/4 3/4 37/4 96

4 Figure Circuit chematic a. ynchronou buck converter b. Single-Inductor Dual-Output (SIDO) converter The SIDO converter wa choen due to it capability to upply two output with different voltage level which i required in many application. The performance of the SIDO converter will be compared to the performance of two buck converter. Figure how the circuit chematic of both topologie. Analytical model of the circuit operation of both topologie were made (in Matchad) and the loe in the component were calculated uing the relevant voltage and current waveform and component phyical characteritic. The calculation of the converter loe include the inductor lo, the input and output capacitor loe and the loe in the witche. The loe in the gate driver have not been included. A. Inductor lo The loe in the inductor are obtained by uing the following equation: L, RMS PL, lo = I ESR (1) L where ESR L i the equivalent erie reitance of the inductor (repreenting the conductor loe and additional core loe in the cae of an inductor with a magnetic core). Two particular inductor deign were ued in the following optimiation procedure; a piral air-core inductor with the inductance value of L air = 18.9nH and a thin-film electroplated magnetic core inductor with the inductance value of L core = 19.9nH. The prototype of thee inductor were already available and the ESR and L for both inductor wa obtained by mean of curve fitting of the experimental reult. B. Power MOSFET loe The MOSFET loe in both PMOS and NMOS conit of conduction loe and witching loe. The conduction loe in the PMOS and NMOS can be obtained by the following equation [15][16]: P con, PMOS = D I L, RMS Rd, ON, PMOS () P con, NMOS = ( 1 D) I L, RMS Rd, ON, NMOS (3) where R d,on i the on-reitance of the tranitor dependent on the tranitor width and can be calculated a: R d, ON Ron = (4) WidthOpt where R d,on i the normalized ON-reitance of the witch [ m]. The witching loe of integrated power tranitor are the loe due to charging and dicharging of the equivalent paraitic capacitance [17]-[19]: P w PMOS = Ceq PMOS Vdd f (5),, P w NMOS = Ceq NMOS Vdd f (6),, Thee equation give a implitic repreentation of the MOSFET loe a they do not conider any dependency of the witching loe on the inductor current during the witching tranition a well a the witching interval duration. A a conequence, the lo reduction due to potential oft witching condition i not included. The capacitance value C g, C d and C gd of the MOSFET are proportional to the ize of the tranitor, and they are non-linear (depend on the working region of the tranitor). For the implicity ake, the non-linearity effect i neglected, and the capacitance value are conidered to be contant for a given width and equal to the value valid when the tranitor i operating in linear region. The equivalent capacitance of the MOSFET under hard-witching condition i given a follow: C = C + C + C (7) eq g gd d and can be calculated a the function of the tranitor width a: C eq = Ceq WidthOpt (8) where C eq i the normalized witch equivalent capacitance [F/ m]. V. DESIGN PROCEDURE AND OPTIMISATION STRATEGY The tradeoff involved in increaing the witching frequency were dicued in Section I. In thi ection, a deign procedure for finding optimal width of the tranitor to achieve the bet efficiency will be preented. The deign procedure will be performed in two tep, coare and fine optimiation. Figure 3 how the flow diagram of the complete procedure. A. Coare optimiation tage In the firt tep, an analytical model of the topology i derived and implemented in Matchad. The model give the time waveform of current and voltage auming the ideal 97

5 component characteritic, which mean that they do not include the voltage drop caued by the on-reitance of the witche and the ESR of the inductor. The width of the tranitor that offer the minimum power diipation can be found by differentiating the total lo of the power witch a follow: d (9) ( PTot, PMOS) = ( C d( Width) eq V dd f ) ( D I L, RMS ( R d, ON 1 Width PMOS )) = The optimum PMOS and NMOS width for minimum total loe can be expreed a: Width Width PMOS NMOS Width OPT Add tranitor ize to the circuit model (D, V in, f ) (Cadence) I outcadence,v outcadence P loecadence, Cadence ( f ( f f,opt Tet converter performance to load change (Cadence) I L, rm ( f) D Rd, ON, PMOS ) = Ceq, PMOS Vdd f I f Start Make frequency dependent model and determine optimum tranitor ize and parameter (MathCAD) C eq, R don D,V in, f S Do Cadence imulation reult correpond to MathCAD reult? Find optimum converter operating point DV in Do Cadence imulation reult correpond to MathCAD reult? Stop D R L, rm( ) (1 ) ) = Ceq, NMOS Vdd Make frequency dependent model including R d,on and ESR L (MathCAD) I outmathcad, V outmathcad P loemathcad, MathCAD L opt, f,opt Tet converter performance to load change (MathCAD) Figure 3 Deign procedure flow chart d, ON, NMOS f Coare Optimiation Fine Optimiation Check converter performance (1) (11) Once the optimum tranitor width i calculated, R d,on (f ) and C eq (f ) are obtained from the equation (4) and (8), which are then ued to calculate the loe in the converter a preented in Section II. From the graph howing efficiency v. witching frequency, the frequency giving maximum efficiency, f,opt, i identified. Thi frequency correpond to the optimum tranitor width Width opt, which i then ued a an input for the fine optimiation tage. A. Fine optimiation tage To validate the deign olution, ytem-level imulation have been performed in Cadence uing real tranitor model. The cro-check of the reult obtained in the analytical model (in Mathcad) with the reult obtained from imulation (Cadence) i performed in thi tage. When the two reult match it can be concluded that the computational model i accurate enough to model the behaviour of the converter and, therefore, the model can be validated. In the fine optimiation tage, the converter paraitic reitance obtained from the coare tage are then included in the converter model. Conequently, a new et of formula ha to be derived which conider the voltage drop caued by the circuit paraitic erie reitance. However, adding the circuit paraitic in the model may hift the optimum witching frequency value (ince the paraitic are frequency-dependent). Therefore, by weeping the frequency in the fine model, a new optimum frequency value f,opt,fine i obtained. Note that the tranitor width remain fixed during the fine optimiation tage, wherea in reality thee width are frequency-dependent. It will be hown later that changing the width lightly around the optimum value will not have a ignificant impact on the converter efficiency, which mean that the aumption above i valid. VI. MODELLING AND SIMULATION RESULTS Following the optimiation procedure decribed in Section III, the performance optimiation of the buck converter operating in CCM and DCM and the SIDO converter ha been carried out. The procedure ha been performed for both the air-core inductor and the magnetic-core inductor decribed in ection IV A. A. Buck converter in CCM Figure 4a how the converter efficiency a a function of the witching frequency. It can be een that maximum efficiency ( = 61.1%) i achieved at f,opt = 145 MHz. Figure 4b how the total lo a a function of the tranitor width. It can be een that there i a relatively large area where the total loe remain low for different value of the tranitor width. Thi mean that a light change of the tranitor width around the optimum ize will not have a ignificant impact on the efficiency. Thi i important ince the width of the tranitor will be fixed for the fine optimiation tage, a explained in Section V. Now that the tranitor width have been fixed the voltage drop caued by the on-reitance of the witche and the inductor ESR will be included in the model. When the PMOS i on, the inductor voltage i given by the following equation: VL = Vin Vout Iout ( Ron, PMOS + ESRL ) (1) When the NMOS i on, the inductor voltage i: V = V I ( R + ESR ) (13) L out out on, NMOS L Applying the volt-econd-balance principle, the modified duty cycle value i given by: 98

6 D ccm Vout + Iout ( Ron, NMOS ( f) + ESRL ( f )) ( f ) = V I ( R ( f ) R ( f )) in out on, PMOS on, NMOS (14) higher inductance value and lower erie reitance. A a reult, the inductor current ripple remain lower than in the cae of inductor with air-core. (a) Figure 4 Buck converter in CCM with air-core inductor coare optimiation a. Efficiency v. frequency b. Loe in the witche v. tranitor width Applying the modified expreion of the duty cycle and current ripple, the total loe of the converter are calculated. Figure 5a how the individual component lo contribution and the total lo veru frequency. The inductor loe at low frequencie are dominated due to a high current ripple. A the operating frequency increae, the inductor paraitic reitance ESR L become dominant reulting in an increae of the inductor lo. Similarly, the lo mechanim related to the power witche i characterized by the fact that at low frequencie, conduction loe are dominant due to the high inductor current ripple. A the operating frequency increae the witching loe become dominant, ince thee are directly proportional to the witching frequency. Figure 5b how the analytically calculated efficiency and imulated efficiency. A new optimum operating frequency i found to be f,opt,fine = 14 MHz reulting in the converter efficiency of 59.3%. The procedure ha been repeated on the converter with the magnetic core inductor reulting in the maximum efficiency of 7.3% at 1MHz. The lower operating frequency i due to the higher inductance value (19nH compared to 18.9nH of the air core inductor). Figure 6 how clearly that the converter that ue an inductor with magnetic core ha better efficiency than the converter with air-core inductor.). It can be concluded that the converter performance depend trongly on the quality of the magnetic component. The magnetic-core inductor ued ha a (b) Figure 5 Buck converter in CCM with air-core inductor fine optimiation a. Lo v. frequency b. Calculated and imulated efficiency Figure 6 Buck converter in CCM air core v. magnetic core efficiency comparion B. Buck converer in DCM A imilar procedure ha been performed for the converter operating in DCM. The optimum operating frequency that i obtained in the coare tage i f,opt = 95 MHz. In the fine 99

7 optimiation tage the voltage drop caued by the paraitic erie reitance of the inductor and witche are included. The expreion for the modified duty cycle D dcm (f) and the interval in which the inductor current decreae to zero Δ dcm (f) become a follow: (15) D ( f ) = dcm Iout f L Vout Vin Vout Iout ( Ron, P( f) + ESRL ( f )) Vin Vout Iout ( Ron, P( f) + ESRL ( f)) 1 + Vout Iout ( Ron, N ( f) + ESRL ( f)) Vout Iout ( Ron, N ( f) + ESRL ( f)) Vin Vout Iout ( Ron, P( f) + ESRL ( f)) Δ dcm( f) = Ddcm( f) V + I ( R ( f ) + ESR ( f )) out out on, N L (16) Figure 7 how the efficiency graph derived from the analytical model and imulation. A new optimum operating frequency i found to be f,opt,fine = 1 MHz reulting in the converter efficiency of 66%. uing an air-core inductor. A behavior imilar to the regular buck converter i noticed here. At low frequencie and high inductor current ripple, the inductor RMS current lo and conduction loe in the witche are dominating. At high frequencie the witching loe in the witche and eddy current loe in the inductor are the main lo contributor. The optimum operating frequency i found where the loe have the lowet value. The optimum frequency for the maximum efficiency in DCM mode i f,opt,fine = 16 MHz and the border frequency between CCM and DCM i f CCM,DCM = 7 MHz. Figure 9 SIDO converter with air-core inductor (a) component lo contribution and (b) efficiency v witching frequency Figure 7 Buck converter in DCM with air-core inductor fine optimiation a. Lo v. frequency b. Calculated and imulated efficiency C. Single-Inductor Dual-Output Converter For the ake of implicity, it i aumed that the two output of the SIDO converter require equal power level (1V@1mA). In practice, however, the load may require different power level. Figure 8 how the voltage and current waveform of the SIDO converter. Figure 8 SIDO converter time waveform Figure 9 how the total power lo and efficiency of the SIDO converter a a function of witching frequency when D. Comparion Table how the main deign parameter of the two topologie, the ynchronou buck and the Single-Input Dual-Output (SIDO) converter. For the buck converter, the deign parameter for the converter operating in CCM and DCM with the air-core inductor and CCM with the magnetic-core inductor are preented. It can be een that the option with the magnetic core achieve the highet efficiency. The main reaon for thi i lower witching loe due to a lower operating frequency (1 MHz v. 14 MHz). The inductor loe are alo omewhat lower in the cae of the magnetic-core inductor due to the lower ESR L for the imilar current ripple value (the product of the inductance value and operating frequency for both cae i imilar: 18.9 nh and 14 MHz for the air-core inductor and 19 nh and 1 MHz for the magnetic-core inductor). The footprint area of the magnetic core ued in thi cae i 5.7mm compared to 3.3mm of the air-core inductor. The deign value of the tranitor width of the converter with the magnetic core are everal time larger than in the cae of the air-core inductor converter (3.8mm PMOS and.mm NMOS). Looking at the deign parameter and reult for the dual-output topologie, namely the SIDO converter and two buck two output (TBTO) converter it can be een that the efficiency of the TBTO deign i higher than that of the SIDO converter. Thi i primarily a conequence of the higher witching loe due to the higher operating frequency of the SIDO converter (16 MHz v 1 MHz). However, the SIDO 3

8 converter ha only one inductor compared to the TBTO olution with two inductor which ubtantially increae the footprint of the complete converter. It can be een that in both cae there i a clear trade-off Iout= 1mA Vout = 1V Vin = 3.6V Buck CCM Air-Core Inductor TABLE DESIGN PARAMETERS AND COMPARISON Single-Input Single-Output Converter Buck DCM Air-Core Inductor between efficiency and ize o when chooing the optimum topology and deign parameter the boundary condition of the particular application have to be taken into account. Single-Input Dual-Output Converter Buck Magnetic SIDO TBTO Core Inductor in (DCM, Air-core (DCM, Air-core inductor) CCM inductor) L [nh] (x) ESR L [ ] (x) R ON_PMOS [ ] f,opt [MHz] R ON_NMOS [ ] [%] VII. CONCLUSIONS In thi paper a ytematic deign procedure for highly SiP integrated DC-DC converter for portable application i preented. The procedure i implemented in two tep, a coare and fine tage, for a time-efficient deign. The optimiation criterion i converion efficiency ince thi i crucial for a long battery life. The deign procedure i demontrated on the choen cae tudy, for a ingle and two-output converter. In both cae, a clear trade-off between efficiency and ize i oberved. The converter footprint i another crucial apect in portable electronic due to the ever-increaing trend for miniaturization. If one take into account the importance of cot in thee application, it i clear that the preented approach hould be extended to a multi-criteria deign-optimization procedure in order to get to the mot optimum olution for the particular application. REFERENCES [1] Mathuna, S.C.O.; O'Donnell, T.; Ningning Wang; Rinne, K. Magnetic on ilicon: an enabling technology for power upply on chip,ieee Tranaction on Power Electronic, Volume, Iue 3, May 5 Page(): [] H.J. Bergveld, R. Karadi, K. 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