Novel quadrature voltage controlled oscillator using series transistors coupling

Transcription

1 Indian Journal of Pure & pplied Physics Vol. 54, eceber 016, pp Noel quadrature oltage controlled oscillator using series transistors coupling Jie Jin a,b * a School of Inforation and Electrical Engineering, Hunan Uniersity of Science and Technology, Xiangtan ity Taoyuan Road , hina b ollege of Inforation Science and Engineering, Jishou Uniersity, Jishou ity People's Road 10, hina Receied 6 January 016; reised 16 ugust 016; accepted Noeber 016 In this paper, a noel quadrature oltage controlled oscillator (QVO) coupled by four transistors has been presented. The proposed QVO consists of two identical L negatie resistance oltage controlled oscillators (VO) and four series coupling transistors. opared with the coupling ethod using paralleled transistors, the series transistors coupling ethod has lower power consuption and phase noise. The proposed QVO is designed and siulated with Global Foundries 0.18 µ MOS 1P6M RF process using adence I esign Tools. The siulation results deonstrate that the proposed QVO operates fro.388 GHz to GHz by adjusting the control oltage, and its phase noise is dc/hz at 1 MHz offset. Moreoer, the power consuption of the QVO is only 1.84 W with 1.5 V supply oltage. Keywords: MOS, Radio frequency (RF), Negatie resistance, Phase noise, Quadrature oltage controlled oscillator 1 Introduction With the rapidly deelopent of wireless counication technology and icroelectronics process, greater deand of low power and highly integrated radio frequency integrated circuits (RFI) becoes ore and ore urgent. s one of the ost iportant building block of the wireless transceiers, the VO proides local oscillation signal for the ixer to realize the spectru shifting of the useful signals. The super-heterodyne transceier and direct conersion transceier are the two ost iportant architectures in odern wireless transceier systes. Howeer, the structure of the super-heterodyne transceier is ery coplex, and it suffers fro serious iage frequency interference. Moreoer, the superheterodyne transceier requires expensie and large chip area filters, which increases its cost. The direct conersion transceiers 1 becoe ore and ore popular because of their siplicity, low power consuption and unnecessary of expensie and large chip area filters. Figure 1 is the block diagra of a direct conersion transceier. s it is shown in Fig. 1, its structure is ery siple, and the QVOs are critical building blocks of the direct conersion transceier. There are four ain ethods to generate quadrature sinusoidal signals: using a polyphase filter conerts the differential signal into *E-ail: jj6713@sina.co four quadrature signals using a phase-locked loop (PLL) and a frequency diider to generate quadrature signals 3-7 the current-ode approach using actie integrator 8-13 using two identical VOs coupled by transistors or transforers to generate quadrature signals 14. Howeer, the polyphase filter ethod will attenuate the signals, and the aplitudes of the output quadrature signals are relatiely sall. The PLL and frequency diider ethod requires a large nuber of flip-flops, coplex structure and higher power consuption is ineitable. The current-ode quadrature oscillators are ery popular in low frequency applications, and they are ery easy to be ipleented. Howeer, the applications of current-ode quadrature oscillators are liited by their lower oscillation frequencies. The QVOs based on the coupling ethod using transforers or transistors hae the adantages of lower phase noise, lower power consuption and accurate quadrature outputs, and they are widely used in direct conersion transceiers. noel QVO coupled by four transistors is deonstrated in this paper. The proposed QVO is based on two identical negatie resistance L oscillators, and they are coupled with four P&N transistors. The cadence I design tools siulation results show that the oscillation frequency of the QVO can be tuned fro.388 GHz to GHz by adjusting the control oltage, and its power consuption is only 1.84 W. The proposed QVO has the

2 766 ININ J PURE & PPL PHYS, VOL 54, EEMER 016 characteristics of low power and siple structure, and it is suitable for wireless counication applications. ircuit nalyses.1 Negatie resistance L oscillator n L oscillator could be considered as an interconnection of a passie L tank and an actie negatie resistance. Figure (a) is an analogy of L tank VO 15. The paralleled passie L tank is a frequency selectie network, and the actie negatie resistance is used for energy copensation of the paralleled passie L tank. ssuing that there is a pulse current i(t)i pulse δ(t) applied to the passie L tank, and the response in tie doain of the tank could be expressed as: Fig. 1 lock diagra of direct conersion transceier t R I pulsee 1 1 ( t) t (1) L 4R out Fro Eq. (1), it is clear that the output of the passie L tank is a sinusoidal signal, and the aplitude decay of the sinusoidal signal is inersely proportional to the capacitor of the tank. When R >> (L/), and the frequency of the output sinusoidal signal could be expressed as: 1 1 f osc () π L Then, to keep the output sinusoidal signal in a steady state with constant aplitude, the energy loss is copensated by the actie negatie resistance.. L oscillator The scheatic of the L oscillator is presented in Fig. (b). The presented L oscillator consists of two transistors (one NMOS transistors and one PMOS transistors) and a L frequency selectie tank. Figure 3 is the equialent circuit of the L oscillator. Looking into the terinals and, we Fig. (a) nalogy of L VO (b) L oscillator Fig. 3 equialent circuit of the L oscillator ay notice that the transistors M 1 and M consist of a single-port network, respectiely. ssuing that the characteristics of the two transistors are identical, this eans: g (3) 1

3 JIN: NOVEL QURTURE VOLTGE ONTROLLE OSILLTOR 767 Fro Figs (b) and 3, we can know that: gs 1 ds (4) gs ds 1 When the oscillator operates at steady state, the oltage aplitudes at the terinals and are syetrical and equal, then: (5) ds1 ds The equialent conductance between the terinals and could be expressed as: G M g 1 gs1 ds1 g (6) Fig. 4 The siplified equialent circuit of the L oscillator Siilarly, the equialent conductance between the terinals and is: G M g ds gs g (7) The input resistance between the terinals and could be expressed as: R 1 1 (8) g in( ) + g g ased on the aboe analysis, the siplified equialent circuit of the L oscillator is presented in Fig. 4. The equialent circuit in Fig. 4 is a classic L negatie resistance oscillator, and the whole negatie resistance of the oscillator is about -/g. When the negatie resistance R in() equals to the parasitic resistance of the L parallel resonant tank, the negatie resistance proides the energy loss of the L parallel resonant tank, and the oscillator aintains steady oscillation..3 Proposed transistors coupled QVO The scheatic of the proposed QVO is presented in Fig. 5. The proposed QVO consists of two negatie resistance L oscillators, and they are coupled with each other by using four transistors (M a, M b, M c and M d ). ssuing that the characteristics of M 1 M 4 and M a M d are identical, which eans the transconductance of the transistors satisfy Eq. (9): g g a b c d (9) Fro Fig. 5, the drain currents of the transistors M 1 M 4 and M a M d could be expressed as: i i i i ds ds 4 ds1 ds3 i i i i dsb dsd dsa dsc b d a c (10) The oltages of nodes,, and satisfy Eq. (11): + i ds + i (11) ds4 Fig. 5 The proposed QVO where (jω) is reactance of the L tank. Moreoer, fro the analysis of negatie L oscillator, the

4 768 ININ J PURE & PPL PHYS, VOL 54, EEMER 016 signals at nodes, and, are inerted, respectiely. The oltages at nodes, and, satisfy Eq. (1): (1) Setting Eq. (1) into Eq. (11), Eq. (13) is obtained as: i i ds ds 4 (13) fter extracting the parasitics and connecting the parasitics to the scheatic, the post-layout siulation results of the QVO are presented in Figs 7-1. Figures 7-10 are the post-layout transient response of the QVO. Figure 8 is the transient response of the QVO during its initial state. Fro Fig. 7, it is clear that the starting tie of the QVO is about 10 ns. obining Eqs (10), (1) and (13), Eq. (14) is obtained as: + + ± j ± j 0 0 (14) Fig. 7 The transient response of the QVO Fro Eqs (1) and (14), it is clear that four quadrature signals are generated. 3 Post-Layout Siulation Results The proposed QVO is designed and erified by using adence I esign Tools Spectre siulator with GlobalFoundries 0.18 µ 1P6M MOS RF process. The physical chip layout is presented in Fig. 6, and the Mentor alibre software is used for its R, LVS and PEX layout erifications. In order to satisfy the etal density requireents of the chip, soe duy etals hae been added. The actie chip area including the bond pads of the QVO is approxiately Fig. 8 The siulated V o1 and V o3 at steady state Fig. 6 The physical chip layout of the QVO ( ) Fig. 9 The siulated V o and V o4 at steady state

5 JIN: NOVEL QURTURE VOLTGE ONTROLLE OSILLTOR 769 Figures 8 and 9 are the siulated V o1, V o3 and V o, V o4 at steady state, respectiely. Figure10 is the siulated V o1, V o, V o3 and V o4 fro 5 ns to 7 ns. Figure 11 is the haronic balance siulation result of V o1. s is shown in Fig. 11, the oscillation frequency of the QVO is about.758 GHz. The output power of the.758 GHz signal is about.96 d, and the other Fig. 10 The siulated V o1 - V o4 at steady state output interference haronic signals are relatiely sall. Moreoer, fro the arks M 0 and M 1 in Fig. 8, it is easy to calculate the phase difference of V o1 and V o3 is (0.08/0.36) π 89.5 ; fro the arks M 0 and M 1 in Fig. 9, it is also easy to calculate the phase difference of V o and V o4 is also (0.08/0.36) π Fro the aboe analysis, the QVO proides four quadrature signals, and the phase errors are about 0.55%. Figure 1 is post-layout siulation result of the phase noise of the QVO. s is shown in Fig. 1, the phase noise of the QVO is about is dc/hz at 1 MHz offset. Figure 13 is the post-layout siulation result of the frequency tuning range of the proposed QVO, the output frequency of the QVO ersus the control oltage is described in Fig. 13. Fro the arkers M 0 and M 1 in Fig. 13, it is clear that when the control oltage (V ctrl ) aries fro 0 V to 1.3 V, the output frequency of the QVO could be tuned fro.388 GHz to GHz, its frequency tuning range is about GHz. Moreoer, the frequency of the QVO could be approxiately linearly adjusted by the control oltage. Table 1 suarizes the recently reported QVOs along with this work. It is obsered that the proposed L QVO has the adantages of lower power consuption, better phase noise perforance and saller chip area. Fig. 11 The haronic balance siulation result of V o1 Fig. 13 The frequency tuning range of the QVO Fig. 1 The phase noise of the QVO Table 1 Perforance coparison with recently reported QVOS References [16] [17] [18] [19] Present Technology (µ) Supply oltage (V) Power consuption (W) Phase noise (d) Tuning range (GHz) hip area ( )

6 770 ININ J PURE & PPL PHYS, VOL 54, EEMER onclusions noel quadrature QVO coupled by four P&N transistors is presented in this paper, and the GlobalFoundries 0.18 µ 1P6M MOS RF process is used to design and erify the proposed QVO. The Mentor alibre software is used for the R, LVS and PEX layout erifications of the QVO. fter extracting the parasitics and connecting the parasitics to the scheatic, the adence post-layout siulation results deonstrate that the power consuption is only 1.84 W fro a 1.5V supply oltage, and the linear frequency tuning range of the QVO is about GHz. cknowledgent The authors would also like to thank Mrs Shanshan Xu in collage of foreign language of Jishou Uniersity for the English iproeents of this paper. This work is supported by the National Natural Science Foundation of hina (no ) the Education epartent of Hunan Proince outstanding youth project (no. 161), and the octoral Scientific Research Foundation of Jishou Uniersity under Grant jsdxxcfxbskyx07. References 1 atean & Haines M, IEEE 39 th Vehicular Technology onf, llen P E & ouglas R, MOS analog circuit design. (Oxford Uniersity Press: London), Tired T, Sjoland H, Sandrup P, Wernehag J, in I U & Toranen M, 8 GHz SiGe QVO and diider for an GHz E-band bea steering transitter PLL, NORHIP, Maligeorgos J P & Long J R, IEEE J Solid-State ircuits, 35 (000) S nn, Park J, Yu J & Ki N, High perforance injectionlocked frequency diider with 50 GHz L cross-coupled oscillator in 0.18 µ MOS process. IEEE 19th workshop on signal and power integrity (SPI), Siriburanon T, Ueno T, Kiura K, Kondo S, eng W, Okada K & Matsuzawa, 60-GHz sub-sapling frequency synthesizer using sub-haronic injectionlocked quadrature oscillators. 014 IEEE radio frequency integrated circuits syposiu, (Tapa ay, Florida, US), Mazzanti, Uggetti P, Rossi P & Selto F, Injection locking L diiders for low power quadrature generation, Proc IEEE custo integrated circuit conference, pp , Tangsrirat W, Mongkolwai P & Pukkalanun T, Indian J Pure ppl Phys, 50 (01) Jin J, oput Elect Eng, 40 (014) Sakul, Jaikla W & ejhan K, Radioengineering, 0(4) (011) Jantakun & Jaikla W, Indian J Pure ppl Phys, 53(8) (015) Jaikla W & Lahiri, Int J Electron oun (EÜ), 66 (01) Suart S, Thongsopa & Jaikla W, Indian J Pure ppl Phys, 5 (014) Yu F, Wireless Pers oun, 78 (014) asar M R, Malek F & Juni K M, Saleh M I M & Idris M S, IEEE International conference on electronics design, systes and applications, IES, Yu F, Tang Q, Wang W & Wu H, Wireless Pers oun, 86 (016) Wan Q, Liu Y & Wang Q, ircuits Syst Signal Process, 34 (015) Wang, Peng G, Ma M & Li, Radioengineering, 0 (011) Liu P, Sah S P, Yu X, Jung J, Upadhyaya P, Nguyen T N & Heo, IEEE Trans Microwae Theory Tech, 61 (013) 3658.