Performance of 3-Phase Neutral Point Clamped Active Front End Multilevel Converter

Transcription

1 Perforance of 3-Phase Neutral Point Claped Actie Front End Multileel Conerter Ait Ojha, P. K. Chaturedi, Arind Mittal 3,. Jain 4,4 Departent of Electrical Engineering, MANIT, Bhopal, Departent of Electrical Engineering, ATI,Vidisha, 3 Departent of Energy, MANIT, Bhopal Corresponding Eail: ojha.ait@gail.co ABTRACT For ediu oltage, high power applications 3-phase neutral point claped AC-DC ultileel conerters are becoing a good choice. In this paper the perforance of a 3-phase neutral point claped Actie Front End three leel conerter for high power application with siplified control schee is presented. A coplete atheatical odel of the control schee is deeloped and perforance is inestigated for balanced load in ters of oltage unbalance across dc link, oltage stress across the switches and THD in the line current. Keywords: Auxiliary circuit, Actie Front End Conerter, DC link capacitors, ultileel conerters.. Introduction AC-DC conerters are extensiely used in power supplies, dc otor dries, front end conerters in adjustable-speed dries, high oltage DC transission, switch-ode power supplies, utility interface with non-conentional energy sources etc. Earlier the conersions fro AC to DC were carried out by diode or phase controlled rectifier which act as non linear load on the power utility. uch non linear load draws current which is rich in haronics with poor supply power factor, thus creating serious issue of power quality. Due to these issues regulatory agencies hae issued seeral strict standards such as IEEE 59, IEC555 etc. to ipose liits on perissible haronic contents and reactie power drawn fro supply[-]. To eet such strict standards, classically shunt passie filters consisting of tuned LC coponents and/or high pass filters are used to suppress the haronics as well as power capacitors are eployed to iproe the power factor of the utility/ains. But these conentional ethods hae the liitations of fixed copensation, large size, and cost, and can excite resonance conditions. Actie power filters hae also been researched extensiely to address such issues [3]. But they hae the drawbacks of large rating, size, cost and coplexity in control. To oercoe these drawbacks and for iproed power quality, high power factor conerters (HPFC) becae the inherent part of AC-DC conersion. Iportant features of HPFCs are conersion at unity power factor with higher efficiency, reduced size and well regulated dc output [4-6]. But these high power factor conerters using high oltage rating deices are haing liitations such as large d/dt, large oltage stress across switching deice, large coon ode oltage, high switching frequency etc. [7-]. Due to continuous research in the field of deeloping efficient static power conersion, a new age of conerters i.e. ultileel conerters hae now reached to certain leel of aturity [-3]. Multileel structure is gaining lot of popularity because of its excellent perforance in ters of sinusoidal input current with negligible haronic contents, unity power factor, less ripple in regulated dc output oltage, reduced oltage stress across switch, reduced d/dt and low electroagnetic interference with neighboring counication lines as copared to its counterpart -leel HPFCs [4]. Diode-claped ultileel conerter is the ost widely used topology in ultileel power conersion [7-9]. Though, it has so any adantages oer its counterpart conentional -leel conerters, it suffers fro serious proble of unbalance oltage of dc link capacitors under unbalanced loading conditions [5]. The oltage equalization of dc link capacitors is the necessary precondition for stable operation of a diode claped ultileel conerters [6]. The basic concept of dc link oltage balancing is to redistribute the charge through each capacitor. One way to control dc link is odifying the control technique inoled. Many carrier based control techniques such as inusoidal Pulse Width Modulation (PWM) and pace Vector Pulse Width Modulation (VPWM) [7-9] hae been proposed to itigate these probles. VPWM control technique requires ery coplicated control algorith at higher leel which is difficult to ipleent without sophisticated and costly control platfor []. These ethods try to switch aong the states haing zero neutral point potential i.e. copletely balanced dc link. Another way to deal with the issue of capacitor oltage unbalance proble is the use of additional hardware circuitry such as oltage regulators, separate dc sources or additional balancing circuit [6, ]. The proble with the auxiliary circuits used for balancing purpose is the extra cost, as well as higher switching losses. A closed loop control ethod which eploys addition of off-set oltage signal to the reference oltage signal is gien in [3]. This not only balanced the dc link but also reduced the switching losses by inserting no switching zone in each half cycle of the phase oltage. A detailed switching losses inestigation was carried out in [4]. Hence this proble can be dealt IJET@3 Page 9

2 effectiely for better perforance of ultileel conerters for high power applications. In this paper, a siplified control schee is analyzed for 3- leel rectifier under balanced and unbalanced loading condition. The aderse effects of unbalanced load for the stable operation of rectifier are highlighted with respect to oltage stress across the switches and other power quality issues. The presented concept of balancing dc link capacitor oltage is based on faous ping-pong theory [6]. The atheatical odeling of auxiliary circuit based on pingpong theory and its working principle is presented in this paper. The paper is organized as follows: ection II gies description of neutral point claped ultileel AC-DC conerter under balanced load and unbalanced with siplified control schee for iproed power quality in ters of input power factor, input current THD and neutral point potential ariation. ection III deals with the perforance analysis of neutral point claped ultileel AC-DC conerter under unbalanced load with auxiliary circuit for oltage balancing of dc link capacitors is presented by conclusion in section IV.. THREE PHAE THREE LEVEL NEUTRAL POINT CLAMPED AC/DC CONVERTER. Power and Control Circuit A three-phase, three-leel neutral-point claped actie front end rectifier is shown in Fig.. There are four power switches ( a, a, a and a for phase A ) in one leg for each phase and each leg is claped with claping diodes (D & D for phase A ). Actie front end rectifier is fed by 3-phase AC source connected through boost inductor (L s ). C and C are the dc link capacitors and idpoint of dc link capacitors and claping diodes of each leg is connected to the neutral of three phase AC source. The load resistance R and R are connected across the dc link capacitors. a b c i i D D D 3 V c R V V sa R L s a b c C N V sb V sc R R i sa L s i sb L s a a b b c c i n i V i sc V c R V a D b D c D 3 C i Fig. Three-Phase Neutral-Point Claped Actie Front End Three-Leel Rectifier Fig. shows control schee used to aintain the dc bus oltage at desired leel and for iproed power quality at supply side. The control schee used consists of a oltage controller and current controller. The carrier based unipolar PWM waefors of line-to-neutral oltages, and are produced at input side of the conerter[4]. The phase locked loop (PLL) circuit is used to generate three unit sinusoidal oltages synchronized with the AC source oltages. Reference supply currents (Isa, Isb, Isc) are calculated by ultiplying the aplitude of the input current coands (I ) and the generated unit sinusoidal oltages. controller is used to iniize the error between two dc link oltages and to generate input current coand, I. These reference current coands are copared with actual load currents. Error generated is processed through another controller. Control or reference oltages are generated by coparing the output of controller and output of PLL. The PWM odulator is used to obtain the switching signals for the power switches by coparing these reference/control oltage signals with triangular carrier waes. IJET@3 Page

3 Current controller i sa i sb i sc a a b b c c Δ I i sa cona i sb conb Voltage controller i sc conc sx (x = a,b,c) PLL sau(t) sbu(t) scu(t) PWM Modulator Fig. cheatic diagra of 3-phase, 3-leel neutral point claped ultileel rectifier control schee. A proportional integral oltage controller is used to balance AC side power and DC side power of the rectifier, to obtain the aplitude of the line current coand i.e. I. The current coand can be gien as: I k p ki () where = - is the DC bus oltage error, is the reference DC link oltage coand and is the easured DC link oltage. The unit sinusoidal oltages generated through PLL can be written as: sau sbu scu ( t) sin t sin( ( t) t ) 3 sin( ( t) t ) 3 The line current coands are deried fro the ultiplication of the output of the oltage controller and the unit sinusoidal oltages as: () i ( t) I a i ( t) I b i ( t) I c sin( t) sin t 3 sin t 3 The easured line currents are copared with the respectie reference line currents and the current errors thus generated are fed to the current controller to track the source current coands. Neglecting the highfrequency switching ters, we can write source oltage of phase A as, di (3) sa sa Lsa cona (4) where is the odulated control/reference oltage signal of PWM odulator deried fro the proposed closed loop control of the syste. The carrier-based sinusoidal PWM schee is eployed for generating proper switching signals as shown in Fig. 3. dt Tie (sec) (a) IJET@3 Page

4 a4 a3 a a Tie (sec) (b) Fig.3 (a) Carrier-based PWM schee for the generation of gating pulses (b) Control pulses According to control schee and gating signals as obtained aboe the switching signals of the power switches can be defined as, if Tc if if cona t t t cona cona t Hence, switching functions can be written as a a a a Tc ( Tc ) a Tc ( Tc ) a Therefore for phase A, in the positie half of the control signal cona, the switch a is turned on and the line current is controlled by turning on or off the switch a. In the negatie half of cona,, a is turned off and turning on or off a can control the line current to follow the current coand. For equal capacitor oltages ( c = c = /), three oltage leels ( /,, and - /) are generated on the AC side of the rectifier phase oltage an. 3. Results and Discussion (6) (5) enironent. Table shows the siulation paraeters for 6.6 kv syste. TABLE iulation Paraeters Phase Voltage V sa 38 V (RM) AC Link Inductance L ac 3 H AC Link Resistance R ac.8 Ω DC Link Voltage V dc V DC Link Capacitance Load Resistance (balanced load) C and C µf each 3 Ω R R 3 Ω Carrier Frequency f c khz Fig.4 shows the phase oltage (V sa ) and line current (i sa ) at source terinals and it can be clearly seen that the conerter is working at unity power factor for balanced load. Fig. 5 shows the haronic spectru of line current of phase A which shows that haronic content in the line current is well below the 5% liit. The oltage across the switch a is shown in Fig. 6 which is only half of the total dc link oltage. The siulated waefors for AC side line-to-line oltage (V ab ) and line-to-neutral oltage (V an ) of the conerter are shown in Fig. 7 (a) and 7 (b). A siulation odel of three-phase, neutral-point claped, AC-DC, 3-leel conerter under balanced load is deeloped using ipowerystes in MATLAB/iulink IJET@3 Page

5 Vc (olt) Vswitch (olt) % of Haronic Van (olt) (Vsa/5) & isa (olt/ap) Vab (olt) Vsa x 4 5 isa Tie (sec) Fig. 4 ource phase oltage (V sa ) and line current (i sa ) under balanced load THD=.4% Haronic order Fig. 5 Haronic spectru of line current (i sa) under balanced load Tie (sec) Fig. 6 Voltage across switch a under balanced load Tie (sec) Tie (sec) (b) Fig. 7 (a) AC side line-to-line oltage (V ab) (b) Line-to-neutral oltage (V an) under balanced load Under balanced loading condition, the oltages across the capacitors (C & C) are shown in Fig. 8(a) & Fig. 8(b). Fro these figures, it can be obsered that the oltages across the capacitors are alost balanced (a) 3 4 Tie (sec) IJET@3 Page 3

6 Vc (olt) Tie (sec) (b) Fig. 8 (a) Voltage across dc link capacitor C (b) Voltage across dc link capacitor C, under balanced load (a) 4. Conclusion The perforance of a three-phase neutral-point claped rectifier is ealuated for iproed power quality and balancing of oltage across dc link capacitors, with siple control. iulation results are presented to study the perforance of the syste under balanced load. The results shows that the proposed three-phase neutral-point claped rectifier works at unity power factor and the THD of supply current is also well within the liits iposed by IEEE 59 standard under balanced load. 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