Single-phase Solid-State Transformer using Multi-cell with Automatic Capacitor Voltage Balance Capability

Transcription

1 Single-phase Solid-State Transforer using Multi-cell with Autoatic Capacitor Voltage Balance Capability Jun-ichi Itoh, Kazuki Aoyagi, Keisuke Kusaka and Masakazu Adachi Departent of Electrical, Electronics and Inforation Engineering Nagaoka University of Technology Nagaoka, Niigata, Japan Abstract- In this paper, a single-phase solid-state transforer (SST) syste based on a ultilevel topology using ulti-cell is proposed. The proposed SST has an autoatic capacitor voltage balancing capability on a priary side due to use of a resonant DC-DC converter. The ain contribution of this paper is revealing the fundaental loss design of the proposed topology connected with a 6.6-kV grid. It is predicted that the axiu efficiency of full odel SST reaches 99%. The iniature odel SST is tested to confir the fundaental operation with an input voltage of 3 V, which is /5 of the full odel. As a result, the sinusoidal input current is obtained with a total haronic distortion of 4.3%. Besides, the bidirectional operation is verified. Then, it is confired that the priary side capacitor voltage of each cell is kept constant and balanced without a voltage balance control. Moreover, the loss analysis is derived in each part and copared with that of the experiental result. The error of the loss between the experiental result and the calculation is less than 5%. Keywords Solid-State Transforer; ower factor correction converter; Resonant DC-DC converter; Highfrequency transforer; I. INTRODUCTION Recently, a DC distribution syste has been actively researched in order to achieve the energy-saving of the data-center or the large building [] []. The DC distribution syste is possible to achieve down-sizing and high efficiency copared with an AC distribution syste [3]. Moreover, a 6.6-kV AC power grid is eployed as one of the power sources. In general, a transforer is applied between the AC power grid and the DC distribution syste in order to achieve the step-down fro 6.6 kv to the distribution voltage of several hundred volts and obtain galvanic isolation between the AC power grid and the DC distribution syste [4] [5]. However, the conventional transforers are bulky and heavy because the transforers operate at a grid frequency, e.g., 5 Hz or 6 Hz. As one of the solutions, a transforer-less converter is proposed [6]. In the five-level diode-claped converter, the high voltage IGBTs with the voltage rating ore than 4.5 kv are required. In addition, the balancing circuit is required as the auxiliary circuit in order to correct the unbalanced voltage aong four capacitors in the DC link. Besides, it is operated by low switching frequency because the loss of high voltage rating devices is large copared to low voltage rating devices. Consequently, large passive coponents are required due to low switching frequency in order to suppress haronic distortion of input current and voltage ripple of output DC voltage. As another solution, solid-state transforers (SST) have been attracting attention [7] [9]. SST is possible to significantly reduce the syste volue copared to the conventional transforer by introducing high-frequency switching with the spread use of silicon carbide (SiC) and galliu nitride (GaN) devices []. SST siultaneously achieves the insulation and the step-down function by using a high-frequency transforer. To su up, SST has following advantages []: Reduced size and weight of the syste Haronic suppression Active/ Reactive power control AC voltage adjustent DC voltage output Besides, it is possible to copose the cell converters based on ultilevel topologies, which enable to reduce a required voltage rating of the switching devices. The cell converters allow using switching devices with low on-state resistance and high-speed switching. In addition, the switching frequency is equivalently increased. Thus, the inductor volue can also be reduced []. Consequently, SST achieves high voltage rating with high switching frequency by ultilevel topologies. However, the nuber of the switches still increases greatly due to the ultistage cell. Moreover, the control syste, which drives the ain circuit, is coplicated because the nuber of the gate signal is increased with increased nuber of the switch [3]. Moreover, a balance control for each capacitor on the cells is required in the ultilevel syste, e.g., odular ultilevel converter (MMC) [4]. The balance control ay cause an unstable if a feedback control has a delay due to isolation or signal transission [5]. Furtherore, the DC link capacitor with a large capacitance is required in order to aintain the constant capacitor voltage in each cell [6].

2 riary side rec. Snubber circuit FC converter Cell No. Resonant DC-DC converter Secondary side rec. C out S S 3 L b S pfc S llc S 5 C L s N : N V dc S 7 V out v in S pfc S llc S 6 C s S 8 V eq S S 4 C snb R snb Cell No. Cell No. 3 Fig.. Circuit configuration of proposed bidirectional single-phase SST. In this paper, a siple circuit configuration of the single-phase SST is proposed. The proposed SST, which achieves capacitor voltage balance aong cells without a coplex voltage balance control with sall priary side capacitor. Additionally, the proposed circuit reduces the nuber of the switching devices copared to the conventional circuit. The originalities of in this paper are proposing a new SST topology and the autoatic voltage balancing ethod using a resonant DC-DC converter, which is connected in parallel in the secondary side. The contributions of this paper are that the volue of syste is reduced and the control is siple. The proposed SST syste is experientally tested under a derating voltage of 3 V which is /5 of the full odel. In addition, the bidirectional operation is verified with the input voltage of V to validate a loss distribution. Then, the proposed SST is designed for a 6.6-kV grid as the input voltage. II. SYSTEM CONFIGURATION OF ROOSED SST A. Circuit configuration Figure shows the circuit configuration of the proposed SST. At the priary side, the output of the full bridge rectifier is connected to all cells in series. The devices with high voltage rating are required on the priary side. However, it is possible to use the devices with the slower switching speed because these switches are operated at the grid frequency. This syste is characterized by a ulticell input stage based on the full bridge rectifier. Each cell consists of a boost-type power-factor-correction (FC) converter and a resonant DC-DC converter. FC converter controls the input current to sinusoidal wavefor with the unity power factor. Moreover, the rectified voltage is equally divided aong each FC converter because each cell at the priary side is connected in series. Thus, the voltage per cell is reduced. Consequently, at the priary side, it is possible to apply the switching device with low voltage rating and low on-state resistance. In the resonant DC-DC converter, the volue of the transforer is reduced because the transforer operates at high frequency. In addition, a large capacitor is used in the output of a general FC converter. In this syste, sall capacitors is Rated Voltage 3.3 kv.7 kv. kv used because the proposed circuit decouples a power pulsation at twice the grid frequency in the secondary side. Table I shows the coparison of the switch nuber between the proposed SST and the conventional SST which includes a WM rectifier and a dual active bridge converter [7]. Note that the nuber of cell is calculated by the rated voltage of the switch. As shown in table, the nuber of devices is reduced by 3% copared to conventional SST. The reason is because the proposed SST uses only one rectifier for each cell. Consequently, the proposed circuit increases the utilization rate of circuit copared the MMC. B. Control syste Figure shows the control block diagra of the proposed circuit. The proposed control includes an autoatic current control (ACR) for the boost inductor current. In the ACR, the boost inductor current is controlled into full wave rectified wavefor in order to correct the power factor of the grid side. Hence, the inductor current coand value I L * is given by I I sin( t) * L TABLE I. COMARISON OF SWITCHING DEVICE BETWEEN CONVENTIONAL SST AND ROOSED SST. ap Nuber of cell 6 6 Nuber of Switching devices Conventional SST roposed SST (WM rec. + DAB) where I ap is the aplitude coand value of the boost inductor current. Inductor current coand I L * is generated by the ultiplication of I ap and the full-wave rectified wavefor with sae phase as the input voltage. In the triangular wave coparator, the gate signal for FC is generated by phase shifted carriers. Thus, the input voltage is equally divided because the switching tiing is different. In addition, it is possible to use the switching device with low voltage rating. Note that the ripple current is reduced because the inductor voltage is reduced by the

3 v in LL Sin Boost inductor current control (ACR) * + I L - ABS I L - V d + hase-shifted carrier V c V c NOT NOT S pfc S pfc S pfc S pfc Fig. 3. Control block of FC converter in proposed circuit. series connection in the FC converter. Then, the phase shift angle θ is given by (). v in k ( k,,, ) Meanwhile, the balance control of the priary side capacitor voltage V dc is not required in this syste. The voltage of the priary side capacitor ay be ibalanced due to the variation of capacitances or a difference of transient response in general ultilevel topology. However, due to the parallel connection of the resonant DC-DC converters, which is operated with constant duties, at the secondary side, the output voltage of each cell is autoatically adjusted. Consequently, the priary side capacitor voltage is naturally cluped by the voltage which is decided by the turn ratio and the secondary voltage because the cell with low voltage is fed ore power fro the cell with high voltage. Thus, the voltage anageent on the high-voltage side is not required. Figure 3 shows the switching pulse generation of the priary side rectifier. The switching pulse is generated by coparing the input voltage v in and the thresholds voltage of positive/negative (V thp/v thn). The switching states are following: v in > V thp Turn on S and S 4 Turn off S and S 3 v in < V thn Turn on S and S 3 Turn off S and S 4 V thn < v in < V thp Turn off S, S, S 3, and S 4 In the power running operation, the current flows the body diode of MOSFET. In the case of regeneration operation, the current flows the snubber circuit. Table II shows the switching state of the priary side rectifier, the resonant DC-DC converter, and the secondary side rectifier. In the priary side rectifier, the switching frequency is set to the grid frequency in order to achieve the polarity inversion. In the resonant DC-DC converter, the switching frequency is set to the resonant frequency in order to achieve ZCS, and the switches are odulated with duty ratio of 5%. Hence, the closed-loop control for the resonant DC-DC converter is unnecessary. Consequently, the control is siple in this syste because the current V thp V thn S, S 4 S, S 3 Fig.. ulse generation for priary side rectifier. control is achieved by only the switches of FC (S pfc). In the secondary side rectifier uses the switching pulse synchronized with the resonant DC-DC converter. III. DESIGN OF ROOSED SST A. Snubber circuit In the proposed SST, a snubber circuit is used in order to achieve the bidirectional operation. At regeneration operation, the continuous current flow is secured because the boost inductor current flows into the snubber circuit during the dead-tie. Moreover, the snubber circuit also has to absorb all energy which is generated in the boost inductor when all gates are off with over current detection. Thus, the capacitor of the snubber circuit is given by C snb LI V b ax where I ax is current at over current detection, V is voltage rise value of capacitor. The resistor of the snubber circuit is given by R TABLE II. SWITCHING MODE OF RESONANT DC-DC CONVERTER AND RECTIFIER. Switching frequency snb Duty ratio L I V clap f b ax sw _ rec S ~ S 4 S llc ~ S llc S 5 ~ S 8 5 Hz 5 khz (= f o ) 5%

4 where f se_rec is the switching frequency of the priary side rectifier, and V clap is the clap voltage. The clap voltage is designed to have a argin with respect to the rated voltage of device. In the iniature odel SST, the argin is %. B. ower-factor-correction (FC) converter The boost converter corrects the power factor of the grid side because the boost inductor current is controlled into full-wave rectified wavefor sae as general FC circuit [8] [9]. The boost inductor L b in the FC circuit is given by Vin Lb 4 f I eq Lb where ΔI Lb is the ripple current of the inductor current, and f eq is the equivalent switching frequency of the output voltage V eq. Then, the equivalent switching frequency f eq is given by f f eq sw where is the nuber of cells, f sw is the switching frequency of the FC circuit. Each cell is operated by phase-shifted carrier. Consequently, the switching frequency coponent in V eq is increased in proportional to the nuber of cells. Thus, the size of the boost inductor is reduced because the inductance is inversely proportional to frequency. C. Resonant DC-DC converter The resonant DC-DC converter generates a highfrequency voltage for the isolated transforer []. The high-frequency operation leads to the iniization of the isolation transforer. In addition, the zero current switching (ZCS) is achieved by the series resonance between the inductor L s and the capacitor C s. ZCS greatly reduce the switching loss of the proposed SST syste. Furtherore, the leakage inductance is designed to be negligibly saller than the excitation inductance. Then, the switching frequency f o of the resonant DC-DC converter is given by (7). Fro resonance frequency, and the duty ratio of the switch is set to 5%. f o LC s s In the proposed SST, the operation ode is always the boost operation with respect of the priary side voltage. Thus, the turn ratio of the transforer is designed by N V in N N V out where N and N are the nuber of turns for priary/secondary side of the high-frequency transforer, TABLE III. CIRCUIT ARAMETER OF ROOSED SST FOR THE MINIATURE MODEL araeter Sybol Value Input voltage Rated output power v in out 3 V rs kw Rated output voltage V out 3 V Snubber capacitor C snb. µf Sunbber resistance R snb.5 MW Boost inductor L b 4 H (%Z =.87%) riary side capacitor Resonant capacitor Leakage inductor Secondary side capacitor C C s L s C out 48 µf 4 nf 5 µh 8 µf Switching frequency of rec. f sw_rec 5 Hz Switching frequency of FC Resonant frequency Nuber of cells Trans turns ratio V in is the input voltage, V out is the output voltage, and λ is the odulation index of the boost converter. IV. EXERIMENTAL RESULTS A. ower running operation f sw_pfc f o khz 5 khz 3 N /N. Table III shows the specifications and the circuit paraeters. In this experient, the fundaental operation is verified with the input voltage of 3 V which is /5 of the full odel. The prototype has three cells. Figure 4 shows the wavefors of the input voltage, the input current, and the output voltage. The operation of the iniature odel without the any large distortion is confired. At the input side, it is confired that the unity power factor between the input voltage and the input current is achieved. The input current THD is 4.3% at the rated load. At the output side, the step-down operation is achieved because the output voltage is regulated to 3 V. Figure 5 shows the priary side capacitor voltage of each cell when the output power is changed fro.8p.u. to.p.u. ( kw). It is observed that the priary side capacitor voltage is balanced even during transient response. Moreover, the axiu value of the priary side capacitor voltage also shows sae value for all cells. Thus, it is confired that the priary side capacitor voltage is balanced aong all cells without the balance control even when the output power suddenly changes. Figure 6 shows the output voltage of all cells. Fro Fig. 6(a), the input voltage is equally divided to each cell because the output voltage of all cells fors balanced ultilevel wavefor. In Fig. 6(b), it is also confired that the equivalent switching frequency f eq is 3 khz. The equivalent switching frequency is deterined by the switching frequency in FC and the nuber of the cells. Figure 7 shows the relationship between efficiency and input power factor. The axiu efficiency is 89.5% at the rated load. The reason is that the percentage of loss in devices against the power becoes low. The input power

5 Input voltage v in [ kv/div] riary side capacitor voltage V dc, V dc, V dc3 [ V/div] 5 s Input current i in [3 A/div] Output voltage V out [ V/div].8p.u.p.u (rated power) s Fig. 4. Operation wavefor at power running. Fig. 5. riary side capacitor voltage in each cell. Output su voltage of each cell V eq [5 V/div] Output su voltage of each cell V eq [5 V/div] 5 s µs (a) Whole figure Fig. 6(b) Fig. 6. Output voltage of all cells at power running. (b) Enlarged figure Efficiency [%]. cosf Efficiency p.u. = kw Output power [p.u.] Fig. 7. Characteristic of efficiency and power factor. Input power factor cosf Input current THD [%] Output power [p.u.] Fig. 8. Characteristic of input current THD p.u. = kw factor is over.95 with the output power fro.5p.u. to.p.u. Figure 8 shows the relationship of the input current THD and the output power of the SST. It is confired that the input current THD is large when the output power is low. The reason is that the rate of the low-order haronics coponent appears rearkably with respect to the fundaental coponent because the input current is low when the output power is low. B. Bidirectional operation In this experient, the iniature odel SST is tested to confir the fundaental operation with the input voltage of V due to the liitation of the experiental facilities. Note that the regeneration power supply is connected to the output side in order to achieve the regeneration operation. Figure 9 shows the bidirectional operation of SST when the switching fro power running to regeneration is tested. In the power running operation, it is confired that the unity power factor between the input voltage and the input current is achieved. On the other hand, it is confired that the input current is reversed against the input voltage in the regeneration operation. The input current THD of 4.% is also confired. In the output su voltage of each cell, it is confired that the wavefor is four-level staircase voltage. Furtherore, an equivalent switching frequency f eq of 3 khz is also confired. Thus, the stable operation of the iniature odel without the any large distortion is achieved even when the operation abruptly changes.

6 Figure shows the priary side capacitor voltage of each cell in the bidirectional operation. It is observed fro the wavefor that the priary side capacitor voltage is balanced aong all cells without the balance control even when the operation changes abruptly. V. LOSS ANALYSIS AND ESTIMATION FOR FULL MODEL Fro Fig., the loss of SST is separated following coponents: (i) riary side diode bridge (ii) Switching devices of FC converter (iii) Switching devices of the resonant DC-DC converter (iv) Secondary side rectifier Table IV shows the selected devices in each part. In the proposed SST, the rated voltage of 3.3 kv is used in the priary side rectifier. The current which flows into the electrolytic capacitor includes not only the power ripple coponent but also the switching frequency coponent fro the inverter. Thus, it is very difficult to derive analytically. Hence, the capacitor ripple current is derived by siulation []. The capacitor ripple current is the function of the output power factor angle φ and the odulation index, which is a nonlinear value. Then, the effective value of the capacitor ripple current is given by I _ K (, ) I rs cap cap out where I out is the average value of the output current, and K cap is the coefficient which is obtained by the siulation. Figure shows the siulation result of K cap. The odulation index, which expresses the ratio of the voltage per cell and the dc-link voltage, is.94 in the iniature odel SST. Therefore, fro Fig., K cap (.,.94) is.83. A. riary side diode bridge The loss of switches, which is calculated by the onvoltage of the switch and the current through the switch, is given by Input voltage v in [3 V/div] Input current i in [3 A/div] Output su voltage of each cell V eq [ V/div] Output voltage V out [5 V/div] ower running ode Input voltage v in [3 V/div] Input current i in [3 A/div] Output su voltage of each cell V eq [ V/div] Output voltage V out [5 V/div] s s Regeneration ode Input voltage v in [3 V/div] Input current i in [3 A/div] Output su voltage of each cell V eq [ V/div] Fig. 9. Bidirectional operation of proposed circuit. Output voltage V out [5 V/div] riary side capacitor voltage V dc, V dc, V dc3 [ V/div] ower running ode Regeneration ode s s v i dt con on sw where v on is the on-voltage of the switch, i sw is the current through the switch. In this case, v on and i sw are given by. Fig.. riary side capacitor voltage of each cell at bidirectional operation. is not considered because the power factor is. The loss of the switches in the priary side rectifier is given by (3). von ron sin( t) v V in con _ pri _ rec on r Vin i sw sin( t) V in B. FC converter The conduction loss of the switches in FC is given by where r on is the on-resistance of the switch, is the rated power of SST. In (), v is defined as zero because the MOSFETs are used in the prototype. Moreover, the phase difference between the input voltage and the input current r I con _ FC on L

7 where I L is the current effective value through the boost inductor. On the other hand, the switching loss of the switches, which is assued that it is directly proportional to the voltage and the current of the switch, is given by e e V on off dc sw _ FC fsw EnoI no Vcell where V dc is the voltage of the priary side capacitor, is the rated power, is the nuber of cell, f sw is the carrier frequency, e on and e off are the turn-on and the turn-off energy per switching fro datasheet, E no and I no are the voltage and the current under the easureent condition of the switching loss fro the datasheet, and V cell is the input voltage of each cell. C. Resonant DC-DC converter The loss of switches in the resonant DC-DC converter is only the conduction loss because ZCS assue achieving over all operation regions. Therefore, the conduction loss is given by N I out Irs _ cap con _ LLC Ron N At the secondary side, the conduction loss is given by out rs _ cap con _ sec_ rec Ron I I D. High-frequency transforer Iron loss, which occurs in the high-frequency transforer, is calculated by the agnetic flux density and the characteristic of the core. The AC agnetic flux density B ac is given by B ac Vout 4 f A N o e where A e is the effective cross-section of the core, and N is the turns ratio of the transforer. The core loss value is given by the characteristic graph between the core loss value vs. the agnetic flux density, which is obtained fro the core aterial, and the agnetic flux density which is calculated fro (9). Therefore, the iron loss is given by V iron _ loss cv e where V e is the effective volue of core. The high frequency transforer of full odel SST is designed by Gecko MAGNETICS which uses iprovediproved Generalized Steinetz Equation (i GSE) in order to calculate the iron loss of the transforer []. Consequently, it is possible to select the optiu core shape, core aterial and winding shape. Fro the analysis TABLE IV. SELECTED DEVICES OF ROTOTYE FOR BIDIRECTIONAL OERATION. Single-phase rectifier Current coefficient Kcap Circuit topology art Type FC converter Resonant DC-DC converter Secondary side rectifier of Gecko MAGNETICS, it is confired that the loss is iniu by using ECOS N95 as the core in the full odel SST. E. Loss distribution S ~ S 4 S pfc ~S pfc S llc ~ S llc S 5 ~ S 8 ower factor cosf Figure shows the loss distribution obtained fro the experient and the calculation of the bidirectional operation. Note that the loss is noralized with the experiental loss as %. The error of the loss between the experient and the calculation is less than 5%. Figure 3 shows the loss distribution of the full odel SST. The loss distribution is calculated with assuing 6.6- kv input voltage and a -kva rated power. Then, the nuber of cells is 5 because.-kv switching devices can be used. Fro this consideration, a 99% efficiency at the rated power is expected. Moreover, it is possible to reduce the loss by applying synchronous rectification in the secondary rectifier. VI. CONCLUSION This paper has proposed a iniature odel SST, which has a capacitor voltage balance capability without a control. The fundaental operation of SST was confired with the input voltage of 3 V which is /5 of the full odel fro the experiental results. As a result, the sinusoidal wavefor of the input current was obtained without any large distortion at the priary side. In addition, the bidirectional operation is confired in the proposed SST with the input voltage of V. Furtherore, the average voltage of the priary side capacitor are stable and balanced aong all cells without a voltage balance control. Finally, the loss equation was derived at each part of the syste and copared with experiental result. As a result, the error of the loss between the experiental result and - SCT8KE Maxiu ration 33 V V 4 A odulation index Fig.. Current coefficient of output capacitor.

8 the calculation is less than 5%. It is predicted that the axiu efficiency of full odel SST is 99%. % =.9 W % = 6.5 W REFERENCES [] T. Tanaka, Y. Takahashi, K. Natori, and Y. Sato High-Efficiency Floating Bidirectional ower Flow Controller for Next-Generation DC ower Network, IEEJ J. Industry Applications, vol. 7, no., pp. 9-34, (8) [] R. Chattopadhyay, S. Bhattacharya, N. C. Foureaux, A. M. Silva, B. Cardoso F., H. de aula, I. A. ires,. C. Cortizio, L. Moraes, and J. A. de S. Brito: Low-Voltage V ower Integration into Mediu Voltage Grid Using High-Voltage SiC Devices, IEC 4, pp.35-33, (4) [3] T. Nakanishi, K. Orikawa, J. Itoh: Modular Multilevel Converter for Wind ower Generation Syste Connected to Micro-Grid, ICRERA4, No. 9, (4) [4] L. Wang, D. Zhang, Y. Wang, B. Wu, and H. S. Athab: ower and Voltage Balance Control of Novel Three-hase Solid-State Transforer Using Multilevel Cascaded H-Bridge Inverters for Microgrid Application, IEEE Trans. On ower Electronics, Vol. 3, No. 4, pp , (6) [5] T. Nakanishi, and J. Itoh, Control Strategy for Modular Multilevel Converter based on Single-phase ower Factor Correction Converter, IEEJ J. Industry Applications, vol.6, no., pp.46-57, (7). [6] N. Hatti, Y. Kondo, and H. Akagi, Five-Level Diode-Claped WM Converters Connected Back-to-Back for Motor Drives, IEEE Trans. On Industry Applications, Vol.44, No.4, pp.68-76, (8) [7] M. Nakahara, and K. Wada, Loss Analysis of Magnetic Coponents for a Solid-State-Transforer, IEEJ Journal of Industry Applications, Vol.4, No.7, pp , (5) [8] D. Ronanki, and S. S. Williason: Evolution of ower Converter Topologies and Technical Considerations of ower Electronic Transforer based Rolling Stock Architectures, IEEE Trans. On Transportation Electrification, (7) [9] X. Yu, X, She, X. Zhou and A. Q. Huang: ower Manageent for DC Microgrid Enabled by Solid-State Transforer, IEEE Trans., Vol.5, No., pp (4) [] A. Q. Huang, Q. Zhu, L. Wang, and L. Zhang, 5 kv SiC MOSFET: An Enabling Technology for Mediu Voltage Solid State Transforers, CSS Trans., Vol., No., pp.8-3 (7) [] J. W. Kolar and G. Ortiz: Solid-State-Transforers: Key Coponents of Future Traction and Sart Grid Systes, IEC 4, pp.-35 (4) [] T. Nakanishi, and J. Itoh, Design Guidelines of Circuit araeters for Modular Multilevel Converter with H-bridge Cell, IEEJ J. Industry Applications, vol.6, no.3, pp.3-44, (7) [3] H. Hwang, X. Liu, J. Ki and H. Li: Distributed Digital Control of Modular-Based Solid-State Transforer Using DS+FGA, IEEE Trans. On Industrial Electronics, Vol.6, No., pp.67-68, (3) [4] T. Nakanishi, and J. Itoh, Capacitor Volue Evaluation based on Ripple Current in Modular Multilevel Converter, 9th International Conference on ower Electronics, No. WeA-5, (5) [5] J. Shi, W. Gou, H. Yuan, T. Zhao and A. Q. Huang: Research on Voltage and ower Balance Control for Cascaded Modular Solid- State Transforer, IEEE Trans. On ower Electronics, Vol. 6, No. 4, pp.54-66, () [6] T. Isobe, H. Tadano, Z. He, and Y. Zou: Control of Solid-State- Transforer for Miniized Energy Storage Capacitors, IEEE ECCE, pp , (7) [7] J. E. Huber, and J. W. Kolar: Solid-State Transforer: On the Origins and Evolution of Key Concepts, IEEE Industrial Electronics Magazine, Vol., pp.9-8, (6) [8] T. Nussbauer, K. Raggl, and J. W. Kolar: Design Guidelines for Interleaved Single-hase Boost FC Circuits, IEEE Trans. On Industrial Electronics, Vol. 56, No. 7, pp , (9) [9] Y. Hayashi, Y. Matsugaki, and T. Ninoiya, Capacitively Isolated Multicell Dc-Dc Transforer for Future Dc Distribution Syste, IEEJ J. Industry Applications, vol. 6, no. 4, pp , (7) [] M. Sato, R. Takiguchi, J. Iaoka, and M. Shoyaa: A Novel Secondary WM Controlled interleaved LLC Resonant Converter for Load Current Sharing, IEMC 6, pp.76-8, (6) Loss [%] Experient Calculation Experient Calculation ower running Regeneration Total loss of 3-cell Boost inductor riary side rec. conduction loss Output capacitor loss Secondary rec. conduction loss HF trans._iron loss HF trans._copper loss Inductor_iron loss Inductor_copper loss LLC_conduction loss FC_switching loss FC_conduction loss Snubber loss Fig.. Loss distribution result by experient and calculation at bidirectional operation. (Explanatory note corresponds to each color of graph.) Loss [W] h = 99.% Outout capacitor Secondary side diode rec. High-frequency trans. Conduction loss (LLC) Switching loss (FC) Conduction loss (FC) Boost inductor riary side diode rec. Fig. 3. Loss distribution of 6.6 kv/ kw full odel SST by calculation. [] J. Itoh, T. Sakuraba, H. N. Le, K. Kusaka: Requireents for Circuit Coponents of Single-hase Inverter Applied with ower Decoupling Capability toward High ower Density, 8th European Conference on ower Electronics and Applications (EE'6), DSa 9, (6) [] J. Muhlethaler, J. Biela, J. W. Kolar, and A. Ecklebe: Iproved Core-Loss Calculation for Magnetic Coponents Eployed in ower Electronic Systes, IEEE Trans. On ower Electronics, Vol. 7, No., pp , ()