A Novel Five-level Three-phase PWM Rectifier. with Reduced Switch Count

Transcription

1 A Novel Five-level Three-phase PWM Rectifier with Reduced Switch Count Jun-ichi. Itoh*, Yuichi Noge*, Taketo Adachi* *Nagaoka University of Technology, Niigata, Japan Abstract This paper proposes a new circuit topology for a ultilevel PWM rectifier. The proposed ethod fors a new circuit by cobg a diode clap type topology with a flyg capacitor type topology. The proposed circuit uses only 1 switches, despite the use of a five-level three-phase PWM rectifier. Further, the proposed circuit can obta good perforance sae as a conventional ultilevel circuit. This paper describes about the features of the proposed topology; the control strategy and the loss analysis which is estiated by a circuit siulator. In addition, the basic operation of the proposed ethod is confired by siulation and experiental results. The proposed converter achieved THD (Total haronic distortion of 3.4% for the put current and efficiency of 97.4% for a 1 kw class experiental setup. Index Ter- Multilevel systes, Pulse width odulated power converters, AC-DC power conversion, Rectifiers, Power syste haronics *Nagaoka University of Technology, Nagaoka, Japan Telephone: FAX: E-ail: itoh@vos.nagaokaut.ac.jp (Jun-ichi Itoh noge@stn.nagaokaut.ac.jp (Yuichi Noge adachi@stn.nagaokaut.ac.jp (Taketo Adachi This paper was presented ECCE 9 San Jose California and odified to subit IEEE transaction on PELS.

2 I. INTRODUCTION Recently, the haronics current power grids have caused various probles, such as le voltage distortion and heatg power factor correction capacitors. The haronics current power grids is aly generated by a diode rectifier which is used as a front converter of an verter. In order to reduce the haronics current of the power grid, power factor correction (PFC rectifier still stands for a very iportant technology. A PWM rectifier, which is consisted of three switchg legs, reas one of the popular PFC rectifiers. A PWM rectifier can reduce the haronics current draatically because the grid current is able to control. A PWM rectifier requires high voltage ratg devices order to be applied to the ediu voltage applications. The high voltage ratg devices have known probles, such as low switchg speed and large saturation voltage between the collector and the eitter. The low switchg speed requires a large volue of a boost reactor and filter sce the high switchg frequency cannot be achieved. As a result, extra cost is needed for the applyg of the PWM rectifier a ediu voltage power grid. For a ediu voltage power grid, ulti-level converter technology is one of the solutions for high voltage rectification application [1]-[3]. In general, a n-level converter can reduce the voltage stress of a switchg device to 1/(n 1 of the DC output voltage. There are any circuit configurations for a ulti-level converter, such as the diode clap (DCLP type [4]-[5] that uses clap diodes and capacitors for the DC output voltage, the flyg capacitor (FC type [6]-[7] that uses clapg capacitors floatg on the DC output voltage, and the cascaded h-bridge type [8]-[9] that uses isolated power supplies to clap each level. In ter of cost reduction and downsizg, the DCLP and FC types are better solutions than the cascaded type, sce the cascaded type requires a large transforer and any switchg devices. However, for the ulti-level converters that are ore than three-level, the DCLP type requires balance circuits the DC part, order to control the clapg capacitor voltage [1]-[11]. And as for the FC type, it requires several capacitors for the clapg capacitors. In addition, both ethods needed to use a high aount of switchg devices. For exaple, the case of a five-level three-phase rectifier, 4 switchg devices are required. In conclusion, the probles of the ulti-level converters would be the nuber of switchg devices and the control of the clapg capacitor voltage. This paper proposes a novel five-level three-phase rectifier topology, which cobes the DCLP and FC type converters, and discusses about the control strategy. The proposed converter requires only half of the nuber of switches coparison to the DCLP and FC types, that is, only 1 switches are used for the five-level rectifier. The pot of the proposed topology is that high voltage diodes can be ore easily to be utilized than the high voltage switchg devices. The features of the proposed circuit are described, and the space vector odulation is used as a control strategy. The used of space vector odulation can result a good susoidal current of the power grid. In addition, a loss analysis ethod based on the PSIM circuit siulator is troduced [13]. The validity of the proposed rectifier, the control strategy, the paraeter design ethod and the loss analysis are confired by experiental

3 results. II. PROPOSED CIRCUIT TOPOLOGY A. Conventional Circuit Fig. 1 (a shows the DCLP and (b shows the FC type five-level PWM rectifier topology. The switchg devices of both topologies are of the sae voltage ratg. Both converters can use a voltage ratg of 1/4 for the DC output voltage; however, these converters use 4 switchg devices. As a result, the cost will be creased and the control strategy is coplicated. For exaple, the control strategy for the FC type five-level PWM rectifier is described the followg. The FC type five-level PWM rectifier has 16 switchg patterns. The switchg patterns and its rectifier put voltage, which is the voltage pot between the rectifier and the boost up reactor based on the neutral pot of the power grid. There are any switchg patterns which can charge or discharge the flyg capacitor disregards of the sae voltage level. These switchg patterns should be selected order to control the voltage of each flyg capacitor constant. When the phase shift PWM is applied, the flyg capacitor voltage will be kept constant [14]-[15]. However, any voltage sensors are required to detect the voltage of the flyg capacitors ters of the voltage protection of power devices. On the other hand, for the DCLP type, the clapg capacitor voltage can not be controlled without an auxiliary circuit except for specific circustances [1]. Additional voltage regulators, such as DC choppers, are required to ata each clapg capacitor voltage at quarter of the DC output voltage. S ' V dc ' S ' ' (a Diode Clap (DCLP (b Flyg Capacitor (FC Fig. 1. Conventional five-level PWM rectifier topologies (sgle leg.

4 B. Proposed Circuit Fig. shows the proposed five-level PWM rectifier usg only 1 switches. The proposed converter cobes both the DCLP and FC types to one circuit. The voltage stress of the switch is 1/4V dc as sae as that of the conventional circuits. The voltage stress for diodes requires 1/V dc the proposed circuit. The current wavefor of the diode is PWM wavefors. However, the diode voltage does not receive reverse voltage for half period of the power grid frequency. As a result, there is no recovery ode the high voltage diode. Thus, the cost of the high voltage low speed diode is cheaper than the high voltage switchg devices. It should be noted that if the regeneration ode is required, then the high voltage diodes can be used replaced with the high voltage switchg devices. In this case, low speed switchg devices, such as a thyristor or a gate turn off thyristor (GTO, can be applied, because the high voltage switchg devices do not switch at high frequency, but only switch at the sae frequency of the power grid. The proposed topology can be applied for both low voltage (V, 4V application and ediu voltage (3.3kV, 6.6kV application. In the low voltage application, the low voltage ratg MOSFETs can be used to iprove the switchg frequency. On the other hand, a ediu voltage application, high voltage ratg (1/Vdc diodes are required. However, it costs lower than the high voltage ratg IGBTs. Table I shows a coparison aong the DCLP, FC and proposed rectifier. The largest advantage of the proposed circuit is that the nuber of coponents the proposed circuit could be used by usg high voltage diodes. The nuber of switchg devices the proposed circuit is reduced to 1, which is half of the conventional circuits. It should be noted that if the proposed concept is applied for N-level rectifier topology, then the nuber of switchg devices can always be reduced to half of that conventional N-level converter topology, because the outer diode can absorb half of the DC output voltage. The other large advantage of the proposed circuit is that the proposed circuit can control each of the clapg capacitor voltage. The voltage of the ner clapg capacitor C 1 can be controlled at 1/4V dc, because the structure of the side part is the sae as that to the FC type. The voltage of the iddle capacitors (C and C 3 also can also be TABLE I D R1 S R1 S R D R D S1 D T1 *1 S S1 S S S T1 * D S D T *1 S T * C 3 *1 COMPARISON OF THE DCLP, FC AND PROPOSED CONVERTER S R3 S R4 C 1 C C 1 C C 1 * C *1 V C1 D R S S3 D S * S T3 *1 D T S S4 * S T4 V dc C 3 *1 R L Proposed DCLP FC circuit Switch D R1 D S1 D T1 *1 Diode * Capacitor L Voltage ratg: *1 1/V dc * 1/4V dc Fig.. Proposed hybrid PWM rectifier. Control of the liited * possible possible capacitor voltage *1 cludg FWD * under specific circustances [1]

5 controlled at 1/V dc, because this part is the sae as the three-level rectifier. Note that the proposed circuit can not run an vert operation where the reverse energy will flow to the circuit because the diodes are used stead of switches. Fig. 3 shows the current path of the proposed rectifier each switchg pattern. The proposed rectifier has eight switchg patterns. However, the available switchg patterns are constraed by the direction of the grid current because the proposed circuit uses diodes the a current path. The switchg patterns and rectifier put voltage levels are described as followg. Note that the neutral pot of the DC side is defed as the zero voltage level this discussion. In prciple, the proposed circuit can output seven voltage levels to the AC side of the converter. However, order to control the ner clapg capacitor (C 1 voltage V c, two switchg patterns for the charge or discharge ode are required. Therefore, to keep the two switchg patterns, the voltage levels +V dc / V c and +V c, -V c and V dc / +V c are set to the sae voltage level of each. That is, V c is set to V dc /4. As a result, V c can be controlled by switchg pattern of ( and (3 or (6 and (7, respectively. III. CONTROL STRATEGY A. Space Vector Modulation In the case of the proposed rectifier, there are 61 kds of the voltage vectors, except for the charge or discharge S S S S Vc Vc Vc Vc (1 Vdc/ ( Vdc/ (5 Vdc/ (6 Vdc/ S S S S Vc Vc Vc Vc Vdc/ (3 (4 Vdc/ Vdc/ (7 (8 Vdc/ (a Positive period of the put voltage. (b Negative period of the put voltage. Fig. 3. Current path of the proposed rectifier.

6 switchg patterns to the ner clapg capacitor the proposed circuit. Firstly, the nearest three space vectors surroundg at the top of the output voltage vector of the rectifier are selected. Secondly, the output tie ratio of each of the voltage vector is calculated. Fally, the charge or discharge ode vector is selected accordg to the ner clapg capacitor voltage and the neutral pot voltage of the DC output part. Further details of the odulation strategy are provided ref. [16]. The ner clapg capacitor voltage is controlled by the selection of the switchg pattern, sce the proposed rectifier can output the sae voltage level usg different switchg patterns that achieved charge or discharge to the ner clapg capacitor. For usg the SVM, the output tie of each switchg pattern is anaged by the controller. The capacitor voltage can be controlled accurately at this pot. B. Control Block Diagra Fig. 4 shows the control block diagra for the space vector odulation of the proposed rectifier. The DC output voltage and the put current are controlled by a PI regulator on a rotatg frae, the sae as that a conventional PWM rectifier. In the switchg table, the output vector is detered by the agnitude of the vector, the phase angle of the power grid, and the capacitor voltage controls the conditions by usg a hysteresis controller. Fig. 5 shows the voltage wavefor of the rectifier put voltage. It is noted that the zero level of the rectifier put voltage is defed as the neutral pot voltage of the DC output part. Five-step stairs wavefor is obtaed as the rectifier put voltage, which is divided to six sectors by the voltage levels. Table II dicates the switchg pattern table of the proposed rectifier. The ner clapg capacitor voltage is controlled by selectg the switchg patterns, where it will appears the sae voltage to the rectifier put voltage but the ner clapg capacitor is controlled to either beg charged or discharged. For exaple, the sector II, when the rectifier put voltage is +V dc / or +V dc /4, if the ner clapg capacitor voltage V c is lower than its coand V c *, the charge ode (S and S4 are turned on will be selected. On the other hand, if V c is higher than V c *, the discharge ode (S1 and S3 are turned on will be selected. Thus, the ner clapg capacitor voltage can be controlled constantly at all sectors. V dc* + _ V dc PI * i q = i r i s it i d * + + i d d -q i q PI PI v 3 * v d -q a Vector-fo. SVM a -b * _ v b T 1 1,T + Carrier _ v sign SW table 4 4 S r1-4 S s1-4 1/4 v r v t q V 3 c* + 3 _ S t1-4 V c Fig. 4. Control block diagra for the proposed circuit.

7 Additionally, the neutral pot voltage of the DC output is controlled by the zero-phase sequence coponent the voltage coands at the power grid frequency as sae as the conventional three-level verter. The switchg pattern cludg the zero-phase sequence coponent is selected accordg to the put voltage polarity due to the liitation of the current path that is caused by the clapg diodes. For exaple, when the put voltage is positive, the switchg pattern + Table II will be selected for the zero level to crease the neutral pot voltage. On the other hand, when the switchg pattern is selected where the put voltage is negative the neutral pot voltage will be decreased. As a result, the DC part capacitor (C3 voltage can be balanced. IV. PARAMETER DESIGN METHOD A. Inductance of Input Inductor (L When the switchg frequency is higher than the put frequency, the fundaental coponent of the reactor voltage assues to be constant durg a switchg cycle. Then, the relations between the put ductor L and the put current ripple Δi can be expressed as 1 i L / a fsw vla vldt L f sw (4 where v V L v V L Vdc V st 4 conv Vdc V st conv ( t / 6 ( / 6 t / where f sw is the carrier frequency, ΔV conv is the put voltage ripple of the rectifier, V is the peak voltage of the put phase voltage. The duty ratio α for each section is defed as (5 because the rectifier voltage coand is a susoidal wavefor. a st a (st.5 ( t / 6 ( / 6 t / (5 TABLE II SWITCHING TABLE OF THE PROPOSED RECTIFIER I II III IV V VI +Vdc/4 Vdc/4 Vdc/ Fig. 5. Rectifier put voltage wavefor. t Sector Voltage level Turn-on switches I +V dc/4, + S - (-, - II +V dc/, +V dc/4 -S, S - (- III +V dc/4, + S - (-, - IV, V dc/4 -S, - (S - V V dc/4, V dc/ - (S -, - VI, V dc/4 -S, - (S -

8 Fig. 6 shows the value of v L a when V and ΔV conv are defed to 1 p.u. and, respectively. Sce the put current ripple is doated by v L a, the put current ripple Δi becoes the axiu value at the duty ratio of.5 when the DC voltage V dc is 1 p.u. Then the put phase angles ωt are s -1 (1/4, or s -1 (3/4. Note that if the DC voltage is changed, the peak position of v L a is only shifted to right and the peak value does not change as shown Fig. 7. Consequently, the axiu put current ripple Δi can be expressed as i V s(s Vdc V ( 4 V ( dc V V conv conv 1 L f 1 L f sw sw (6 Therefore, L can be designed by L 3 Vdc V ( 4 V conv 1 i f sw (7 Thus, the put reactor can be reduced by creasg the current ripple Δi and the switchg frequency f sw. B. Capacitance of Inner Clapg Capacitor (C 1 The variations of the output voltage are ±V dc /, ±V dc /4, and. Note that ±V dc /4 levels are outputted through the ner clapg capacitor C 1. The axiu output tie of ±V dc /4 levels can be expressed as T 1/ sw _ ax f sw Consequently, the axiu voltage ripple of C 1 is given by Vc C 1 Tsw_ ax _ peak i _ peak i dt 1 C1 fsw i i (8 (9 where i _peak is the peak of the put current. Practically, the peak current cludes the ripple coponents. Therefore, the capacitance of C 1 is decided by (1 fro (9. i C 1 _ peak V f c i sw (1 where Δi is the ripple current. v L a [p.u.] V dc =1. π/8 π/4 3π/8 π/ ωt [rad] Fig. 6. Input current ripple Δi and phase angle of put voltage.

9 As shown (1, the capacitance of C 1 can be reduced by creasg the switchg frequency and the allowance voltage ripple ΔV c. C. Capacitance of DC part Capacitor (C 3 At first, the quantity of the electric charge flows to the neutral pot should be calculated order to design the capacity of C 3. The relations between the voltage level and the current at the neutral pot are shown Table III. It is noted that the selected switchg pattern depends on the phase angle of the put voltage. For exaple, the quantity of the electric charge which flow to the neutral pot fro R phase is expressed as followg equations. Q Q T s /1 Vdc /4_3 c3 _3 I st( D_3 D Ts / 6 Vdc / 4 _ 36 c3 _ 36 I st( Ts /1 D dt dt (11 (1 where T s is a period of the put voltage, I sωt is the put current of R-phase, D is the duty ratio. The subscripts dicate the voltage level and the phase angle of the put voltage. It should be noted that duty ratio for to 3 on V dc /4 level is used as a half of the origal value because alost half of this period does not flow the current to the neutral pot. The rectifier voltage coand is fored susoidal, and then it can be defed as 1% at and % at 3 while outputtg voltage level. At V dc /4 output voltage level, the rectifier voltage coand can be defed as 1% at 3 and % at 9. Consequently, the duty ratio of each area can be expressed as D 1 st _ 3 D Vdc st / 4_ 3 D Vdc / 4 _ 36 t (1 s The quantity of the electric charge Q np fro to 6 region can be expressed by (16. Q np ( Q I Ts /6 c3_3 Q c3_ 36 I st(1 st dt ( Ts 16 1 (13 (14 (15 (16 On the other hands, the DC output voltage ripple is generated at six ties of the put voltage frequency. Then, the axiu quantity of the rectifier put electric charge (Q _R, Q _T can be expressed by (17, (18 for a half cycle of the output voltage ripple, i.e. T s /1. Q _ R Ts /1 I Ts cos 1 I st dt 1 (17

10 Q _ T Ts /1 4 I s t dt 3 I Ts cos (18 Q out is the quantity of the electric charge which is supplied to the load. Q out IloadTs 1 (19 where Q out is the DC output current. Therefore, the quantity of the electric charge which flow to the neutral pot at the terval of T s /1 is expressed as Q C3 ( Q _ R Q _ T 3Q np Q out I load I Ts 8 1 ( Note that T s /1 is equal to /6. Next, the DC output voltage ripple ΔV dc can be expressed as (1 with the put current ripple Δi. V dc 1 i (3 C f sw Q C3 (1 Fally, the capacitance of C 3 can be calculated. 1 C3 V dc 1 V dc i (3 f sw i 3 f sw Q I C Iload T s 8 1 ( As shown (, the capacity of C 3 can be reduced by creasg voltage ripple ΔV dc and the switchg frequency f sw. D. Capacitance of Clapg Capacitor (C The capacitance of C depends on the voltage fluctuation of the neutral pot voltage at the DC lk part. The TABLE III VOLTAGE LEVELS AND CONNECTION TO NEUTRAL POINT Phase angle of put voltage Voltage level Current to neutral pot Active +V dc/4 (C 1 Charge / Discharge Active/active +V dc/4 (C 1 Charge / Discharge Active/active +V dc/ Active

11 relations between the voltage ripple of the neutral pot ΔV np and C can be calculated fro the quantity of the electric charge flowg to the neutral pot (Q np, as expressed by (3. Qnp Vdc Vnp (3 C C 3 As a result, the capacitance of C can be calculated by (4 fro (3. C I 4 ( 3 1 T s Vnp Vdc 8 6 C 3 (4 As shown (4, the capacitance of C can be reduced by creasg the voltage ripple of neutral pot ΔV np. V. EXPERIMENTAL RESULT Fig. 7 shows the operation wavefors for the proposed rectifier. The put voltage is V, 5 Hz, the output power is 1 kw (ratg, and the DC output voltage coand is set to 3 V, that is, the ner clapg capacitor voltage coand is set to 8 V (the circuit paraeter is the sae as Table IV. Susoidal put current wavefors with THD of 3.4% is obtaed (the 4 th or less order coponents haronics were considered. In addition, the DC output voltage and the ner clapg capacitor voltage agrees with coands of that respectively. In Fig. 7, a five-step voltage wavefor is observed the rectifier put voltage of the proposed converter, which agrees with the expectation. It should be noted that the spike voltage the rectifier put voltage is caused by the coutation of the diode at the edge of the sectors. However, each switchg of the device voltage is claped by the ner or outer clapg capacitor. Therefore, the low voltage ratg switchg device can be used as discussed previous chapter. Fig. 8 shows the haronic analysis of put current. Each haronic coponent is less than % which is coplyg with IEC61-3- standards. Fig. 9 shows the load step response. A load is changed at the dotted le fro.5 kw to 1. kw. The put current is creased to twice of it. However, the DC output voltage and the ner clapg capacitor voltage are kept constant. Therefore, the load regulation characteristic is confired by this experiental result. Fig. 1 shows the voltage ripple of the ner clapg capacitor and the rectifier put current ripple. Fig. 11 shows the voltage ripple of the DC output and the neutral pot. The paraeters are designed by the optial design ethods which are discussed section III. The results shown Table V are accurately atched with the design paraeters.

12 Fig. 1 shows the efficiency and put power factor of the proposed rectifier. The axiu efficiency is 97.6% at a.5 kw load, and an put power factor of over 98% is achieved at over.5 kw load. The proposed circuit can obta efficiency of over 97% a wide load condition because the switchg frequency of the outer diode is the sae as the power grid frequency even if that of the ner switchg device is high. Fig. 13 shows the put current THD of the proposed rectifier. The proposed rectifier achieves 3.4% THD for the put current. It should be noted that the THD creases the light load condition because the agnitude of the haronics coponent is alost constant. Therefore, the ratio between the fundaental and haronics coponent becoes larger the light load condition Fig. 14 illustrates the loss analysis result for a 1 kw load. The power loss is coposed by lkg a circuit siulator (PSIM, Powersi Technologies Inc. and a DLL (Dynaic Lk Library file. The DLL file contas a loss table that calculates the switchg loss and conduction loss based on the stantaneous values of the current and the voltage of the power device, as written [13]. This ethod can estiate the power seiconductor loss any kd of circuit configurations. The loss siulation results are well agreed with the efficiency fro the experiental results. In the proposed circuit, the conduction loss is the ost doant section of the power losses. In order to iprove the efficiency, a low conduction loss device should be selected. TABLE IV PARAMETERS OF THE PROPOSED RECTIFIER Output power Input voltage Input frequency Output voltage coand (Vdc * Load resistance(rl Inner clapg capacitor(c1 Clapg capacitor(c DC part capacitor(c3 Carrier frequency Input ductor (L 1 [kw] [V] 5Hz 3 [V] 1 [] 47 [F] 1 [F] [F] 1 [khz] [H]

13 Input voltage [5V/div] Input current [5A/div] DC output voltage [5V/div] Inner clapg capacitor (C 1 voltage [1V/div] 1 Rectifier put voltage [5V/div] Content rate [%] s Haronic nuber Fig. 7. Experiental results of the proposed rectifier at a 1 kw. Fig. 8 Haronic current analysis at 1kW. Input voltage [5V/div] Input current [5A/div] DC output voltage [5/div].5kW 1kW Inner clapg capacitor (C1 voltage [1V/div] s Fig. 9. Experiental result of load step response 3 DC output voltage (V dc [V].5V/div 3.1V Flyg capacitor voltage (V C1 [V] V/div Neutral pot voltage (V np [V] 5V/div V 74.3 Input current (i [A] 5A/div 5A/div Input current (i [A] 5A/div 4s 4s 4s Fig. 1. Experiental result of the ner clapg capacitor voltage ripple and the put current ripple. Fig. 11. DC output voltage ripple and neutral pot voltage ripple.

14 TABLE V THEORETICAL AND EXPERIMENTAL RESULT OF THE RIPPLES. Paraeters Equation Theoretical Experiental Rearks i (6 1.1 A 1. A V conv = 7 V V C ( V 11 V V dc (1 3.1 V 3. V V np (3 9.4 V 9. V Efficiency and put power factor [%] Input power factor Efficiency Input current THD [%] Output power [kw] Output power [kw] Fig. 1. Input power factor and efficiency of the proposed rectifier. Fig. 13. Input current THD of the proposed rectifier. Efficiency 97.6% Loss.4% Conduction loss 65.3% Recovery loss 3.8% Turn-on loss 1.5% Turn-off loss.4% Fig. 14. Loss analysis results by loss siulation at a 1 kw load. VI. CONCLUSIONS A novel five-level PWM rectifier and its control strategy have been proposed. Features of the proposed circuit are the followg; nuber of reduction of the switchg devices, and a controllable clapg capacitor voltage. The proposed converter achieves THD of 3.4% for the put current at a 1 kw load and efficiency of 97.6% at a.5 kw load for a 1 kw class experiental setup.

15 REFERENCES [1] B. Sgh, B. N. Sgh, and A. Chandra, et al, A Review of Three-Phase Iproved Power Quality AC-DC Converters, IEEE Transactions on dustrial electronics, vol.51, no.3, pp , 4. [] J. Rodriguez, L. G. Franquelo, and S. Kouro, et al : Multilevel Converters: An Enablg Technology for High-Power Applications, Proceedgs of the IEEE, vol.97, no.11, pp , 9. [3] U. Drofenic, J. W. Kolar, Y. Nishida, Y. Okua, and J. Sun, Three-Phase PFC Rectifier Systes, PCC-Osaka Tutorials, pp.-93,. [4] X. Yuan, I. Barbi, Fundaentals of a New Diode Clapg Multilevel Inverter, IEEE Transactions on power electronics, vol.15, no.4, pp ,. [5] Z. Pan, F. Z. Peng, and K. A. Corze, et al, Voltage Balancg Control of Diode-Claped Multilevel Rectifier/Inverter Systes, IEEE Transactions on dustry applications, vol.41, no.6, pp , 5. [6] A. A. Sneeh, M. Wang, Novel Hybrid Flyg-Capacitor -Half-Bridge 9-Level Inverter, TENCON 6. [7] X. Kou, K. A. Corze, and Y. L. Failiant, A Unique Fault-Tolerant Design for Flyg Capacitor Multilevel Inverter, IEEE Transactions on power electronics, vol.19, no.4, pp , 4. [8] D. Kang, Y. Lee, B. Suh, C. Choi, and D. Hyun, An Iproved Carrier-Based SVPWM Method Usg Leg Voltage Redundancies Generalized Cascaded Multilevel Inverter Topology, IEEE Transactions on power electronics, vol.18, no.1, pp , 3. [9] F. Z. Peng, J, W. McKeever, and D. J. Adas, A Power Le Conditioner Usg Cascade Multilevel Inverters for Distribution Systes, IEEE Transactions on dustry applications, vol.34, no.6, pp , [1] F. Z. Peng, A Generalized Multilevel Inverter Topology with Self Voltage Balancg, IEEE Transactions on dustry applications, vol.37, no., pp. 4-31, 1. [11] Natchpong Hatti, Kazunori Hasegawa, and Hirofui Akagi, A 6.6-kV Transforerless Motor Drive Usg a Five-Level Diode-Claped PWM Inverter for Energy Savgs of Pups and Blowers, IEEE Transactions on power electronics, vol.4 No.3, pp [1] Marya Saeedifard, Reza Iravani, and Josep Pou, A Space Vector Modulation Strategy for a Back-to-Back Five-Level HVDC Converter Syste, IEEE Transactions on dustrial electronics, vol.56 No., pp [13] Jun-ichi Itoh, Takashi Iida, and Akihiro Odaka, Realization of High Efficiency AC lk Converter Syste based on AC/AC Direct Conversion Techniques with RB-IGBT, Industrial Electronics Conference, Paris, PF-1149, 6. [14] Dae-Wook Kang, Byoung-Kuk Lee, and Jae-Hyun Jeon, et al A Syetric Carrier Technique of CRPWM for Voltage Balance Method of Flyg-Capacitor Multilevel Inverter, IEEE Transactions on dustrial electronics, vol.5 No.3, pp [15] Chunei Feng, Jun Liang, and Vassilios G. Agelidis, Modified Phase-Shifted PWM Control for Flyg Capacitor Multilevel Converters, IEEE Transactions on power electronics, vol. No.1, pp [16] Jun-ichi Itoh, Yuichi Noge, and Taketo Adachi, A novel five-level three-phase PWM rectifier usg 1 switches, Energy Conversion Conference and Exposition, San Jose, CA, pp31-317, 9.

16 Jun-Ichi Itoh was born Tokyo, Japan, 197. He received the M.S. and Ph.D. degrees electrical and electronic systes engeerg fro Nagaoka University of Technology, Niigata, Japan, 1996,, respectively. Fro 1996 to 4, he was with Fuji Electric Corporate Research and Developent, Ltd., Tokyo, Japan. Sce 4, he has been with Nagaoka University of Technology, Niigata, Japan as Associate Professor. His research terests are atrix converters, dc/dc converters, power factor correction techniques and otor drives. Dr. Itoh received the IEEJ Acadeic Prootion Award (IEEJ Technical Developent Award 7 and the Isao Takahashi Power Electronics Award 1. He is eber of the Institute of Electrical Engeers of Japan. Yuichi Noge was born Wakayaa, Japan, He received the B.S. degrees electrical, electronics and foration engeerg fro Nagaoka University of Technology, Nagaoka, Japan, 8 respectively. Sce 8, he has been with Nagaoka University of Technology as a aster student. His a research terests are ultilevel power converters. Mr. Noge is a eber of the Institute of Electrical Engeers of Japan. Taketo Adachi was born Miyagi, Japan, He received the B.S. and M.S. degrees electrical, electronics and foration engeerg fro Nagaoka University of Technology, Nagaoka, Japan, 7 and 9 respectively. Sce 9, he has been An eployee of Fuji Electric FA Coponents & Systes Co., Ltd and eber of IEEJ. His a research terests are ultilevel power converters.