Summary. 1 Introduction. 2 Proposed circuit topology. 2.1 Conventional circuit

Transcription

1 Evaluation o Power Denity o a Reduced Switch Count Five-level Three-phae PWM Rectiier or Aircrat Application Jun-ichi Itoh, Yuichi Noge Nagaoka Univerity o Technology 63- Kaitoioka, Nagaoka, Niigata, Japan Suary Recently, ore electric aircrat concept i attracted to achieve ore light weight and downizg o an aircrat. Thi paper propoe a novel ive-level three-phae rectiier topology, which cobe the DCP and FC type erter ha been propoed. The propoed erter require only hal o the nuber o itche coparion with the DCP and FC type, that i, only itche are ued or the ive-level rectiier. Moreover, the volue o the put boot reactor can be reduced due to 5-level put voltage waveor o the rectiier. Thi paper etablihe the optiization deign ethod o the boot-up reactor, clapg capacitor and power device order to achieve high power denity. Beide, it volue and power-denity are obtaed by the theoretical analyi. Introduction Recently, ore electric aircrat concept i attracted to achieve ore light weight and downizg o an aircrat [3]. A rectiier the aircrat application i required to reduce haronic current a power grid. The haronic current the power grid caue variou proble, uch a le voltage ditortion and EMI. In order to reduce the haronic current o the power grid, power actor correction (PFC rectiier ug a PWM rectiier i a very iportant technology ter o light weight and downizg coparion to paive PFC rectiier. A PWM rectiier, which conit o three itchg leg, i popular PFC rectiier; however entional PWM rectiier o -level i diicult to reduce the put haronic current the aircrat application becaue the axiu put requency i around 8Hz. On the other hand, a ulti-level erter technology i one o the olution to obta high eiciency and low put haronic current or high requency put at the ae tie [4]. In general, a n-level erter can reduce the voltage tre o a itchg device to /(n o the DC output voltage. PWM rectiier o 3-level ug VIENNA topologie have been achieved low haronic current and high power denity []. Thi erter ue only ix itche pite o three-level topology o a three-phae rectiier, however ter o ore reduction o lo and haronic current, the rectiier hould ake a lot o level. There are any circuit coniguration or a ulti-level erter, uch a the diode clap (DCP type that ue clap diode and capacitor to divide the DC output voltage, the lyg capacitor (FC type that ue clapg capacitor loatg on the DC output voltage [6]. However the DCP type rectiier ore than our-level require balance circuit the DC part, order to control the clapg capacitor voltage. In contrat, the FC type require everal capacitor or the clapg capacitor. Beide, both ethod ue any itche. For exaple, the cae o a ive-level three-phae rectiier, 4 itchg device are required. In concluion, the proble o ultilevel erter are the nuber o itchg device and the volue o the clapg capacitor voltage. Then it i not enough to achieve high power denity rectiier by entional ulti-level rectiier. A ive-level three-phae rectiier topology, which cobe the DCP and FC type erter ha been propoed [4]. The propoed circuit require only hal o the nuber o itche coparion with the DCP and FC type, that i, only itche are ued or the ive-level rectiier. The pot o the propoed topology i that high voltage diode can be ore eaily to be utilized than high voltage itchg device. Thereore the propoed erter reduce the nuber o coponent. Beide, a low on-tate reitance MOSFET i ued tead o IGBT becaue the voltage tre o the power device becoe /4 o the DC output voltage. That i the propoed erter ug MOSFET achieve high eiciency. Thi paper dicue the optiization deign ethod o the boot-up reactor, clapg capacitor and power device or the propoed circuit. In the propoed circuit, the volue o the put boot reactor can be reduced due to ive-level put voltage waveor o the rectiier. In addition, the volue o the other paive coponent or the propoed erter i entioned to dicate the rearkable iaturization o the propoed circuit coparion to the entional two or three-level erter topology [5]. Beide, it volue and power denity are dicued by the theoretical analyi. Propoed circuit topology. Conventional circuit Figure (a how the DCP and (b how the FC type ive-level PWM rectiier topology. The itchg device o both topologie are o the ae voltage ratg. Both erter can ue a voltage ratg o /4 or the DC output voltage; however, thee erter ue 4 itchg device. A a reult, the cot creae and the control trategy becoe coplicated. In the DCP type, the clapg capacitor voltage can not be controlled without an auxiliary circuit. Additional

2 voltage regulator, uch a DC chopper, are required to ata each clapg capacitor voltage at quarter o the DC output voltage [7]. On the other hand, the FC type ha any itchg pattern which can charge or dicharge the lyg capacitor diregard o the ae voltage level. Thee itchg pattern hould be elected order to control the voltage o each lyg capacitor. However, everal lyg capacitor are needed and any voltage enor are required to detect the voltage o the lyg capacitor practically.. Propoed circuit Figure how the propoed ive-level PWM rectiier ug only itche. The propoed circuit cobe both the DCP and FC type to one. High voltage ratg diode are required the propoed circuit; however, a at recovery diode i unneceary, becaue there i no recovery ode or the high voltage diode the propoed circuit. Thu, the high voltage low peed diode i cheaper than the high voltage itchg device. Table how a coparion aong the DCP, FC and propoed rectiier. The larget advantage o the propoed circuit i that the propoed circuit allow the nuber o the itche and capacitor to reduce, o that the nuber o itchg device becoe pite o three-phae rectiier, which i hal o the entional circuit. It hould be noted that i the propoed concept i applied or other ulti-level count, then the nuber o itchg device can alway be reduced to hal o that entional topology, becaue the outide diode can take hal o the DC output voltage. The other large advantage o the propoed circuit i that the propoed circuit can control each clapg capacitor voltage. The voltage o the ner clapg capacitor C can be controlled, becaue the tructure o the ide part i the ae a that to the FC type. The voltage o the iddle capacitor (C and C 3 alo can alo be controlled, becaue thi part i the ae a the three-level rectiier. Note that the propoed circuit can not accept an vert operation where the revere energy will low becaue the diode are ued tead o itche. Figure 3 how the voltage waveor o the rectiier put voltage. It i noted that the zero level o the rectiier put voltage i deed a the neutral pot voltage o the DC output part. Five-tep tair waveor i obtaed a the rectiier put voltage, which i divided to ix ector by the voltage level. Table dicate the itchg pattern table o the propoed rectiier. For exaple, the ector II, when the rectiier put voltage i V dc / or V dc /4, i the ner clapg capacitor voltage V c i lower than it coand V c *, the charge ode (S and S 4 are turned on will be elected. On the other hand, i V c i higher than V c *, the dicharge ode (S and S 3 are turned on will be elected. Thu, the ner clapg capacitor voltage can be controlled contantly at all ector. Additionally, the neutral pot voltage o the DC part i controlled by the zero level a the ae a a entional three-level verter. The zero level output itchg pattern i elected by the put voltage polarity. When the put voltage i poitive, the i elected or the zero level to creae the neutral pot voltage. On the other hand, the i elected when the put voltage i negative to decreae the neutral pot voltage. A a reult, the DC part capacitor (C 3 voltage can be balanced by the zero level election..3 Experiental reult The propoed circuit wa deontrated by all capacity prototype. The circuit paraeter and condition i hown Table 3. The put voltage i V, 5 Hz, the output power i kw (ratg, and the DC output voltage (a Diode Clap (DCP (b Flyg Capacitor (FC Figure Conventional ive-level PWM rectiier topologie (gle leg. Figure Propoed hybrid PWM rectiier. Table Coparion o the DCP, FC and propoed erter Propoed DCP FC circuit Switch 4 4 Diode * Capacitor Control o the capacitor voltage ipoible poible poible * cludg FWD

3 coand i et to 3 V, that i, the ner clapg capacitor voltage coand i et to 8 V. It i noted that the ore high requency power grid could not be ued laboratory condition; however calg aong the control period, itchg requency and power grid requency ha been conidered. Figure 4 how the operation waveor or the propoed rectiier. The uoidal put current waveor without ditortion are obtaed and the total haronic current (THD o that i 3.4% (the 4 th or le order coponent haronic were conidered. In addition, the DC output voltage and the ner clapg capacitor voltage agree with coand o that repectively. In Figure 4, a ive-tep voltage waveor i oberved the rectiier put voltage o the propoed erter, which agree with the expectation. It hould be noted that the pike voltage the rectiier put voltage i caued by the coutation o the diode at the edge o the ector. However, each itchg o the device voltage i claped by the ner or outer clapg capacitor. Thereore, the low voltage ratg itchg device can be ued. Figure 5 how the operation waveor at 6Hz undaental requency. Thi condition i uppoed to apply aircrat power upply yte (4Hz undaental requency at 5 khz carrier with a carrier and power upply requency calg (6Hz undaental requency at khz carrier. The uoidal put current waveor are obtaed, and the total haronic ditortion (THD or the put current i.4%. 3 Paraeter deign ethod 3. Inductance o boot-up ductor ( When the itchg requency i higher than the put requency, the undaental coponent o the reactor voltage aue to be contant durg a itchg cycle. Then, the relation between the put ductor and the put current ripple i can be expreed a where v V i / α vα vdt Vdc ωt 4 ( ωt π / 6 (. Vdc v V ωt ( π / 6 < ωt π / where i the carrier requency, i the put voltage ripple o the rectiier and V i the peak voltage o the put phae voltage. Table 3 Experient paraeter o the propoed rectiier Output power [kw] Input voltage [V] DC output voltage coand (Vdc * 3 [V] oad reitance(r [Ω] Inner clapg capacitor(c 47 [µf] Clapg capacitor(c [µf] DC part capacitor(c3 [µf] 5 [Hz] Carrier requency [khz] Input ductor ( [H] 6 [Hz] Carrier requency [khz] Input ductor ( [H] Input voltage [5V/div] Input current [5A/div] DC output voltage [5V/div] Inner clapg capacitor (C voltage [V/div] Rectiier put voltage [5V/div] Figure 4 Experiental reult o the propoed rectiier at a 5Hz undaental requency Figure 3 Rectiier put voltage waveor. Table Switchg table o the propoed rectiier Sector Voltage level Turn-on itche I V dc/4, S -S 4 (S -S 3, S 3-S 4 II V dc/, V dc/4 S -S, S -S 4 (S -S 3 III V dc/4, S -S 4 (S -S 3, S 3-S 4 IV, V dc/4 S -S, S -S 3 (S -S 4 V V dc/4, V dc/ S -S 3 (S -S 4, S 3-S 4 VI, V dc/4 S -S, S -S 3 (S -S 4 Figure 5 Experiental reult o the propoed rectiier at a 6Hz undaental requency

4 Sce the rectiier voltage coand i a uoidal waveor, the duty ratio α or each ection i deed a α ωt ( ωt π / 6 (. α (ωt.5 ( π / 6 < ωt π / Figure 6 how the value o v α when V and are deed to p.u. and, repectively. Sce the put current ripple i doated by v α, the put current ripple i becoe the axiu value at the duty ratio o.5 when the DC voltage V dc i p.u. Then the put phae angle ωt are - (/4, or - (3/4. Note that i the DC voltage i changed, the peak poition o v α i only hited to right and the peak value doe not change a hown Figure 6 Conequently, the axiu put current ripple i can be expreed a i V ( 3 V Vdc ( Vdc ( Thereore, can be deigned by 3 Vdc V ( 4 i (3. (4. Thu, the put reactor can be reduced by creag the current ripple i and the itchg requency. 3. Capacitance o ner clapg capacitor (C The output voltage variation o the propoed circuit are ±V dc /, ±V dc /4, and. Note that ±V dc /4 level are outputted through the ner clapg capacitor C. The axiu output tie o ±V dc /4 level can be expreed a T _ ax / (5. Conequently, the axiu voltage ripple o C i given by i i c C (6. T _ ax _ peak _ peak dt C where i _peak i the peak o the put current. Practically, the peak current clude the ripple coponent. Thereore, the capacitance o C i decided by (7 ro (6. C i i _ peak (7. C where i i the ripple current. A hown (, the capacitance o C can be reduced by creag the itchg requency and the allowance voltage ripple c. 3.3 Capacitance o DC part capacitor (C 3 At irt, the quantity o the electric charge low to the neutral pot hould be calculated order to deign the capacity o C 3. The relation between the voltage level and the current that low to the neutral pot i hown Table 4. It i noted that the elected itchg pattern depend on the phae angle o the put voltage. For exaple, the quantity o the electric charge which low to the neutral pot ro R phae i expreed a ollowg equation. T / DVdc / 4 _ 3 Qc3 _ 3 I ( ω t D _ 3 dt (8. T / 6 DVdc / 4 _ 3 6 Qc3 _ 3 6 I ω t( dt (9. T / where T i a period o the put voltage, I ωt i the put current o R-phae, D i the duty ratio. The ubcript dicate the voltage level and the phae angle o the put voltage. It hould be noted that duty ratio or to 3 on V dc /4 level i ued a a hal o the origal value becaue alot hal o thi period doe not low the current to the neutral pot. The rectiier voltage coand i ored uoidal, and then it can be deed a % at and % at 3 durg zero output voltage level. At V dc /4 output voltage level, the rectiier voltage coand can be deed a % at 3 and % at 9. Conequently, the duty ratio o each area can be expreed a D _ 3 ωt (3. D Vdc / 4 _ 3 ωt (4. D Vdc / 4 _ 3 6 ( ωt (5. The quantity o the electric charge Q np ro to 6 region can be expreed by (6. Q ( Q Q (6. np c3_ 3 c3_ 3 6 On the other hand, the DC output voltage ripple i generated at ix tie o the put voltage requency. Then, the axiu quantity o the rectiier put electric charge (Q _R, Q _T can be expreed by (7, (8 or a hal cycle o the output voltage ripple, i.e. T / Figure 6 Input current ripple i and phae angle o put voltage. Table 4 Voltage evel and Connection to Neutral Pot Phae angle o Current to neutral Voltage level put voltage pot Active -3 V dc/4 Active/active (C Charge / Dicharge 3-6 V dc/4 (C Charge / Dicharge Active/active V dc/ Active

5 Q _ R T I ( ωt dt I ωt co ω T (7. 4 Q _ T I ωt π dt 3 (8. I 4 ωt co π ω 3 The quantity o the electric charge Q out which i upplied to the load i obtaed by I loadt Q out (9. Next, the DC output voltage ripple dc can be expreed a ( with the put current ripple i. i Vdc (3 QC 3 (. C Fally, the capacitance o C 3 can be calculated. Note that ωt / i equal to π/6. i C3 (3 QC 3 dc (. i I π Iload 3 dc π 4 T Fro (, the capacity o C 3 can be reduced by creag voltage ripple dc and the itchg requency. Capacitance o Clapg Capacitor (C The capacitance o C depend on the voltage luctuation o the neutral pot o the DC lk part. The relation between the voltage ripple o the neutral pot np and C can be calculated ro the quantity o the electric charge lowg to the neutral pot (Q np, a expreed by Qnp dc Vnp (3. ( C C 3 A a reult, the capacitance o C can be calculated by Qnp C np C 3 I 9 3 π ( C3 np dc dc A hown (4, the capacitance o C can be reduced by creag the voltage ripple o neutral pot np. 4 Conideration o theoretical volue o paive coponent 4. Volue o put ductor The put ductor volue i depend on everal actor which are axiu put current I ax, ductance and aturable lux denity B at. The core lux o the put ductor (φ can be expreed by I ax φ B S at c (5. N where S c i the cro-ection area o the ductor core. Thi equation i tranored to I ax Sc (6. B N at On the other hand, the radiu o the wdg wire can be expreed by I ax rw S w (7. π π I where S c i the cro-ection area o the wdg wire. I d i the allowable current denity o the wdg wire, which i et to A/ thi paper. The length o the agnetic circuit l can be expreed by d l r N (8. w Figure 7 how the hape o the boot-up ductor ug troidal core to obta the put ductor volue (V, (6, (7 and (3 are uarized a V l Sc π Sc r (9. π w 4. Volue o capacitor The volue o the capacitor i depend on capacitance C, dielectric contant ε and applied voltage. The thickne o dielectric il d depend on applied voltage. The capacitance C and the volue o the capacitor V c can be expreed by (3 and (3. S C ε (3. ε d Cd Vc Sd (3. ε ε Fro (3, the volue o the capacitor i proportional to the capacitance and proportional to the quare o the thickne o dielectric il. 4.3 Coparion o volue In thi ection, the propoed 5-level erter i copared with a DCP 3-level erter. The total volue o paive coponent i calculated by u o (9 and (3 accordg to each ductance and capacitance. Note that the ductance and capacitance are decided accordg to the power ratg or put requency. In order to calculate the value o the paive coponent, C, C and C 3, the deign paraeter are ued Table 5. In addition, the paraeter o paive coponent are hown below. JFE Steel JNHF (µ :4., B at :.5[T] high requency electrical Figure 7 Coniguration o the put ductor core. (croection diagra

6 teel heet i ued calculation or the volue o an put boot-up ductor. In act, concerng capacitor, there are variou type o dielectric contant ε and thickne dielectric il d. In thi paper, thee paraeter o Nichicon GU erie electrolytic capacitor are ued calculation. Figure 8 how the volue o paive coponent accordg to power ratg. An upward trend o the volue can be uppreed over 3 kw power ratg area o the propoed circuit. The advantage o the propoed circuit i tend. Figure 9 how the volue o paive coponent or power upply requency. The volue o the propoed circuit i dratically decreaed by creag the power upply requency. For exaple, the volue o paive coponent o the propoed rectiier i.8% aller than DCP at 5 Hz. However, it i aller than.% at 8 Hz. Thi i becaue the capacitor volue i the doant paraeter the propoed circuit. Figure how the power denity o paive coponent a a unction o power ratg. It hould be noted that the power denity o power eiconductor and heat k are aued a alot ae i power ratg and the put requency i changed. High power denity can be achieved high power ratg area over 3 kw. Thee analyi reult dicate that the propoed circuit i uitable or high requency and large capacity application uch a aircrat power upply yte. 5 Concluion A novel ive-level PWM rectiier and it control trategy have been propoed. Feature o the propoed circuit are the reduction the nuber o itchg device, and a controllable clapg capacitor voltage. The propoed erter achieve THD o 3.4% or the put current at 5 Hz and.4% at 6 Hz or a kw cla experiental prototype. Fally, the iaturization o the paive coponent i conired by conideration o the theoretical volue calcuation. The volue o the paive coponent are.% aller than DCP three-level at 8 Hz. In addition, high power denity can be achieved high power ratg area over 3 kw. 6 iterature [] B. Sgh, B. N. Sgh, and A. Chandra, et al, A Review o Three-Phae Iproved Power Quality AC- DC Converter, IEEE Tranaction on dutrial electronic, vol.5, no.3, pp.64-66, 4. [] F. Z. Peng, A Generalized Multilevel Inverter Topology with Sel Voltage Balancg, IEEE Tranaction on dutry application, vol.37, no., pp. 4-3,. [3] H. Wol, T.Gathann "Active Three-Phae Rectiier or Aircrat Equipent" EPE 5, Dreden, 5 [4] J. Itoh, Y. Noge and T. Adachi: A novel Five-level PWM Rectiier Ug itche, ECCE IEEE, P (9 [5] J. W. Kolar, J. Biela: "Explorg the Pareto Front o Multi-Objective Sgle-Phae PFC Rectiier Deign Optiization -99.% Eiciency v. 7kW/d3 Power Denity" IPEMC, 9 [6] P. Barboa, P. Steier : "Active Neutral-Pot- Claped Multilevel Converter" COMPE, 5 [7] N. Hatti, Y. Kondo, H. Akagi : "Five-evel Diode- Claped PWM Converter Connected Back-to-Back or Motor Drive" IEEE Tranaction on dutry application, vol.44, iue 4, pp.68-76, 8 Table 5 Calculation paraeter Ite Sybol Value Inductor current ripple i % Capacitor voltage ripple C, np, dc 5% Volue o paive coponent [ 3 ] Switchg requency 5kHz Figure 8 Volue o paive coponent or power ratg at 8[Hz] Volue o paive coponent [ 3 ] Figure 9 Volue o paive coponent or power upply requency at P5[kW] Power denity o paive coponent [W/ 3 ] Figure Power denity o paive coponent or power ratg at 8[Hz]