Power Losses of Multilevel Converters in Terms of the Number of the Output Voltage Levels

Transcription

1 ower Losses of Multilevel Converters in Ters of the Nuber of the Output Voltage Levels Yugo Kashihara Energy and Environental Science Nagaoka University of Technology Nagaoka, Niigata, Japan Ju-ichi Itoh Electrical Engineering Nagaoka University of Technology Nagaoka, Niigata, Japan Abstract This paper presents loss calculation ethods of which the ultilevel converters have several nuber of the output voltage level. The ultilevel converters of the flying capacitor topology and the active neutral point clap topology are evaluated in ters of the high efficiency in this paper. In addition, the power losses of the ultilevel converters are discussed using two power devices. As a result, in case of the MOSFET device, the active neural point clap topology is better than the flying capacitor topology, regardless of the nuber of level. The power loss of the two-level inverter is lower than other topologies. Keywords Inverter, Multilevel converter, ower loss, hoto voltaic. I. INTRODUCTION In ters of syste integration on power electronics syste, it is iportant to choose suitable circuit topology according to the purpose of the syste. Multilevel converters are one of the good options in order to obtain high efficiency. In general, ultilevel converters are applied in ediu-voltage applications, such as large power otor drives and 6.6-kVA power transission lines because by coparing between the ultilevel converters and the conventional two-level converters, the ultilevel converter can reduce the voltage stress of a switching device to /(n-) of the DC input voltage and also reduce the haronic coponent of the output voltage. Hence, applications of ultilevel converters have been actively investigated [-5]. However, in order to achieve high efficiency using low conduction loss devices such as MOSFETs and size reduction of the output filter, the ultilevel converters have been applied in low-voltage applications, such as uninterrupted power supplies (USs) and power converters for photo voltaic cells (Vs) [6]. In order to achieve high efficiency when ultilevel converter is concerned, this factor need to be considered seriously, i.e., the suitable circuit topologies selection and the nuber of output voltage level. Although there are any topologies for ultilevel converters, however in general, this converter can be categorized into separated two topologies, which are the diode clap (DCLM) topology and the flying capacitor (FC) topology [], []. Besides that, these two topologies have shared the sae wavefors at the sae levels. Thus, it is difficult to select the circuit topology in the ultilevel topologies. In addition, the nuber of the voltage levels of ultilevel converter is decided depending on the application. Nubers of studies have deonstrated the power losses of a ultilevel converter in ters of nuber of the output voltage level [7], [8]. Those studies analyzed the power losses of the ultilevel converters using atheatical expression. This ethod calculates the power loss depending on the device paraeters and the circuit structure only. Thus, it is possible to design the ultilevel converters depending on the application in ters of soe paraeters such as efficiency, volue, cooling perforance, cost, reliability and so on. However, previous studies did not evaluate and copare power losses of the ultilevel converter topologies in ters of nuber of the output voltage levels. This paper presents several nubers of loss calculation ethods with regard to the type of the ultilevel converters, and regardless of the nuber of level. In addition, the power losses of the ultilevel converters are discussed using two kinds of the power devices which are MOSFET and IGBT. Thus, the best topology and output voltage level of the ultilevel converter can be selected based on its application. First, the loss calculation ethods of the FC topology and the active neural point clap (ANC) topology are discussed [], [3] because these topologies do not require the voltage balance circuit at DC link capacitor. In addition, the power losses of the two ultilevel topologies using two power devices are discussed. The power losses of the two ultilevel topologies using MOSFETs fro threelevel to eleven-level of output voltage levels are calculated based on the atheatical expression. On the other hand, the power losses of the two ultilevel topologies using IGBTs fro two-level to five-level of output voltage levels are calculated. In addition, power losses of the conventional two-level inverter and the diode clap (DCLM) topology are also discussed with siulation results in the case of IGBT. Finally, power loss characteristics are copared in ters of the nubers of the output voltage level. Fro the point of efficiency, in the case of MOSFET, the ANC topology shows better results than other types of ultilevel converters, regardless of the nuber of level. On the other hand, in

2 the case of IGBT, the two-level converter shows the best result copared to other types of ultilevel converters, regardless of the nuber of level. II. MULTILEVEL CONVERTER TOOLOGY A. Flying capacitor topology Figure shows the single phase generalized FC topology []. The nuber of the flying capacitors and switches in the generalized FC topology increases in proportion to the nuber of levels. Outputs step wavefor of FC topology is su of the voltages of the flying capacitor and DC soothing capacitor. B. Active neutral point clap topology Figure shows the single phase generalized ANC topology. The ANC topology cobines the DC and FC topologies into one converter. Due to switching devices of the ANC topology has two switching frequencies, the ANC topology can be separated into two cells as shown in the Figure. Switching frequency of the Cell switches is the carrier frequency. On the other hand, switching frequency of the Cell switches is sae to the output frequency. Thus, switching loss of the Cell switches is low. In addition, circuit structure of the Cell is siilar to FC topology. Thus, nuber of the flying capacitors in the Cell increases in proportion to the nuber of levels. On the other hand, nuber of the seiconductors in the Cell increases in proportion to the nuber of levels. However, in the Cell, a high voltage rating device can be used instead of any low voltage rating devices. III. CALCULATION METHODS OF THE TWO GENERALIZED MULTILEVEL CONVERTER TOOLOGIES These ultilevel converter topologies are assued to be operated under ideal condition. The power losses are calculated under ideal condition, i.e., no current and voltage ripples in the capacitors. The voltage fluctuation in the flying capacitor occurs only during the switching cycle. In addition, the applied voltage of the switches fluctuates during the switching cycle. However, there are two switches that apply low voltage and high voltage for the sae switching pattern. Thus, the power loss by voltage ripple is counterbalanced. Seiconductor loss is separated into the switch-side loss and the FWD-side loss [6]. The power losses of the switch-side sw and the FWD-side D are sw con _ sw switch nl _ sw,...() D con _ D rec nl _ D,...() where con_sw is the conduction loss of the switch-side, switch is the switching loss, nl_sw is the no-load loss, con_d is the conduction loss of the FWD-side, rec is the recovery loss, and nl_d is the no-load loss of the FWDside. The conduction loss is separated into the switch-side loss and the FWD-side loss. In addition, if the switching Fig.. Single phase generalized flying capacitor converter. Fig.. Single phase generalized active neutral point clap converter. device of the two-level converter is a MOSFET, both the positive and negative currents will flow into the switch side due to low on-resistance. We assue that positive current flows into the switch-side and negative current flows into the FWD-side. The conduction losses of the switch-side and the FWD-side are calculated fro onvoltage of the seiconductor and switch current. Thus, conduction loss of the seiconductor con is β Con π voniswdx,... (3) α v r i i sw λ I sin( θ φ),... (5) on on sw v,... (4)

3 where v on is the on-voltage, i sw is the switch current, α and β are phase angle during current flowing, r on is the on-resistance, v is the on-state voltage when I sinθ equals to approxiately A, λ is the duty ratio coand, θ is the power factor, and φ is the phase angle. Using switching characteristics fro a data sheet, the switching loss and recovery loss are E y dc switch ( eon eoff ) ioutdθ,...(6) n Edc e n π x y rec ( rec ) ioutdθ,...(7) π x where E dc is the input voltage, e on is the turn-on energy per switching fro datasheet, e off is the turn-off energy fro switching at datasheet, I out is the output current, f c is the carrier frequency, n is output voltage level, x and y are the phase angles while the current is passed, e rec is the recovery energy per switching fro datasheet. The no-load loss occurs as a result of the parasitic capacitance of switching devices. When an input voltage is applied to the switching devices, the parasitic capacitance of the drain-source of the switching device charges the voltage in the MOSFET. The parasitic capacitance for the IGBT is on the collector-eitter of the switching device. When the voltage of the floating capacitor is discharged, the no-load loss occurs at the on resistance of the switching device. The no-load loss is nloss C pδvsw,...(8) where C p is the parasitic capacitance of the switching device, and ΔV sw is the applied voltage of the switching device. A. ower loss of the generalized FC topology This section explains the power loss expression of the generalized FC topology. The switching pulse pattern of all switches in the FC topology is sae. Thus, seiconductor loss per one switch is sae. The conduction loss FC_con_sw on the switch-side and conduction loss FC_con_FWD on the FWD-side can be,...(9) 8 3π π 8 a cosφ roni a cos φ v I....() 8 3π π 8 FC _ con _ sw a cosφ roni a cosφ vi FC _ con _ FWD Therefore, the switching loss depends on the current flows through the switches and the nuber of switches. The switching loss FC_sw is EdcI FC _ sw ( e ) ( ) on e off f c.... () n π EdcdId In addition, the recovery loss FC_rec is E I dc FC_ rec err ( )...() n π EdcdId Finally, the no-load loss FC_nl is E f dc c FC_ nl Cp...(3) ( n ) Thus, total seiconductor loss per one switch in the n- level FC topology is FC _ Loss _ sei ( n )( FC _ con _ Sw FC _ con _ FWD FC _ switch FC _ rec FC _ nl )....(4) B. ower loss of the generalized ANC topology This section explains the power loss expression of the generalized ANC topology (Figure ). The conduction loss ANC_con_Cell_sw on the switch side can be ANC _ con_ Cell_ sw 4 sinφ φ acosφ roni π 4 3 π a cosφ v I.... (5) On the other hand, the conduction loss ANC_con_Cell_FWD on the switch side is ANC _ con _ Cell 4 π _ FWD sin φ φ acosφ roni π 4 3 π a cosφ v I.... (6) The conduction loss in Cell is obtained by the sae forula that is used to calculate the conduction loss in Cell. However, the current that flows into the Cell switches is different fro the current that flows into the Cell switches because S n and S n are turned on when the output voltage coand is positive and S n and S n3 are turned on when the output voltage coand is negative. Therefore, the conduction loss ANC_con_Cell_swA for the switch side of S n and S n3 is a ANC _ con _ Cell _ swa cosφ cosφ roni π (7) ( sinφ ( π φ ) cosφ ) vi The conduction loss ANC_con_Cell_FWDA for the FWD side of S n and S n3 is 4 a φ 8sin ron I 3( sin φ φ cosφ ) v I π ANC _ con _ Cell _ FWDA... (8) Likewise, the conduction loss for the switch side of S n and S n is ANC _ con _ Cell _ swb π φ sin φ a cosφ cosφ roni π π ( cosφ ) a cosφ sinφ φ cosφ v I,...(9) and the conduction loss for the FWD side of S n and S n is φ ANC _ con _ Cell _ FWDB sin φ a cos φ cosφ roni π cosφ a( sinφ φ cosφ ) vi...() Thus, the switching loss of the switches in Cell is proportional to the applied voltage and current. Therefore, the switching loss of Cell depends on the current flows through the switches and the nubers of switch. The Cell switching loss ANC_switching_Cell is EdcI ANC_ switching_ Cell ( e ) ( ) on e off f c...() n π EdcdI d The recovery loss ANC_rec_Cell is E I dc 5 A_ rec_ Cell err ( n π )....() EdcdI d The switching loss in Cell depends on the output frequency (5 Hz).As a result, the switching loss in Cell.

4 is lower than that in Cell, which is approxiately zero, and therefore can be ignored. No-load loss in the Cell ANC_nl_Cell is calculated by E dc ANC_ nl _ Cell Cp ( n )...(3) On the other hand, the no-load loss in Cell is also approxiately zero, and therefore can be ignored based on the switching loss in the Cell. Thus, total seiconductor loss per one switch in the n- level FC topology is ( n 3) ANC _ Loss _ sei ( ANC _ con_ sw _ Cell ANC _ con _ FWD _ Cell ANC _ switch _ Cell ANC _ rec _ Cell ANC _ nl _ Cell ) ( n ). ( ANC _ con _ sw _ CellA ANC _ con _ FWD _ CellA ANC _ con _ sw _ CellB ANC _ con_ FWD_ CellB )...(4) C. Experiental verification Table shows the converter specifications and device paraeters. This section discusses the validity of atheatically calculated losses based on the experiental results. Thus, the three-level FC inverter and the five-level ANC inverter are designed based on converter specifications and device paraeters. Figure 3 shows the experiental wavefors of the prototypes of the single-phase three-level FC inverter and the single-phase five-level ANC inverter for a 3.3 kw load. Both inverters show a perfect sinusoidal wavefor without distortion of the output current, respectively. In addition, a three-step wavefor of the output voltages of the three-level FC inverter is shown, Figure 3 (a). On the other hand, a five-step wavefor of the output voltages of the five-level ANC inverter is shown as well, Figure 3 (b). Figure 4 shows the no-load loss coparison between the calculation and siulation results of the both ultilevel inverters. Note that the paraetric capacitance of the MOSFET is easured by LCR eter (5 V, khz). Both, the calculation results of no-load loss and the experiental results show a good agreeent. In addition, the error ratio is under. %. Figure 5 shows the power loss coparison between the calculation results and experiental results of the both inverters. Both, the calculation results and the experiental results show a good agreeent. In addition, the error ratio is under 6 %. The validity of the loss TABLE SECIFICATION (a) Three-level FC topology. (b) Five-level ANC topology. Fig. 3. Experiental wavefors. Fig. 4. No-load loss coparison. Fig. 5. ower loss coparison.

5 calculation ethod for the both generalized ultilevel inverters is confired by the experiental results. The power loss coparison results as shown in Figure 5 include the wire resistance, equivalent series resistance (ESR) of the flying capacitor, and ESR of the DC soothing capacitor. The easureent results of those paraeters are as follow, 3.5 Ω (wire resistance of the three-level FC), 4.9 Ω (wire resistance of the fivelevel ANC),. Ω (ESR of the flying capacitor), and 9.8 Ω (ESR of the DC soothing capacitor). IV. OWER LOSS EVALUATION IN TERMS OF THE NUMBER OF LEVELS This section discusses the power loss in ters of the nuber of levels using two kinds of the power devices, which are MOSFET and IGBT. First, in the case of MOSFET, the power losses fro three-level to elevenlevel are calculated based on the atheatical expression. On the other hand, in the case of IGBT, the power losses fro two-level to five-level are calculated siilar to the case of MOSFET. A. MOSFET Figure 6 shows the scatter plot of the on-resistance and the breakdown voltage of the MOSFET. The MOSFETs are selected fro five different seiconductor anufactures which are Infineon, IR, IXYS, Renesas, and TOSHIBA. The criterions of selecting devices are the range of breakdown voltage fro 6 V to 3 V and the range of continuous drain current fro 5 A to A. In Figure 6, we assue that the on-resistance of the MOSFET increases in proportional to the breakdown voltage of the MOSFET. Thus, a line in the Figure 6 is calculated by approxiate expression based on the hypothesis situation. In addition, power losses of the both ultilevel converters the range of the nuber of levels fro three-level to eleven-level are calculated based on the line. Note that the -kw application of three-phase inverter for V is considered. On the other hand, ANC topology is considered for two conditions. First condition is Cell devices of the ANC topology use highvoltage rating devices. Second condition is Cell devices of the ANC topology use the sae devices rating of the Cell devices. Figure 7 shows the power loss characteristics of the ultilevel converters that are structured fro three-level to eleven-level. Fro Figure 7 (a), the conduction loss of ANC topology is the sae to the conduction loss of FC topology. On the other hand, the switching loss of the ANC topology is half of the switching loss of the FC topology in the Figure 7 (b). Thus, the power loss of the ANC topology is lower than the power loss of the FC topology in the Figure 7 (c). Table shows the relationship between nuber of switch per one switching state and total on-voltage. ower loss of the ultilevel inverter decreases in inverse proportion to the nuber of level. The condition that Fig.6. Scatter plot of on-resistance and breakdown voltage of MOSFET. (a) Conduction loss (b) Switching loss (c) Total loss Fig.7. ower loss characteristics of ultilevel converters. [p.u.] of the figure 7 (a) is noralized value by total conduction loss of the three-level ANC topology. On the other hand, [p.u.] of the figure 7 (b) are noralized by total switching loss of the three-level ANC topology. Finally, [p.u.] of the seiconductor losses of figure 7 (c) are noralized value by total loss of the three-level ANC topology. Cell devices of the ANC topology use high-voltage rating devices. Cell devices of the ANC topology use sae rating devices of the Cell devices.

6 TABLE RELATIONSHI BETWEEN LEVEL AND NUMBER OF SWITCH AND TOTAL ON-RESISTANCE Selection critea Breakdown voltage : 6V-8V Continuous drain current: 55A-8A Device product : ABB, Fuji electric. Infeneon, IR, MITSUBISHI, Renesas power loss decreases in inverse proportion to the nuber of level is discussed based on Figures 6 and 7. Multilevel converter increases the nuber of seiconductor device per on switching state in proportion to the nuber of level in the table. Thus, if the total resistance of seiconductor per on switching state of n-level inverter is lower than the total resistance of the (n-)-level inverter, the n-level inverter can achieve low seiconductor loss. The condition that power loss decreases in inverse proportion to the nuber of level is von _ nl < von _ l ( n ),...() Where v on_nl is on-voltage of seiconductor of n-level inverter, v on_l is on-voltage of seiconductor of -level inverter. For exaple, the level of inverter is assued to change fro three-level to five-level. If the total onresistance of the five-level inverter is achieved by referring equation (), the power loss of the five-level inverter is reduced. On the other hand, if the five-level inverter is not achieved by referring equation (), the power loss of the five-level inverter is larger than the three-level inverter. Thus, it is not effective to change the level fro three-level to five-level. However, the power loss of three-level inverter can be reduced if low onresistance MOSFET which is lower than existing MOSFET. Note that the level of inverter is held the sae level. Thus, the power loss of three-level inverter can be reduced. B. IGBT Figure 8 shows the scatter plot of the on-voltage and the breakdown voltage of the IGBT device. The IGBTs are selected fro five different seiconductor anufactures which are ABB, Fuji electric, Infineon, IR, MITUBISHI, and Renesas. The criterions of selecting devices are the range of breakdown voltage fro 6 V to 8 V and the range of continuous drain current fro 55 A to 8 A. In Figure 8, we assue that the onvoltage of the IGBT increases in proportion to the breakdown voltage of the IGBT. Thus, a line in the Figure 8 is calculated by approxiate expression based on the hypothesis situation. In addition, this section discusses the power loss aong four topologies which are ANC topology, FC topology, DCLM topology, and conventional two-level topology. It is because the 5 5 Breakdown Volltage of device [V] Fig.8. Scatter plot of on-voltage and breakdown voltage of MOSFET. Conduction loss [p.u.] (a) Conduction loss Two-level topology ANC topology ANC topology FC topology DCLM topology Specification Rated power : 5 kw Input voltage : 55 V Output voltage : 3 V Output current : 48 A Output frequency : 5 Hz Carrier frequency : khz Nuber of level (b) Switching loss (c) Total loss Fig.9. ower loss characteristics of ultilevel converters. [p.u.] of the figure 9 (a) is noralized value by total conduction loss of the two-level topology. On the other hand, [p.u.] of the figure 9 (b) are noralized by total switching loss of the two-level topology. Finally, [p.u.] of the seiconductor losses of figure 9 (c) are noralized value by total loss of the two-level ANC topology. Cell devices of the ANC topology use high-voltage rating devices. Cell devices of the ANC topology use sae rating devices of the Cell devices.

7 conventional two-level topology and the DCLM topology are applied in ediu-voltage application. The power losses of four ultilevel converters, the range of the nuber of levels fro two-level to five-level are calculated based on the line. Note that the application of four topologies is 5-kW three-phase inverter for V. In addition, the two-level topology is calculated by atheatical expression [8]. On the other hand, DCLM topology is calculated by siulation software (SIM). Figure 9 shows the power loss characteristics of ultilevel converters that are structured fro two-level to five-level. Fro Figure 9 (a), the conduction loss of the two-level inverter is the lowest than other topologies. On the other hand, the conduction loss of ANC topology is the sae to the conduction loss of FC topology. Fro Figure 9 (b), the switching loss of the five- level DLMC inverter is the lowest than other topologies. Fro Figure 9 (d), the power loss of the two-level inverter is lower than other topologies. ower loss of the ultilevel inverter increases in proportion to the nuber of level. This result is different in the case of MOSFET. It is because there is little change in on-voltage of the IGBT which is the range of breakdown voltage fro 6 V to 8 V. It is difficult to achieve the criteria of selecting devices by equation (). Thus, in case of the IGBT, it is not effective for power converter in ediu-voltage application to increase the nuber of levels in ters of the power loss. V Inverter Topologies Derived Fro NC Topology, EE 9-Barcelona,pp.-, 9 [7] M. Kaaga, Y. Sato, K. Sung, H. ohashi: An investigation of power device loss in ultilevel converters, EDD-8-73, SC-8-6, 8. [8] Yugo kashihara, Jun-ichi Itoh, The perforance of the ultilevel converter topologies for V inverter, International Conference on Integrated ower Electronics Systes, Nureberg, Gerany,. [9] J. W. Kolar, J Biela and J, Minibock: Exploring the areto Front of Multi Objectice Single-hase FC Rectifier Design Optiization -99.% Efficiency vs. 7kW/d 3 ower Density, IEMC 9-China,9. V. CONCLUSION This paper discussed power losses of two ultilevel topologies in ters of nubers of the output voltage level using two power devices. In case of the MOSFET, power loss of the ultilevel inverter decreases in inverse proportion to the nuber of level. In addition, the ANC topology is better results coparing to the FC topology, regardless of the nuber of level. On the other hand in case of the IGBT, power loss of the ultilevel inverter increases in proportion to the nuber of level. The twolevel converter shows the best result copared to other types of ultilevel converters, regardless of the nuber of level. REFERENCES [] F. Z. eng : A Generalized Multilevel Inverter Topology with Self Voltage Balancing, IEEE Transactions on industry applications, Vol.37, No., pp. 4-3, [] A. Nabae, I. Takahashi, H. Akagi, A new neutral-point-claped WM inverter, IEEE Trans.Industry Applications, Vol.IA-7, pp.58-53, 98. [3] Barbosa,.; Steier,.; Steinke, J.; Meysenc, L.; Winkelnkeper, M.; Celanovic, N: Active Neutral-point- Claped Multilevel Converter, ower Electronics Specialists Conference, 5. ESC '5. IEEE 36th 6-6 June 5 age(s):96 3, 5. [4] Gateau, G., Meynard, T.A., Foch, H.: Stacked ultilcell converter (SMC) : properties and design, ower Electronics Specialists Conference, IEEE 3nd Annual,. [5] ABB RESEARCH LTD. : A [6] Lin Ma, Taas Kerekes, Reus Teodorescu, Xinin Jin, Dan Floricau, Marco Liserre: The High Efficiency Transforer-less