Design and Implementation of a 125kW T-NPC PV Inverter

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1 CIM Asia 015, 4 6 June 015, Shanghai, China Design and Implementation of a 15kW T-C V Inverter Yuelin, Wu, ational Active Distribution etwork Technology Research Center (Beijing Jiaotong University), Beijing, China, @bjtu.edu.cn Guohong, Zeng, ational Active Distribution etwork Technology Research Center (Beijing Jiaotong University), Beijing, China, ghzeng@bjtu.edu.cn Jingdou, Liu, ational Active Distribution etwork Technology Research Center (Beijing Jiaotong University), Beijing, China, jdliu@bjtu.edu.cn Gaosheng, Song, MITSUBISHI ELECTRIC&ELECTRICS (SHAGHAI) C., LTD., Shanghai, China, SongGS@mesh.china.meap.com Jian, Sun, MITSUBISHI ELECTRIC&ELECTRICS (SHAGHAI) C., LTD., Shanghai, China, SunJian@mesh.china.meap.com Abstract This paper presents a design method and its implementation of V inverter, in which the T- type C three-level (T-C) topology is adopted, to achieve the benefits of low voltage stress, low switching losses, low harmonic distortion and high conversion efficiency. The design procedure is presented in detail, including power losses calculation, efficiency analysis, power stack designing, filter designing. The effectiveness of the proposed V inverter and its design method is validated by experimental results. 1. Introduction Driven by the increasing environmental concerns, photovoltaic (V) power generation systems are attracting the market and research interest. V grid-connected inverters, acting as the interface between the grid and V power system, have been studied widely. Although two-level inverter is commonly adopted, three-level topology is found to be more suitable for distributed V generation systems. As one of the most typical three-level inverter, neutralpoint-clamped (C) inverter, has been researched in many literatures [1-], with the advantage of low device voltage stress, superior output voltage quality, low switching losses and low du/dt. To simplified the control algorithm and reduce the number of devices, topology of T-type three-level neutral-point-clamped converter (T-C) is derived [3], as shown in Fig.1. +Udc/ L1 L Ua Ub Grid Uc Cf -Udc/ Fig. 1. Topology of T-C V inverter Fig.. Single-phase of T-C topology Compare to that in C, each bridge leg in T-C reduces two diodes as shown in Fig., so lower conduction losses can be achieved and the operation algorithm can be simplified, while the other advantages of C are kept. Considering the lower DC link voltage available in distributed V generation systems, T-C grid-connected V inverter is more exceptive in efficiency and cost comparing to C inverters. VDE VERLAG GMBH Berlin ffenbach, Germany ISB

2 CIM Asia 015, 4 6 June 015, Shanghai, China This paper attempts to give the power losses calculation method and design procedure of T- C V inverter with high efficiency for power and space. To verify the effectiveness and reliability of T-C inverter, temperature rise experiment has been performed.. Efficiency analysis This section explains the operation principle of T-C and gives the calculation method of power losses to design dissipation system. Based on the method, a calculation example is given to show the high efficiency of T-C..1. peration principle of T-C The single-phase of T-C V inverter is shown in Fig., in which ~ are IGBT switches, ~ are FWDs, and are DC link capacitors. Assume that the direction of current flowing out from bridge leg is positive. Generally, the output terminal of the bridge leg can be connected to positive (), neutral (), or negative () side of DC link, and the output voltage can be set to three values, as shown in Table 1. peration mode utput voltage FF FF +Udc/ FF FF 0 FF FF -Udc/ Table. 1. Switching operation modes of IGBT The driving signals of and are complemented to and respectively, and cannot be turned on simultaneously. To illustrate the working process and control principle of T-C, the switch commutation procedure is analyzed in detail. Six current commutation diagrams are deduced, as shown in Fig.3, and can be described as follow. (1)Mode, Uo=Udc/,IL>0 ()Mode, Uo=0,IL>0 (3)Mode, Uo=-Udc/,IL>0 (4)Mode, Uo=Udc/,IL<0 (5)Mode, Uo=0,IL<0 (6)Mode, Uo=-Udc/,IL<0 Fig. 3. Current commutations of T-C topology VDE VERLAG GMBH Berlin ffenbach, Germany ISB

3 CIM Asia 015, 4 6 June 015, Shanghai, China (1) The direction of output current is positive, and are turned on, and are turned off, current commutates over and the output voltage Uo=Ud/. () The direction of output current is positive, and are turned on, and are turned off, current commutates over and and the output voltage Uo=0. (3) The direction of output current is positive, and are turned on, and are turned off, current commutates over and the output voltage Uo=-Ud/. (4) The direction of output current is negative, and are turned on, and are turned off, current commutates over and the output voltage Uo=Ud/. (5) The direction of output current is negative, and are turned on, and are turned off, current commutates over and and the output voltage Uo=0. (6) The direction of output current is negative, and are turned on, and are turned off, current commutates over and the output voltage Uo=-Ud/. From the six operating mode, it can be deduced that the operation algorithm can be simplified compared with C... ower losses Calculation To design the inverter efficiently and to handle the power dissipation effectively, power losses of each device should be estimated precisely. The losses of each power device is consisted of conduction losses, and switching losses sw. Conduction losses Two factors need to be considered in calculating conduction losses. ne is the conduction time in a modulation period, and the other is the conduction current. During one modulation period, assume only one transition of -- or -- is permitted. Conduction voltage drop and instantaneous conduction power can be described as: VT VT 0 it rt (1) V i i r () on T 0 T T T Where r T, V T0, V T and i T are conduction internal resistance, initial saturation voltage, conduction voltage drop, conduction current, respectively. The energy losses of power devices in one carrier cycle can be calculated with: E V i DT [ V + I sin( t) r ] I sin( t) DT T T L c T 0 m T m c Where T c is period of carrier wave, D is duty ratio, a function of modulation ratio M and power factor angle θ. I m sinωt is load current and I m is the peak current. Then the average conduction losses in one modulation period can be calculated with: 1 1 E d t [ V 0+ Im sin( t) r ] Im sin( t) Dd t T T T 1 0 T T Where T 0 =π, [θ 1 ~θ ] is the conduction time interval. Switching losses The switching losses of power devices are proportional to current and DC voltage. Turn-on energy losses E on.nor, turn-off energy losses E off.nor of IGBT and reverse recovery energy E rr.nor of FWD in normal working condition are shown in the datasheet, they should be converted in actual working condition according to U dc and I on, I off, I rr, which mean DC link voltage, turn-on current, turn-off current of IGBT, reverse recovery current of FWD. The switching frequency is f s, the switching power losses in one modulation period can be calculated with: I U sw on E dt T T I U 1 1 on dc on. nor 1 c 0 nor dcnor (3) (4) (5) VDE VERLAG GMBH Berlin ffenbach, Germany ISB

4 CIM Asia 015, 4 6 June 015, Shanghai, China I U sw off E dt T T I U 1 1 off dc off. nor 1 c 0 nor dcnor I U sw rr E dt T T I U 1 1 rr dc rr. nor 1 c 0 nor dcnor Where sw-on, sw-off and sw-rr are IGBT turn-on losses, IGBT turn-off losses, FWD reverse recovery losses, respectively. I nor and U dcnor are output current and DC voltage in normal working condition..3. Efficiency Calculation Example In this paper, MITSUBISHI 4in1 module CM400ST-4S1 is adopted in T-C V inverter to design with high efficiency for power and space, 100V chip for half bridge (/ and /), 650V chip for AC SW (/ and /). Test condition is shown as Table. Modulation SWM ower factor 0.9 DC voltage 850V Gate resistance 1.5Ω Switching frequency 8kHz Modulation ratio Heat sink temperature 95 Fundamental frequency 50Hz Table.. Test condition for efficiency calculation The power losses calculation results of T-C according to equation (1) ~ (7) are shown in Table 3. Device Io(A)-rms -T (W) sw-t (W) _sum(w) _total(w) Efficiency / / A / % / Table. 3. Calculation results of T-C Based on the calculation results of power losses above, suitable fan and heat sink can be chosen as dissipation system. (6) (7) 3. Design of T-C inverter ower stack is one of the important devices in a V inverter which have great impact on stability and reliability. This section designs a modular power stack consisting of power device, DC link capacitor and current sensor etc. As another important element in a V inverter, LCL filter designing procedure is also presented in this section Design of T-C power stack Fig.4 shows the schematic diagram of T-C power stack, filtering the DC voltage through DC link capacitor, feeding the DC power to IGBT modules, converting the DC power into AC power which can regulate the voltage amplitude and frequency by control the switching devices in T-C inverter. It has the functions of over-voltage protection, over-current protection, over-heat protection, short circuit protection and fault locking. VDE VERLAG GMBH Berlin ffenbach, Germany ISB

5 CIM Asia 015, 4 6 June 015, Shanghai, China DC+ 0 DC- Heat sink AC AC AC Drive board-a Drive board-b Drive board-c C C C AC.out.U AC.out.V AC.out.W Drive signal A Drive signal B Drive signal C Fig. 4. Schematic diagram of T-C power stack To reduce system volume and stray parameters, it integrate the power devices, cooling system and sensors into a high power density stack as shown in Fig.5 and Table umber Device 1 Fan DC link laminated busbar 3 DC link capacitor 4 ower device CM400ST-S1 5 Current sensor 6 Drive board Fig. 5. The figure of power stack Table. 4. Devices in the power stack 3.. Design of LCL filter LCL filter is preferred to L filter because its switching harmonic attenuation with smaller reactive element is more effective. Thus the cost and the weight of the inverters are reduced. So LCL filter is adopted in this paper. The design of the filter is mainly based on the harmonic voltage. Harmonic current is generated by harmonic voltage and inverter-side inductor, the output current is the one which passes through from filter capacitor and grid-side inductor. The choice of filter elements is a tradeoff considering switching harmonics attenuation, reactive power consumption, relative short-circuit voltage drop, grid decoupling, filter losses, and the costs and sizes of filter elements. The equivalent circuit of inverter with LCL-filter is shown in Fig.6. VDE VERLAG GMBH Berlin ffenbach, Germany ISB

6 CIM Asia 015, 4 6 June 015, Shanghai, China i g L g L e C u Fig. 6. Equivalent circuit of inverter with LCL-filter Where e, u, L g, L, C are grid voltage, inverter output voltage, grid-side inductor, inverter-side inductor, filter capacitor, respectively. Filter capacitor C needs to be satisfied with: C (8) 3 fe 1 m Where, E m, f 1, λ are rated power of inverter, RMS phase voltage of grid, fundamental frequency of grid, the ratio of the fundamental reactive power absorbed by filter capacitor C to rated power of inverter, respectively. The resonance frequency f res of inverter should satisfied with equation (9) as followed to avoiding resonance peak emerges at too low frequency and too high frequency band. 10 f1 fres 0.5 f (9) sw The f sw is switching frequency. The range of resonance frequency can be further reduced as: 1kHz f res khz (10) Based on engineering experience, 1450Hz can be chosen as resonance frequency. According to equation (11) as follow: 1 Lg LC f (11) res Lg L Take cost and volume into consideration, LCL-filter parameters C=180uF, L=190uH, L g =100uH are chosen in this paper. 4. Experimental method and results The parameters of the T-C V inverter are shown in Table 5. arameter Rated capacity Rated output voltage Rated output current Rang of output frequency ower factor Value and unit 139kVA(15kW, F=0.9) 315Vrms 55Arms 47.5~51.5Hz 0.9ind~0.9cap DC link voltage 480~850V DC link capacitor Switching frequency ower module Table.5. arameters of T-C V inverter 1300uF 8~10kHz 100V/600V/400A To verify the stability and reliability of T-C power stack, H-bridge circuit is composed of two T-type bridges connected an inductor load (L=640uH) shown in Fig.7. utput voltages of the two bridges are U1 and U (AC-). Voltage difference ΔU can be adjusted by changing the phase angle θ of U1 and U, so rated output power can be achieved. Fig.8 shows phasor diagram of H-bridge circuit, it can work in both inverter operation and rectifier operation. VDE VERLAG GMBH Berlin ffenbach, Germany ISB

7 CIM Asia 015, 4 6 June 015, Shanghai, China D5 T5 U1 L U + ΔU - D8 T8 D7 T7 D6 T6 ΔU U θ I U1 (a) Inverter operation I θ ΔU U (b) Rectifier operation U1 Fig.7. H-bridge circuit for testing T-C Fig.8. hasor diagram of H-bridge circuit Fig.9 shows the waveforms in inverter operation (a) and rectifier operation (b). (a) (b) Fig.9. Experimental waveforms of inverter operation and rectifier operation Where CH1 is DC link ripple current (100A/div), CH is U1 (500V/div), CH3 is ΔU (500V/div), CH4 is load current I (00A/div). After about 1 hour, the temperature of some main components in the power stack have been measured, results are shown in Table 6. Component Initial temperature( ) Final temperature( ) Inverter operation Rectifier operation Temperature rise( ) Inverter operation Rectifier operation DC link capacitor DC laminated busbar AC output busbar Table. 6. Results of temperature rise experiment The experimental results indicate that the T-C V inverter can meet the working requirements and reach the industry standard of Technical Specification of Grid-connected V inverter (B/T ). 5. Conclusion A T-C V inverter has been presented in this paper. Calculation method of power losses and design procedure of power stack and LCL filter are expressed. Because of the high power density power stack, the V inverter can achieve more efficiency, less space and less stray parameters. Experimental results proved the effectiveness and reliability. VDE VERLAG GMBH Berlin ffenbach, Germany ISB

8 CIM Asia 015, 4 6 June 015, Shanghai, China 6. References [1] J. Rodriguez, S. Bernet,. K. Steimer, and I. E. Lizama, A Survey on eutral-oint- Clamped Inverters, IEEE Transactions on Industrial Electronics, vol. 57, pp , 010. [] A. Yazdani and R. Iravani, A eutral-oint Clamped Converter System for Direct-Drive Variable-Speed Wind ower Unit, IEEE Transactions on Energy Conversion, vol. 1, pp , 006. [3] Schweizer, M., Lizama, I., Friedli, T., & Kolar, J. W. (010, ovember). Comparison of the chip area usage of -level and 3-level voltage source converter topologies. In IEC th Annual Conference on IEEE Industrial Electronics Society (pp ). IEEE. [4] Liu Fei, Zha Xiaoming, & Duan Shanxu. (010). Design and Research on arameter of LCL Filter in Three-hase Grid-Connected Inverter [J]. Transactions of China Electrotechnical Society, 5(3), [5] DU Yi & LIA Meiying. (011), Losses calculation of IGBT module and heat dissipation system design of inverters [J]. ELECTRIC DRIVE AUTMATI, 33(1), [6] LI Youmin, TG Yibin, WU Xuezhi &YA Xiuyuan. (013). 65kW TC Three-level Grid-connected Inverter Design [J]. ower Electronics, 47(1), [7] CM400ST-4S1 datasheet, MITSUBISHI ELECTRIC. VDE VERLAG GMBH Berlin ffenbach, Germany ISB