10kW Three-phase SiC PFC Rectifier

Transcription

1 10kW Three-phase SiC PFC Rectifier SEMICON EUROPA, Nov 13-18, 2018, Munich, Germany

2 Contents General PFC Concept 3 Phase System and PFC Control Simulation Understanding the losses 3 Phase PFC Implementation Results 2 2/2/2018

3 General PFC Concept 3 2/2/2018

4 Definition of Power Factor φ 1 Real Power (W) V I Reactive Power (VAR) PF Real Power (W) Apparent Power (VA) I V POWER FACTOR V P RMS avg I RMS I I V I 1, RMS RMS cos 1 DISPLACEMENT FACTOR DISTORTION FACTOR cos( 1 ) DISTORTION FACTOR = DISPLACEMENT DISPLAC. FACTOR FACTOR = 0.96 = 1 PF = DIODE PFC TARGET BRIDGE DISTORTION FACTOR = 1 DISPLACEMENT FACTOR < 1 PF < 1 DISTORTION FACTOR < 1 DISPLACEMENT FACTOR = 1 PF < 1

5 3 Phase System and PFC Control 5 2/2/2018

6 3-phase PFC: Selected Topology Power Flow 3 Half Bridges. Each half bridge connected to a input phase voltage. Input voltages form a unique system. The 3-phase PFC control concept works as an inverter for motor application. Only the control strategy changes. This configuration would allow to control the reactive power because of Q axis availability.

7 3 Phase PFC: Voltage Relationship, ABC Model N σ i=a,b,c E im =0 E V LA AN V N0 d 1 d 2 d 3 A V A0 B C V DC 0 SYSTEM VOLTAGE EQUATIONS IN ABC DOMAIN v v v L, A L, B L, C e e e AN BN CN u u u N 0 N 0 N 0 V V V A0 B0 C0 dia L R i S S A dt dib L R i S S B dt dic L R i S S C dt Goal of the PFC is to control the voltage across the inductors. SUPPLY VOLTAGE E AM = തE cos(ωt) E BM = തE cos(ωt 2 3 π) E CM = തE cos(ωt 4 3 π) TIME E A (t 1 ) E B (t 1 ) E C (t 1 ) B C E A,(t1) E S E C,(t1) E B,(t1) A VECTOR SPACE

8 Bus Voltage Limitation and Driving Capability SAH SBH SCH V DC When the switches are modulating, the following vectors can be provided in the vector space domain. E S,MAX = 0.57 V DC SAL SBL SCL VOLTAGE SOURCE INVERTER When FETs are left OPEN, the HW is operating as a diode bridge because of the FWD. The target DC BUS voltage has to be higher than the line to line voltage amplitude: V DC = 6E RMS,PHASE

9 System Reference: From 3φ Stationary To 2φ Rotating GEOMETRIC TIME B B β D β E B,(t1) E S E C,(t1) E A,(t1) A E S φ A α Φ = 0 E S θ α C CLARKE C PARK (αβ) = [T 0 ] (ABC) (DQ) = [T θ S ] (αβ) Q EAM EBM ECM Eα Eβ ED EQ ϑ [rad] -400 ϑ [rad] ϑ [rad]

10 3 Phase PFC: (DQ) Model di e L D S dt diq e L Q S dt dudc C dt D R R i D S S s i i D D Q L i L ELECTRICAL QUANTITIES ON DQ DOMAIN ARE CONSTANT VALUES Q s Q S S i i Q D V V u R DC L D Q Input quantities are transformed by means of Clarke/Park matrix. E D E Q are the supply voltages expressed in the DQ domain. i D, i Q are the phase currents in the DQ domain. ω is the fundamental frequency of the input voltage. V D and V Q are the voltage generated by the control in the DQ domain that will be used for the PWM generation. 10 2/2/2018

11 3 Phase PFC Control Scheme on DQ Domain SPECIFICATION Input voltage: 230V RMS 3-Phase voltage, 50Hz. Output Voltage: 700V 3 MODULATION STRATEGIES TESTED Switching Frequency: 70kHz Control Frequency: 20kHz Source Inductance: 300uH Output capacitance: 470uF CONTROL ALGORITHM FIXED DURING TEST CONDITIONS DQ SYSTEM MAKES PI REGULATION POSSIBLE! Ref. Fig Control in power electronics Author. M.P. Kazmierkowski et al. 2002

12 3 Phase PFC: Applied Modulation Strategies PWM Adaptive Modulator A modification into the zero sequence voltage doesn t affect the voltage applied to the inverter phases, however it will affect noise between DC output and PE. An impact on the input filter should be expected, even if in this presentation EMI FILTER was not considered. 12 2/2/2018

13 Simulations 13 2/2/2018

14 3 Phase PFC Simulink Model, Behavioral PARAMETERS F CLK = 84 Mhz 70kh pwm freq F PWM = 70 Khz F CNTR = 20 Khz ADC & PWM Peripherals DEAD TIME = 1.1% HARDWARE L S = 300 uh R S = 0,04 Ohm R HL = 72 Ohm ANALOG INPUTS Control Strategy (C-code) PWM OUTPUT R FL = 36 Ohm

15 3 Phase PFC SPICE Model, Quantitative CONTROL STRATEGY POWER STAGE SENSING INPUTS THE PARAMETERS SELECTED FOR RUNNING SPICE SIMULATION WERE ALIGNED WITH THE SIMULINK ONES.

16 Understanding the Losses 16 2/2/2018

17 Choke Inductor Losses (simplified) 700V P L,CORE = k f a Bc PK I X V LX L X X E XN (t) k, a and c are core material dependent. N f is the high switching frequency B PK is half the flux density ripple calculated considering the current ripple introduced by the inductance selected B PK = μ 0 μ R N I. 2 P L,JOULE = R W I 2 RMS Where R W is the winding resistance. I RMS is the circulating current for a certain power level with a known input voltage. 0 V X0

18 FETs Losses in Space Vector Modulation (1/2) t DT ia d A M D1 M1 D1 M2 ib ic d B D M3 D4 M1 M3 M d C D6 M5 D6 d A d B d C T PWM ia ib ic d' A A M2 d' B B M4 d' C C M6 HARD ON OFF HARD OFF ON SOFT ON - OFF SOFT OFF ON LEG A M2 - [1] M2 - [4] M1 - [3] M1 - [2] LEG B M3 [3] M3 [2] M4 [1] M4 [4] LEG C (as B) M5 [3] M4 [2] M6 [1] M4 [4] SWITCHING LOSSES P L,SW f PWM Notes During t DT both switches on each leg are fully OFF. FETs are bidirectional when turned ON and current flows according source and drain voltage potential. va is depending on phase voltage and star voltage when low side FET OFF and current into the node.

19 FETs Losses in Space Vector Modulation (2/2) P SW = 3 E OFF + E ON f PWM Note By designing a different modulation strategy, the number of transitions could be decreased by 33% and together with an appropriate timing based on current amplitude, a switching loss minimization can be achieved Since all the FETs are equal we simplify the calculation with the following formula P J = 3 R DS,ON T I2 RMS

20 3 Phase PFC Implementation 20 2/2/2018

21 3 Phase PFC Power Board Concept (1/2) Note: V BUS,MIN = = 650V 3V3 15V 3V3 15V 3V3 15V 700V 24V PWM EN FAULT ISO-GATE DRIVER PWM EN FAULT ISO-GATE DRIVER PWM EN FAULT ISO-GATE DRIVER vbus va ia CURR SEN. vb ib CURR. SEN. vc ic CURR. SEN. 24V 3V3 15V 3V3 15V 3V3 15V Note Inrush OFF PWM EN FAULT ISO-GATE DRIVER PWM EN FAULT ISO-GATE DRIVER PWM EN FAULT ISO-GATE DRIVER Analog INP Digital

22 3 Phase PFC Power Board Concept (2/2) 390 V DCDC CONVERTER 24V [ ]/24V 3V3 DIGITAL ISOLATOR 5V IN+ IN- XEN REF. GATE DRIVER R SRC R SINK DESAT 15V ISO DCDC 20V SIGNAL CONDITIONING FOR 3V3 uc ISO-GATE DRIVER Note Analog INP Digital

23 3 Phase PFC Power Board SIZE 375 x 240mm TOP VIEW BOTTOM VIEW

24 Results 24 2/2/2018

25 SiC Switching Behavior INPUT VOLT: 230 Vrms OUTPUT POWER: 10kW EFFICIENCY: 97.6% F PWM : 80kHz DC OUT: V DC RIPPLE: 29.4V R G,ON : 22 Ohm R G,OFF : 4.7 Ohm L (Is = 0, F = 1kHz) : 600 uh TURN OFF 65 Vns -1 TURN ON 38 Vns -1

26 METRICS FACTORS Overview of the Experiment INDUCTOR [μh] SWITCH. FREQUENCY [khz] MODULATION [type] DIS1 FBM SVM DIS1 FBM SVM DIS1 FBM SVM DIS1 FBM SVM OUTPUT POWER [kw] [3..10] [3..10] [3..10] [3..10] [3..10] [3..10] [3..10] [3..10] [3..10] [3..10] [3..10] [3..10] TOTAL HARMONIC DISTORTION [THD] EFFICIENCY [η] POWER FACTOR [PF] PHASE DELAY [φ] Ideally 100% Ideally 1" Ideally 0 " Testing conditions Input voltage: 50Hz IEEE STD 519

27 Current 10 kw 70 khz 120 khz DISCONTINOUOS 1 FLAT BOTTOM SPACE VECTOR THD1: 4.7% THD2: 5.8% THD3: 4.4% THD1: 4.9% THD2: 5.6% THD3: 5.0% THD1: 3.7% THD2: 4.2% THD3: 3.7% THD1: 5.1% THD2: 6.5% THD3: 6.2% THD1: 8.1% THD2: 8.3% THD3: 8.0% THD1: 3.6% THD2: 3.5% THD3: 3.0%

28 Efficiency Result Factor with the highest impact is the output power at which the board is working. Efficiency is affected by the modulation strategy selected, a variation in average of 0.5% can be considered which, in turn, affects switching losses. Modulation frequency and inductor selection have a smaller influence on efficiency result. Most likely they are compensating each other. Note Thermal steady state 10kW. Power Supply: Chroma 61511, DC Load: ELR , Power Analyzer: Zimmer LMG500 Oscilloscope: Yokogawa DLM6054.

29 Power Factor & THD

30 Thank you 30 2/2/2018