Preliminary hardware implementation of a six-phase quad-inverter induction motor drive

Transcription

1 Preliinary hardware ipleentation of a six-phase quad-inerter induction otor drie Gabriele Grandi, Padanaban Sanjeeikuar, Doenico Casadei DEPT. OF ELECTRICAL ENGINEERING UNIERSITY OF BOLOGNA iale Risorgiento 2, Bologna, Italy Ph./Fax: /88 <nae.surnae>@unibo.it URL: Keywords Multileel conerters, Multiphase drie, Power conditioning, Conerter control, oltage Source Inerters (SI). Abstract A hardware ipleentation of a quad-inerter configuration for ulti-phase ulti-leel induction otor dries is presented in this paper. The schee is based on four conentional 2-leel three-phase oltage source inerters, able to supply the open-end windings of a dual three-phase otor (asyetric six-phase achine), quadrupling the power capability of a single SI with gien oltage and current ratings. By a proper control algorith the proposed conerter is able to generate ulti-leel oltage waefors, equialent to the ones of a 3-leel inerter, and to share the total otor power aong the four sources within each switching period. A full-scale prototype of the whole power syste has been realized utilizing six balanced ipedances as six-phase load. A coplete set of experiental results is gien with reference to both balanced and unbalanced operating conditions. Introduction Both ulti-phase and ulti-leel inerter technologies hae been widely recognized as a iable solution to oercoe current and oltage liits of power switching conerters for high-power ediuoltage ac dries. In ore details, ulti-phase otor dries hae any adantages oer the traditional three-phase otor dries, such as reducing the aplitude and increasing the frequency of torque pulsations, reducing the rotor haronic current losses and lowering the link current haronics. In addition, owing to their redundant structure, ulti-phase otor dries iproe the syste reliability. As a consequence, the use of ulti-phase inerters together with ulti-phase ac achines has been recognized as a iable approach to obtain high power ratings with current liited deices [1]-[3]. On the other side, ulti-leel conerters are able to generate output oltage waefors consisting in a large nuber of steps. In this way, high oltages can be synthesized using sources and switching deices with lower oltage alues, with the additional benefit of a reduced haronic distortion and lower d/dt in the output oltages. For these reasons, the use of ulti-leel inerters has been recognized as a iable approach to obtain high power ratings with oltage-liited deices [4]-[6]. It becoes eident that the cobination of ulti-phase and ulti-leel inerter technologies [7] could be an effectie ethod to group the benefits of such technologies and to obtain high power ratings with both oltage- and current-liited deices. Seeral conersion structures hae been introduced in last decades for ulti-phase and ulti-leel inerters. Aong these structures, there are topologies based on a proper arrangeent of conentional 2- leel three-phase oltage source inerters (SIs) to realize both ulti-phase [8]-[12] and ulti-leel [13]-[17] inerters, or dual-source fed ultiphase induction otor dries [18]. The great adantages of such topologies are reliable power layout and effectie protecting circuitry, reduced cost of both con-

2 30 {1} {2} L L Fig. 1: Scheatic diagra of the proposed ulti-phase ulti-leel induction otor drie consisting in four oltage source inerters supplying a dual three-phase achine with open-end windings. erter and otor due to conentional slot/winding configurations, and odularity of the whole conersion structure. In order to exploit all these adantages, a noel structure based on a dual three-phase open-ends winding otor (asyetric six-phase induction achine) has been proposed in [19]. In this paper, the hardware ipleentation of this ulti-phase ulti-leel structure is described. The power supply consists of four standard 2-leel three-phase SIs haing insulated sources to preent circulation of zero-sequence current coponents. A scheatic diagra of the whole syste is gien in Fig. 1. Note that the structure is easy scalable to nine, twele, or higher triplen phase nubers. Each couple of 2-leel SIs is odulated to obtain output oltage waefors such as a 3-leel inerter, proiding proper ulti-leel oltage waefors for each three-phase stator winding. The control algorith allows total otor power to be shared aong the four sources with three degrees of freedo. Power sharing is a useful skill in battery supplied dries where the charge status of batteries should be balanced. Dual three-phase induction otor drie Multiple Space ector Representation Multiple space ectors are considered to represent the ariables of the whole six-phase syste consisting of the dual three-phase achine supplied by four insulated three-phase SIs. In particular, the asyetric six-phase space ector transforations introduced in [8], [12] are considered. The relationships between ultiple space ector ariables ( x 1, x 3, x 5 ) and the three-phase space ector ariables ( x, x ) of each three-phase sub-syste {1}, {2} are 1 x x x x x jx 2 * 1 x5 = x α x 2 * x = x1 x 1 * 5 x = α ( x1 x5 ), x0 = x3 1 x0 = x3 j 1 = α, 3 = 0 0,, where the sybols * and denote coplex conjugate and scalar (dot) product, respectiely. The representation of the proposed ulti-phase ulti-leel induction otor drie shown in Fig. 1 in ters of three-phase space ectors leads to the scheatic equialent circuit of Fig. 2. Machine Model by Multiple Space ectors The behaior of the dual three-phase induction achine haing sinusoidal distributed stator windings can be described in ters of ultiple space ectors by the following equations, written in a stationary reference frae:

3 i SI i i SI i i L i L SI L L L SI L Fig. 2: Equialent circuit of the whole induction otor drie in ters of three-phase space ectors. S1 dϕs1 = RS is1, ϕ S1 = L S1 is1 M1 ir1, (3) dt d R1 0 = ϕ RR ir1 j pωϕr1 dt, ϕ R1 =M 1 is1 LR1 ir 1, (4) S5 = dϕs5 RS is5 dt, ϕ S5 = LS is 5, (5) T =, (6) 3p M1 is1 j ir1 where p is the pole pairs nuber, ω is the rotor angular speed, and the subscripts S and R denote stator and rotor quantities, respectiely. It should be noted that i S1 and i R1 are responsible for the sinusoidal spatial distribution of the agnetic field in the air gap, whereas i S 5 does not contribute to the air gap field. Field Oriented Control In dual three-phase induction otor dries, the reference alues of the d 1 -q 1 coponents of the stator currents in a synchronous reference frae, i 1d,ref and i 1q,ref, are deterined on the basis of flux and torque coands, respectiely [11]. The d-axis of synchronous reference frae is aligned with the rotor flux, displaced by angle ϑ with respect to the d-axis stationary reference frae. The reference oltages of the two dual three-phase inerters are deterined according to the block diagra shown in Fig. 3 [19]. i 1d,ref i 1q,ref k i k i 1 i 5d,ref -i 5q,ref i 1d i 1q i 5d -i 5q PI PI PI PI 1d,ref 1q,ref 5d,ref - 5q,ref e jϑ e jϑ S 1, ref * S5, ref 6φ to 2x 3φ decoposition ref ref k k 1 1,ref L,ref,ref L,ref SM SM SI SI L SI SI L gate signals gate signals Fig. 3: Block diagra of the regulation schee with power sharing capabilities for dual three-phase induction otor dries [19].

4 In the considered syste, the power sharing aong the four sources shows three degrees of freedo. The first one, k i, concerns the power sharing between the two three-phase windings {1} and {2}. The second and third ones, k and k, are related to the power sharing between the two inerters and L which supply each three-phase winding. With reference to the block diagra of Fig. 3, indiidual odulation indexes are defined as ref =, 2 3, = 3 ref, L, = 3 L ref (7) ref =, 2 3, = 3 ref, L, = 3 L ref (8) being 2/ 3 and 1/ 3 the axiu aplitude of sinusoidal balanced output oltages for dual three-phase inerters and single three-phase inerters, respectiely [17]. Introducing in (7) and (8) the definition of oltage ratios k and k, the relationships aong indiidual odulation indexes can be deterined as follows, ref = k ref, L, ref = (1 k ) ref = 2 k, L = 2 (1 k ) (9), ref = k ref, L, ref = (1 k ) ref = 2 k, L = 2 (1 k ) (10) ardware ipleentation The six-phase quad-inerter induction otor drie has been ipleented in the Power Electronics Lab of the Dept. of Electrical Engineering, Uniersity of Bologna (IT). A picture of the working area is gien in Fig. 4. The syste consists in two processor boards, including a TMS320F2812 DSP each, as depicted in Fig. 5. The DSP-1 board acts a aster unit, perforing all the calculations required by the control schee of Fig. 3, and proiding for the firing signals of inerters 1 and L1 by its own internal PWM unit. The DSP-2 board acts a slae unit, receiing the odulating signals fro the DSP-1 by the ultichannel buffered serial port (McBSP data cable connection). DSP-2 proides for the firing signals of inerters 2 and L2 by its own internal PWM unit. Two DSP controllers are synchronized with proper counication for transitting/receiing the signals by setting proper frae period, frae pulse-width of frae synchronization generator, saple rate clock diision and transitter/receier interrupts of the McBSP protocol unit. In detail, transitter/receier is configured in reset at the beginning of initialization, then the McBSP is prograed for desired transitter/receier operation. Finally the McBSP transitter/receier is taken out of reset after two clock cycle of the saple rate generator clock cycle. Inerter 1 Inerter 2 DSP-1 DSP-2 McBSP data cable Inerter L1 Inerter L2 Fig. 4: Oerall iew of the working area in the Lab. Fig. 5: Top iew of the ain syste boards.

5 Table I: Main paraeters of four inerters and six-phase load MOSFETs (6 in parallel per switch) ishay Siliconix SUM85N15-19 MOSFET ratings DSS =150 []; R DS GS =10[]; I D =85[A] switching frequency 2 [kz] -bus capacitance (4 banks) 12 [F] -bus oltage (4 in all) 52 [] load ipedance (open ends, 6 in all) 6 [Ω] load power factor (angle) 0.67 (48 ) load rated current 10 [A] In DSP-1 McBSP transitter frae is configured with single-phase, 2 words per frae of two 16-bit data for transitting (odulating signal in stationary reference frae) to DSP-2 and receier frae is configured with single-phase, 1 words per frae of one 16-bit data for receiing enable reception fro DSP-2 slae unit. In DSP-2 McBSP receier frae is configured with single-phase, 2 words per frae of two 16-bit data for receiing (odulating signal in stationary reference frae) fro DSP-1 and transitter frae is configured with single-phase, 1 words per frae of one 16-bit data for transitting enable reception to DSP-1 aster unit. Rising edge of the transitter clock pin generates the transission of the data and falling edge of the receier clock pin generates the reception of the data in the both aster/slae DSP McBSP configuration with transitting/receiing the data in 2-bit data delay. The McBSP sends a receier interrupt request to the CPU when each receie frae-synchronization pulse is detected and in reset state as well. Transitter generates an interrupt request to the CPU when new frae synchronization occurs. In this way both aster DSP-1 and slae DSP-2 transit/receie the data with proper synchronization and hand-shake. The ain paraeters of the four 2-leel SIs are gien in Table I, together with load paraeters. For the sake of siplicity, these first experiental tests are carried out by using a syste of six balanced ipedances (passie load) instead of the dual three-phase induction otor load. The six-phase otor will be deried fro a conentional three-phase induction otor by rearranging the winding connections. Inerters are odulated here without ultileel output oltage optiization, and a phase angle of 30 is set as the displaceent between the output oltages of the two dual three-phase inerters. Experiental Results A coplete set of open-loop experiental results is presented in this section, on the basis of the siulations gien in [19], with reference to balanced and unbalanced operating conditions. In the first experiental test (Figs. 6-8), the behaior of the syste is analyzed in balanced conditions with odulation indexes = = 0.75, corresponding to a current ratio k i = 1/2 (balanced currents), and oltage ratios k = k = 0.50 (balanced oltages). In this operating condition the total power is equally shared aong the four SIs, and indiidual odulation indexes fro (9) and (10) are = L = = L = Fig. 6 depicts line-to-line oltages ( and L), artificial phase-to-neutral oltages ( and L), and load phase oltage (calculated) for the two dual three-phase inerters {1} and {2}. Fig. 7 shows artificial phase-to-neutral oltages ( and L) and their fundaental coponents, load phase oltage (easured) and current for the two dual three-phase inerters {1} and {2}. All the six-phase output currents are shown in Fig. 8. It should be noted that the currents are alost sinusoidal, practically with sae aplitude and correct phase angle displaceent (load ipedances are not perfectly balanced).

6 {1} {2} Fig. 6: oltage waefors of the two dual three-phase inerters {1} and {2} in balanced conditions, = = 0.75 (k i = 1/2), k = k = Fro top to botto: line-to-line oltages ( and L), artificial phase-to-neutral oltages ( and L), and load phase oltage (calculated). {1} {2} Fig. 7: oltage, current, and filtered waefors of inerters {1} and {2} in balanced conditions. Fro top to botto: artificial phase-to-neutral oltages ( and L) and their fundaental coponents, load phase oltage (easured) and current. Fig. 8: Six-phase load currents in balanced conditions. Inerter {1}: purple traces (2 easured, 1 calculated). Inerter {2}: turquoise traces (2 easured, 1 calculated).

7 In the second experiental test (Fig. 9) the behaior of the syste is analyzed in unbalanced conditions to erify the power sharing capability between the two inerters and L of the two dual threephase inerter {1} and {2}. In particular, odulation indexes = are set as in the preious case, = = 0.75, corresponding to a current ratio k i = 1/2 (balanced currents), whereas oltage ratios are k = k = 0.60 (unbalanced oltages), leading to indiidual odulation indexes = = 0.90, L = L = 0.60, gien by (9) and (10). In this operating condition inerters supply 50% ore power that inerters L. Fig. 9 shows artificial phase-to-neutral oltages ( and L) and their fundaental coponents, load phase oltage (easured) and current for the two dual three-phase inerters {1} and {2}. As expected, fundaental oltage coponents of indiidual inerters and L are one 50% ore than the other. oweer, being load phase oltages the sae as in preious case, load currents are the sae as well. {1} {2} Fig. 9: oltage, current, and filtered waefors of inerters {1} and {2} in unbalanced conditions, = = 0.75 (k i = 1/2), k = k = Fro top to botto: artificial phase-to-neutral oltages ( and L) and their fundaental coponents, load phase oltage (easured) and current. In the third and last experiental test (Figs ) the behaior of the syste is analyzed in unbalanced conditions to erify the power sharing capability between the two inerters {1} and {2}. In particular, odulation indexes and are set one the double of the other, = 0.75, = 0.375, corresponding to a current ratio k i = 2/3 (unbalanced currents), whereas oltage ratios are k = k = 0.50 (balanced oltages), leading to indiidual odulation indexes = L = 0.75, = L = 0.375, gien by (9) and (10). In this operating condition inerter {1} supplies 50% ore power that inerter {2}. {1} {2} Fig. 10: oltage, current, and filtered waefors of inerters {1} and {2} in unbalanced conditions, = 0.75, = (k i = 2/3), k = k = Fro top to botto: artificial phase-to-neutral oltages ( and L) and their fundaental coponents, load phase oltage (easured) and current.

8 Fig. 10 shows artificial phase-to-neutral oltages ( and L) and their fundaental coponents, load phase oltage (easured) and current for the two dual three-phase inerters {1} and {2}. As expected, fundaental oltage coponents of inerters {1} and {2} are one the double of the other, proiding load currents with the sae ratio, corresponding to k i = 2/3. All the six-phase output currents are shown in Fig. 11. Also in this case, currents are practically sinusoidal, with an alost correct phase angle displaceent (een if load ipedances are not perfectly balanced). As expected, the currents supplied by inerter {1} hae an aplitude double of the currents supplied by inerter {2}. Fig. 11: Six-phase load currents in unbalanced conditions. Inerter {1}: purple traces (2 easured, 1 calculated). Inerter {2}: turquoise traces (2 easured, 1 calculated). Conclusion A preliinary ersion of a ulti-phase ulti-leel ac otor drie based on a dual three-phase openend windings induction achine has been ipleented and analyzed in this paper. The power supply consists of four conentional 2-leel three-phase oltage source inerters with insulated sources. The whole control schee was deeloped using two TMS320F2812 DSP controllers working under McBSP protocol for PWM counication in open-loop analysis, controlling a six-phase load with open-end configuration. It has been shown that, by an appropriate control strategy, the total otor power can be shared aong the four sources with three degrees of freedo. In order to regulate the couple of 2-leel SIs supplying each three-phase winding such as a 3-leel inerter, a siplified PWM technique has been adopted, allowing the power sharing between the two sources. This regulation leads to two degrees of freedo in the total power sharing, one for each dual three-phase inerter. A suitable technique has been adopted in order to regulate the power sharing between the two dual three-phase inerters, leading to an additional degree of freedo in the total power sharing. Real tie test results proided in this paper proe the effectieness of the proposed six-phase quadinerter syste in different operating conditions using two DSP-based controllers. oweer, these experiental results should be considered only as the preliinary tests in order to proe the effectieness of the hardware ipleentation of the ulti-phase ulti-leel induction otor drie. Next step is to introduce the six-phase induction otor instead of the passie load, according to the control schee presented in [19], and to optiize the output oltage waefors according to the ultileel control strategy proposed in [17].

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