Designing a Variation-Tolerant Ultra Wide Band Low-Noise Amplifier

Transcription

1 Desinin a Variation-Tolerant Ultra Wide Band ow-noise Amplifier ECE 551 Course Project Report 1 Desinin a Variation-Tolerant Ultra Wide Band ow-noise Amplifier Aliakbar Ghadiri and Majid Ghanbarinejad Abstract In this report, the steps for desinin and simulatin an ultra wide band low-noise amplifier are explained. A technique is used to make the amplifier robust aainst process ariations. The performance of the desined amplifier and the technique used for process inariance are erified ia simulation. Index Terms Process ariations, low-noise amplifier (NA), ultra wide band (UWB) amplifier, Chebyshe filter. P I. INTRODUCTION ROCESS ariation is defined as the deiation from intended or desined alues for a structure or circuit parameter of concern [1]. Generally, there are two types of sources of ariation: enironmental factors and physical factors. Enironmental factors are those affectin the circuit behaior durin the operation of the circuit. Examples are ariations in power supply, switchin actiities, and temperature of (or across) the chip. Physical factors, howeer, affect the circuit durin manufacturin and cause permanent ariations in structures and interconnections. These ariations are mainly due to the processin and maskin limitations. The deiations from the desined alues can be either random or spatially aryin. Process ariations affect both yield and performance of hihspeed diital, and hih-frequency analo, circuits especially in deep sub-micron technoloies [1]. By the term process ariations, we mean the physical factors affectin the fabricated circuit permanently. As an instance of the techniques used to reduce the effects of process ariations, in this report, we desin a ariation-tolerant UWB NA. The report is oranized as follows. Section II is a literature reiew on process ariations, their effects on circuit performance, and examples of the techniques proposed to derade these effects. In section III, the steps to desin a process-inariant UWB NA are explained and the circuit performance is tested ia simulation. Finally, section IV concludes the report. cateorized into two major types [1]: inter-die ariations and intra-die ariations. Inter-die, or die-to-die, ariation is the difference in a parameter alue across different nominally identical dies. In eneral, eery parameter alue has a (typically normal) distribution instead of hain a fixed alue in all the dies. Inter-die ariation, thus, is accounted for as a shift in a parameter alue, e.. threshold oltae or wire width. There are two types of models for inter-die ariations: one can simply consider the die-to-die ariations independently, or characterize systematic trends across the wafer. Die-to-die ariations are themseles rouped into site-to-site and waferto-wafer ones. Fi. 1 illustrates the difference between these two sub-cateories. The deiation occurrin spatially within a sinle die is called intra-die, or within-die, ariation. This type of ariation causes mismatch in the structures that are supposed to be the same (e.. the half-circuits of a differential amplifier). There are two main sources for within-die ariations: spatially aryin trends across the die as a part of whole the trend in a wafer, or die-pattern (lay) dependencies. Aain, one may find systematic methods to model these ariations, or the ariations can be treated as random. The followin is a list of typical process ariations [1]. Deice Geometry Variations (e.. lateral dimension), Deice Material Parameter Variations (e.. dopin), Deice Electrical Parameter Variations (e.. threshold oltae, leakae current), Interconnect Geometry Variations (e.. line width and thickness, ia size), Interconnect Material Parameter Variations (e.. contact and ia resistance, dielectric constant). B. Effects of Process Variations As mentioned before, process ariations can affect either yield because of failures or performance due to ariations in parameter alues. Parameter alues in an interated circuit are II. ITERATURE REVIEW A. Types of Process Variations From the pattern iewpoint, process ariations are Fi. 1. Die-to-die process ariations. a) site-to-site ariations and b) waferto-wafer ariations [].

2 Desinin a Variation-Tolerant Ultra Wide Band ow-noise Amplifier ECE 551 Course Project Report Fi.. Variations of a) the rise time and b) the fall time of an inerter [3]. Fi. 3. Variations of the input-to-put delay of a -input NAND ate [3]. not constant (and equal to what are desined or intended). Each parameter alue can be modeled as a random ariable, with a typically normal (i.e. Gaussian) distribution. Mainly, the effects of ariations bein considered in the literature are: Effects on diital circuit characteristics: timin characteristics, power consumption, and noise marins; Effects on VSI circuits: clock frequency of microprocessors, clock skew, nano-scale memories, and FPGA deices; and, Effects on analo/rf circuits. We will take a look at a few instances. Effects on Timin Characteristics. Fi. shows the distribution of put rise time and fall time of an inerter. As can be seen, the distributions are almost normal. Similarly, as shown in Fi. 3, the delay from the inputs of a NAND ate to its put in the same technoloy is normally distributed [3]. Effects on Noise Marin. Fi. 4 illustrates the oltae transfer characteristic of an inerter in different sub-micron technoloies. As technoloy shrinks from 90-nm to 3-nm, the noise marin (illustrated as the ede lenths of the embedded squares) derades. Aain, as expected, the distributions of the hih and low noise marins are bell-shaped as shown in the fiure [4]. Effects on Maximum Clock Frequency. Maximum clock frequency in VSI circuits, especially in hih-speed microprocessors, is a main concern. Fi. 5 illustrates how process ariations toether with the number of critical paths affect both the mean and the ariance of the distribution of maximum clock frequency in a sample microprocessor [5]. Hain a ood estimation of the ariations is an important concern oerestimatin impacts the desin effort while Fi. 4. Variations of noise marin in an inerter in different technoloies. a) Voltae transfer characteristic, b) Historams of hih and low noise marins [4]. Fi. 1. Variations of maximum critical path delay in clock re for different numbers of critical paths [5]. underestimatin affects the manufacturin effort. C. Process Variation-Tolerant Techniques Seeral techniques hae been proposed to decrease the effects of process ariations on CMOS circuits. These techniques can be diided into two main cateories: Postsilicon methods and pre-manufacturin methods. Post-silicon methods are used when the chip is fabricated and suffers from process ariations. Pre-manufacturin methods are included in the desin stae and the manufactured chip will hae processtolerant capabilities. 1) Post-silicon Methods These methods are usually effectie for VSI circuits and can be diided into two major cateories: Adaptie Body Bias (ABB) and Adaptie Voltae Scalin (AVS). With ABB, the threshold oltae of the transistors will be chaned in an adaptie manner to decrease the effect of process ariations. AVS is used to optimize power consumption under a set of

3 Desinin a Variation-Tolerant Ultra Wide Band ow-noise Amplifier ECE 551 Course Project Report 3 Fi. 6. Comparison of ABB and IWABB techniques for leakae current of different dies [7]. Fi. 8. Binnin improement for adaptie V DD [7]. Fi. 7. Architecture of a Dynamic Voltae Scalin (DVS) system [14]. timin constraints in the presence of process ariations. a) Adaptie Body Bias (ABB) Most of the existin ABB methods use a sinle body bias for NFETs and a sinle body bias for PFETs across an entire die, but it is more effectie to apply ABB technique for indiidual wells, i.e. to use Indiidual Well-Adaptie Body Biasin (IWABB) [6]. Fi. 6 illustrates the distribution of natie leakae ersus F max as well as the resultin distribution after ABB and IWABB are applied. ABB reduces the ariance of the frequency ariation by a factor of 6, and moes oer 30% of the dies into the hihest frequency bin. But within-die ariations cannot be handled usin only a sinle bias alue per die. IWABB further reduces the frequency ariation and moes 97% of the dies into the hihest bin [7]. In IWABB technique, n-wells are tied to a separate V bp rid and the p-type substrate is tied to a V bn rid. New rids need rin and affect the functionality of the analo and memory blocks. Thus, to be isolated, such elements must be implemented in separate p-wells. This requires a triple-well process. Therefore, IWABB is expensie. b) Adaptie Voltae Scalin (AVS) AVS has the similar effect as ABB on chanin performance and power consumption in presence of process ariations. A simple ersion of AVS is the use of dual supply oltaes to minimize power under timin constraints, but this method is a pre-manufacturin technique. The well-known equation for dynamic power consumption in diital circuits is Fi. 9. The topoloy of the proposed current enerator in [10]. P dyn C V f. (1) a DD AVS Chanes V dd to optimize power consumption under a set of timin constraints. Fi. 7 shows the architecture of a eneric AVS system [8]. The performance manaer exploits a software interface to predict the performance requirements. When performance requirement for the next task is determined, the performance manaer sets the new alues for oltae and frequency to accomplish the task. The new frequency alue is sent to the phase-locked loop (P) to apply the frequency scalin and the new oltae alue is produced by a prorammable oltae reulator. Fi. 8 illustrates the binnin improement possible with an AVS technique, where the number of dies in the top two frequency bins improes by 45% [7]. c) Comparin ABB s. AVS Both techniques can be used to improe product yield in the presence of process ariations, but it is not necessary to use them simultaneously in the same desin, at least up to 100-nm CMOS technoloy eneration. From the cost perspectie, ABB is more expensie than AVS due to additional rin. For AVS, potential concerns may include reliability issues stemmin from increased hot electron effect [9]. ) Pre-manufacturin Methods Pre-manufacturin techniques are used before manufacturin in desinin step. Seeral circuit techniques hae been reported to decrease the effects of process ariations in diital, analo and RF circuits. Since our oal is to desin a process inariant UWB amplifier, we present two techniques

4 Desinin a Variation-Tolerant Ultra Wide Band ow-noise Amplifier ECE 551 Course Project Report 4 Fi. 10. Spread of the transistor current in two wafer runs. a) With and b) with usin the proposed current enerators [10]. Fi. 1. Process-inariant structure for the tuned NA [11]. Fi. 11. Conentional NA with C-tuned load [11]. used for analo and RF circuits. a) Process-Inariant Current Source In this section, we introduce a current enerator where the put current is the summation of two currents, i.e. I I1 + I I I1 + I. Fi. 9 shows the topoloy of this current enerator. We make some assumptions to simplify the expression for currents in this circuit. We assume that the threshold oltaes of M1 and M are well matched due to their proximity in the lay. Moreoer, we consider that the mean alue of ate oltaes and sizes of M1 and M equal V s1 Vs Vs, () and W W ( µ Cox ) 1 ( µ Cox ). (3) Assumin that the moment does not ary, we obtain [10] [( V V V ] W I I1 + ( µ Cox ) s th) s. (4) To reduce the effect of process ariations, I 0. Therefore, V s ( µ C ox I1 I W ) V m ( s Vth ) 1. (5) If we set the alue of the resistor accordin to Eq. 6, we will hae a process-tolerant current enerator [10]. R (6) m Fi. 10 shows the results measured after applyin this Fi. 13. Gain ariation due to ±0% MOM capacitor and ±13% poly resistor deiation a) conentional NA structure b) proposed NA structure [11]. technique to two wafers run with 40 current enerators of the proposed topoloy. The mean alues of the current distribution for two wafers are approximately the same while the standard deiation of the distribution decreases 0% in comparison to current enerators not exploitin this technique. b) Process-tolerant Tuned RF NA Another example is a ain stabilization technique used for tuned RF NA. Fi. 11 shows the circuit for a conentional NA with an C-tuned load. With tolerance of ±0% of interated poly-silicon resistor, NA oltae ain ariation is ab 3.5 db [11]. Fi. 1 shows the proposed structure to decrease the effect of process ariations [11]. In this topoloy, R ser and P par are realized with the same resistance material. Moreoer, R ser n s.r sh, par n p.r par P. (7) These resistors are placed close to each other on the circuit and thus, their process radient is ery similar. Thus, process ariation affects the resistances in a similar manner and the equialent resistance will be less sensitie to process ariations. The oad impedance for the amplifier can be written as ( ω0) Z ( ) R Rpar ( R + R ) f ( R ω. (8) 0 sh ls ser To remoe the ariations, we must hae Z ( ω 0 ) 0 R sh and thus, we hae equations, (9) )

5 Desinin a Variation-Tolerant Ultra Wide Band ow-noise Amplifier ECE 551 Course Project Report 5 Fi. 16. A T-type 3 rd order Chebyshe filter [13]. TABE I EEMENT VAUES CACUATED FOR THE DESIRED FITER Fi. 14. The topoloy selected for the UWB NA [13]. 1 C 1 C + s C t The alues are inductances and capacitances are in nh and pf respectiely. (nm) W 1 (µm) W W 3 (µm) TABE II CACUATED EEMENT VAUES C p (ff) R (Ω) s (nh) (nh) (nh) x Fi. 15. A source-deenerated common-source stae. The input impedance, Z in, is supposed to be purely resistie in the resonance frequency. n p R R sh0 Qω0 Qω R 0 ω R Q 0 0, n ( 1), (10) s sh0 Qω R in which R sh0 is the nominal alue of the sheet, i.e. unit resistance. Fi. 13 shows the comparison of the proposed technique with the conentional circuit. With ±0% capacitor deiation and ±13% poly resistor deiation, the proposed technique presents less than 1 db ariations in ain while the conentional circuit shows more than 3 db ain ariations [11]. A. Desin Criteria III. DESIGNING THE UWB AMPIFIER The technoloy used for the desin is 90 nm. The frequency band will be from 3.1 GHz to 10.6 GHz. We want the circuit to consume no more power than 10 mw with the supply oltae of 1 olt. The load and source impedances are 50 ohms. The desired ain should be more than 10 db and the reflection at each terminal is desired to be less than -10 db. We also expect the noise fiure to be less than 3 db. B. Selected Topoloy The topoloy chosen for the UWB amplifier circuit is shown in Fi. 14. The main part of the amplifier circuit is an inductiely source-deenerated common-source stae followed by a common-drain stae as put buffer. The adantae of the source-deeneration structure is that it proides purely matched resistie input impedance in the resonance frequency. Fi. 15 illustrates the source-deenerated topoloy. The input impedance of the common-source transistor, Z in, is Z 1 m in + jωs jωc + C s s s. (11) From the equation, it is obious that the real, i.e. resistie, part of the input impedance is a function of s, the inductance used to deenerate the source [1]. A 3 rd order Chebyshe filter is used at the input of the amplifier as shown in Fi. 16. The T-type structure is used to allow the bias oltae, V bias, fed from the bottom and the input sinal, V in, fed from the left. The parameters of the filter must be desined so that the pass band of the filter is the frequency rane of UWB, i.e. 3.1 GHz to 10.6 GHz. The alues of the elements for a low-pass 3 rd order Chebyshe filter are aailable in tabulated form. The alues of the elements are typically normalized by a factor of 50 ohms. The followin equations are used to chane the alues of the elements in order to moe the frequency band to the UWB pass-band [14]. ω ω ω 0 u l (1) C C BP1 BP BP ω ω u l (13) ω0 1 ω ω (14) u u 1 ω ω l l 1 (15)

6 Desinin a Variation-Tolerant Ultra Wide Band ow-noise Amplifier ECE 551 Course Project Report 6 Fi. 17. Broad-band model of an inductor. Fi. 19. Cascode stae of the amplifier. Fi. 18. Output buffer of the amplifier. The put impedance must be matched to R ext. TABE III FINA SIMUATION RESUTS S1(dB) S11(dB) S(dB) BW(GHz) NF (db) P(mW) 11.5 <-13 < <3 9.8 BP ω ω u l (16) ω0 In the aboe equations, ω l and ω u are respectiely the lower and upper frequencies of the desired band. The calculated alues are listed in Table I. The inductances are assumed to be ideal. In reality, howeer, an inductance has parasitic resistie and capacitie components. To hae simulation results closer to the behaior of the real circuit, a broad-band model, as what is illustrated in Fi. 17, is used. The last stae of the amplifier is a common-drain transistor as the put buffer. Since the supply oltae is 1 olt, the total consumed current will be 10 ma in order to hae a power consumption of 10 mw. We choose 4 ma for each of the two staes and ma for the reference current circuit. The ain of the last stae, as illustrated in Fi. 18, is 1 m3rext 1+ R m3 ext. (17) To hae matched impedance at the put, one has m3 and thus, R 50Ω ext 0.5 6dB, (18), (19) Fi. 0. Primary schematic of the simulated circuit. An ideal current source is used at the buffer stae. resultin in 16dB. (0) Fi. 19 shows the schematic of the cascode stae. The total ain from the source to the put of the stae will be s R (1 + ) mw ( s) R in sctrs 1+ src + s C. (1) R is determined by the oltae headroom and R and are chosen to place the zero frequency ω z R / close to the lower frequency band, i.e. 3.1 GHz. To increase the put impedance of the transistors, their lenths are chosen to be 180µm. Assumin the oer-drie oltaes of M1 and M and oltae drop of R to be respectiely 0., 0.4 and 0.4, the calculated alues for the elements are obtained as shown in Table II. Fi. 0 shows the schematic of the simulated circuit. For the first step ideal current source was used at the put buffer. Then, the ideal current source is replaced by the circuit shown in Fi. 1. Fi. shows the S-parameters resulted from the simulation of the circuit. S 1 is more than 11.5 db, and S 11 and S are less than -13 db and -10 db, respectiely. Furthermore,

7 Desinin a Variation-Tolerant Ultra Wide Band ow-noise Amplifier ECE 551 Course Project Report 7 Fi. 1. Schematic of the current source at the put buffer. Fi. 3. Simulation results for noise fiure. Fi.. Simulation results for S-parameters. the ain is flat across the bandwidth. Fi. 3 illustrates the noise fiure of the amplifier which is less than 3 db across the bandwidth. Table III shows the final simulation results. C. Desinin the Variation-Tolerant UWB Amplifier The major effects of process ariations on a UWB amplifier are shiftin the bandwidth and improper input matchin. These effects arise due to ariations of the alues of inductors and capacitors. To decrease this effect, each inductor is composed of four series smaller inductors and each capacitor is chosen to be the parallel connection of four smaller capacitors. For each inductor, these four series inductors will be placed symmetrically in the lay. Therefore, the equialent inductors will be less sensitie to process ariations. Such a structure acts in a similar way for capacitors. Thus, the filter and the cascode stae will be less sensitie to process ariations. Moreoer, similar to the technique discussed in section II, small inductors in series and small capacitors in parallel are multiples of a reference inductor and a reference capacitor, respectiely. Therefore, with splittin the inductors and capacitors to smaller parts and exploitin the technique used in [11], both the filter characteristics and the frequency response of the amplifier will be ariation-tolerant. Fis. 4, 5, and 6 show the comparison of simulation results for the UWB NA with and with usin the proposed technique. In both cases, a ariation of 15% is applied to the inductors and the capacitors. As illustrated in Fi. 4.b, the ariation of S 1 for the amplifier exploitin the proposed technique is less than Fi. 4. S 1 of a) oriinal and b) modified circuit that of the amplifier not exploitin it. As shown in Fi. 4.a the oriinal amplifier does not always meet the desin criteria while the modified one does. Fi. 5.b shows that the modified amplifier presents S 11 less than -1 db in the presence of process ariations, while the oriinal amplifier has an S 11 more than -8 db for some frequencies. Finally, both the amplifiers meet the desin criteria for S since the puts of the amplifiers are less sensitie to the chanes of their inductors and capacitors. IV. CONCUSION In this report, we desined a UWB NA composin of a Chebyshe filter, a source-deenerated common-source amplifier, and a common-drain stae as the put buffer. Then, a technique was proposed to make the amplifier robust

8 Desinin a Variation-Tolerant Ultra Wide Band ow-noise Amplifier ECE 551 Course Project Report 8 Fi. 5. S 11 of a) oriinal and b) modified circuit aainst process ariations. Simulation shows that the technique improes the performance of the amplifier in terms of the robustness of the S-parameters aainst process ariations. REFERENCES [1] D. Bonin and Sani Nassif, Models of Process Variations in Deice and Interconnect, in A. Chandrakasan, W. J. Bowhill, and F. Fox (Ed.), Desin of Hih-Performance Microprocessor Circuits, IEEE Press, 000. [] D. Kim, C. Cho, J. Kim, J. O. Plouchart, R. Trzcinski, and D. Ahlren, CMOS Mixed-Sinal Circuit Process Variation Sensitiity Characterization for Yield Improement, in IEEE Custom Interated Circuits Conf. (CICC 06), Sep [3] H. Mahmoodi, S. Mukhopadhyay, and K. Roy, Estimation of Delay Variations Due to Random-Dopant Fluctuations in Nano-Scaled CMOS Circuits, IEEE Journal of Solid-State Circuits, ol. 40, no. 9, pp , Sep [4] Z. ian, M. Ikeda, and K. Asada, Analysis of Noise Marins Due to Deice Parameter Variations in Sub-100nm CMOS Technoloy, in IEEE Desin and Dianostics of Electronic Circuits and Systems (DDECS '07), 007. [5] K. A. Bowman, S. G. Duall, and J. D. Meindl, Impact of Die-to-Die and Within-Die Parameter Fluctuations on the Maximum Clock Frequency Distribution for Giascale Interation, IEEE Journal of Solid-State Circuits, ol. 37, no., pp , Feb. 00. [6] J. Gre and T. W. Chen, Post Silicon Power/Performance Optimization in the Presence of Process Variations Usin Indiidual Well-Adaptie Body Biasin, IEEE Transactions on Very are Scale Interation (VSI) Systems, ol. 15, no. 3, pp , Mar [7] J. Tschanz, K. Bowman and V. De, Variation-Tolerant Circuits: Circuit Solutions and Techniques, Proceedins of the 4nd annual conference on Desin automation, 005, pp [8] M. Elebaly and M. Sachde, Variation-Aware Adaptie Voltae Scalin System, IEEE Transactions on Very are Scale Interation (VSI) Systems, ol. 15, no. 5, pp , May 003. [9] T. Chen and S. Naffzier, Comparison of Adaptie Body Bias (ABB) and Adaptie Supply Voltae (ASV) for Improin Delay and eakae Under the Presence of Process Variation, IEEE Transactions on Very Fi. 6. S of a) oriinal and b) modified circuit are Scale Interation (VSI) Systems, ol. 11, no. 5, pp , Oct [10] A. M. Pappu, X. Zhan, A. V. Harrison and A. B. Apsel, Process- Inariant Current Source Desin: Methodoloy and Examples, IEEE Journal of Solid-State Circuits, Vol. 4, Issue 10, Oct. 007, pp [11] P. Sionen, A. Vilander, and A. Pärssinen, A Gain Stabilization Technique for Tuned RF ow-noise Amplifiers, IEEE Transactions on Circuits and Systems-I: Reular Papers, ol. 51, no. 5, pp , Sep [1] T. H. ee, The Desin of CMOS Radio-Frequency Interated Circuits, Cambride, U.K.: Cambride Uni. Press, [13] A. Beilacqua and A.M. Niknejad, "An Ultrawideband CMOS ow- Noise Amplifier for GHz Wireless Receiers," IEEE Journal of Solid-State Circuits, Vol. 39, Issue 1, Dec. 004, pp [14] D. K. Misra, Radio-Frequency and Microwae Communication Circuits, Analysis and Desin, nd Ed., John Wiley and Sons Inc., Hoboken, New Jersey, 004.