Lecture 19 ANNOUNCEMENTS. For Problem 4 of HW10, use V DD = 1.8V and V TH = 0.4V Note: Midterm #2 will be held on Thursday 11/15 OUTLINE

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1 Lecture 9 ANNOUNCEMENTS For Proble 4 of HW0, use V DD.8V and V TH 0.4V Note: Midter #2 will be held on Thursday /5 OUTLINE Coon ate stae Source follower ead: Chapter EE05 Fall 2007 Lecture 9, Slide Prof. Liu, UC Berkeley

2 Diode Connected MOSFETs Diode-connected NMOSFET Diode-connected PMOSFET X ro Y ro 2 2 Sall-sal analysis circuit Sall-sal analysis circuit Note that t the sall sal lodel dlof a PMOSFET is identical to that of an NMOSFET EE05 Fall 2007 Lecture 9, Slide 2 Prof. Liu, UC Berkeley

3 Suary of MOSFET Ipedances Look to the ate, the ipedance is fite ( ). Look to the dra, the ipedance is r o if the ate and source are (ac) rounded. Look to the source, the ipedance is / parallel with r o if the ate and dra are (ac) rounded. EE05 Fall 2007 Lecture 9, Slide 3 Prof. Liu, UC Berkeley

4 Coon Gate Aplifier Stae An crease V decreases V GS and hence decreases I D. The oltae drop across D decreases V creases The sall sal oltae a (A ) is positie. A D EE05 Fall 2007 Lecture 9, Slide 4 Prof. Liu, UC Berkeley

5 Operation Saturation eion For M to operate saturation, V cannot fall below V b V TH. Trade off between headroo and oltae a. EE05 Fall 2007 Lecture 9, Slide 5 Prof. Liu, UC Berkeley

6 I/O Ipedances of CG Stae (λ 0) Sall-sal analysis circuit for deter put resistance, Sall-sal analysis circuit for deter put resistance, D EE05 Fall 2007 Lecture 9, Slide 6 Prof. Liu, UC Berkeley

7 CG Stae with Source esistance Sall-sal equialent circuit seen at put X S + X X D S + For λ 0: A + D S EE05 Fall 2007 Lecture 9, Slide 7 Prof. Liu, UC Berkeley

8 The put ipedance of a CG stae with source resistance is identical to that of CS stae with deeneration. Sall-sal analysis circuit for deter put resistance, ( + ) ( ) S + S + ro S ro r + O EE05 Fall 2007 Lecture 9, Slide 8 Prof. Liu, UC Berkeley

9 CG Stae with Bias and 2 establish the ate bias oltae. 3 proides a path for the bias current of M to flow. ( ) 3 / / + 3 ( ) D S EE05 Fall 2007 Lecture 9, Slide 9 Prof. Liu, UC Berkeley

10 CG Stae with Gate esistance For low sal frequencies, the ate conducts no current. Gate resistance does not affect the a or I/O ipedances. EE05 Fall 2007 Lecture 9, Slide 0 Prof. Liu, UC Berkeley

11 CG Stae Exaple X Sall-sal equialent circuit seen at put S + ( + ) 2 S Sall-sal equialent circuit seen at put r O S + r 2 O X D A X ( ) S r + r O S O 2 D EE05 Fall 2007 Lecture 9, Slide Prof. Liu, UC Berkeley

12 Source Follower Stae r O L A < + ro L Sall-sal analysis circuit for deter oltae a, A Equialent circuit + ( r ) o L ( )( r ) o L EE05 Fall 2007 Lecture 9, Slide 2 Prof. Liu, UC Berkeley

13 Source Follower Exaple In this exaple, M 2 acts as a current source. A r O + r r O O 2 ro O 2 EE05 Fall 2007 Lecture 9, Slide 3 Prof. Liu, UC Berkeley

14 of Source Follower The put ipedance of a source follower is relatiely low, whereas the put ipedance is fite (at low frequencies); thus, it is useful as a oltae buffer. Sall-sal analysis circuit for deter put t resistance, ro L L EE05 Fall 2007 Lecture 9, Slide 4 Prof. Liu, UC Berkeley

15 Source Follower with Bias G sets the ate oltae to V DD ; S sets the dra current. (Sole the quadratic equation to obta the alue of I D.) Assu λ 0: I D µ nc 2 ox W L ( V I V ) 2 DD D S TH EE05 Fall 2007 Lecture 9, Slide 5 Prof. Liu, UC Berkeley

16 Supply Independent Bias If s is replaced by a current source, the dra current I D becoes dependent of the supply oltae V DD. EE05 Fall 2007 Lecture 9, Slide 6 Prof. Liu, UC Berkeley