Transimpedance Amplifier Based on Inductive Peaking Techniques for Broadband Data Transmission

Transcription

1 ISSN 348-7X May 04 Transimpedance Amplifier Based on Inductive Peak Techniques for Broadband Data Transmission Jitendra Kumar Saroj PG Student, Noida Institute Of Eneer & Technoloy, Greater Noida,U.P, India. Kanika Jdal Assistant Professor, Noida Institute Of Eneer & Technoloy, Greater Noida,U.P, India. Satyendra Sharma Associate Professor, Noida Institute Of Eneer & Technoloy, Greater Noida,U.P, India Abstract A Cross-Coupled Current Conveyor base Transimpedance Amplifier implemented to obta the put capacitance load sensitivity effect is troduced. The proposed architecture is desed us 0.µm.-V technoloy with on-chip spiral ductor as shunt peak element and parasitic element are compensated for achiev hih a at mimum tailored put. The measured results show a -3dB bandwidth of about.5 GHz with a 0.5 pf photodiode capacitance and transimpedance a of implemented circuit is 55.5dBΩ. The architecture provides very low power dissipation, reduced by 58% which is most important factor as it can be used cascade confiuration where its output is fed to another system. Keyword: Bandwidth enhancement, crosscoupled current conveyor, on-chip spiral ductor, Transimpedance Amplifier, Parasitic element. I. Introduction The set of communication services be offered to residential home has seen rapid extension the last decades. Customers are no loner only terested Voice technoloy, broadcast television and radio. They are also creasly ask for always on fast ternet communication []. This fast ternet communication system has 36 motivated researchers to look to lare capacity system that is possible by low cost terated optical communication system with ever creas transmission bandwidth []. Currently the most successful hih speed optical communication protocol is SONET OC-9, OC- 768,.5Gb/s Ethernet, 0 Gb/s Ethernet. While the 0 Gb/s Ethernet (IEEE 80.3ae) is also emer as an alternative for pot - to pot applications. Therefore, optical communication system operat at 0 Gb/s are of reat terest [3]. An optical receiver consists of a Photo detector and Transimpedance Amplifier (TIA), is used to convert optical sal to electrical sals the front end of optical communication system. Therefore, hih performance broad bandwidth TIA plays a key role achiev hih speed data transmission lk for the above mentioned standards [4]. Des of hih speed bandwidth TIAs is more expensive us GaAs or Si-bipolar technoloy than CMOS technoloy. CMOS process technoloy ives low power, low cost and hih yield: which offers the most economical solution the consumer application market[5]. There is a need to des a TIA for lare bandwidth, hih a, low noise, low power consumption and small roup delay variation. Amon these parameters, lare bandwidth is critical to achieve [6]. A lare area photodiode is used to capture sufficient optical power, br lare junction capacitance at put node. This capacitance restricted the bandwidth of

2 ISSN 348-7X May 04 conventional TIA. For bandwidth extension, various CMOS TIA architecture for isolat the lare put capacitance of the photodiode from bandwidth determation are used such as common ate (CG) put stae [5], CG feed forward topoloy conta neative feedback also used bandwidth enhancement technique such as ductive peak and capacitive deeneration. To isolate the put capacitance and enhance the bandwidth of transimpedance amplifier capacitive-peak (C-peak) technique is used. This technique is used to des a transimpedance amplifier hav larer bandwidth [7]. Another bandwidth extension technique is optimized that is on-chip spiral ductors as shunt-peak elements. The series resistance of the on-chip ductor is a part of the load resistance to permit a lare ductance to be realized with mimum area and capacitance. Onchip shunt peak is troduced at the domant pole to improve the overall system performance, clud a 40% crease the transimpedance [8]. There is another novel low-power, low-noise CMOS voltae current feedback technique to des transimpedance amplifier. The bandwidth of the amplifier was extended us the ductive peak technique, and, simulation results dicated comparatively hih 3dB bandwidth with a hih transimpedance a. The dynamic rane of the amplifier was wide enouh to enable an output peak-to-peak voltae sw [9]. By us these techniques an optical receiver analo front-end circuit has been desed. This terated circuit terates both transimpedance amplifier and post limit amplifier on a sle chip. In order to facilitate hih-speed operations a low-cost CMOS technoloy, the receiver front-end has been desed utiliz several enhanced bandwidth techniques, clud ductive peak and current jection. The put sensitivity of the receiver front-end is very hih with very low put referred noise [0]. 37 Bandwidth extension of differential CMOS transimpedance Amplifier (TIA) us on-chip ductor techniques is a suitable method to enhance the bandwidth without creas the total power consumption. On-chip ductor is connected series with the output node to enhance the bandwidth. It is seen that the bandwidth is creased by 47 % by us on-chip spiral ductor []. A crossed coupled current conveyor is a bandwidth extension technique for CMOS TIA. It is low noise structure and capacitive sensitive put load. It also supports the capacitive deeneration to further enhancement bandwidth with a very hih speed and low roup delay. This cross-coupled structure also helps build an putsensitive differential TIA []. In the above discussion we come to know about different bandwidth extension technique that ives a successful bandwidth crement as well as low noise, low power consumption and hih transimpedance a. However, we see that the bandwidth of all reported TIAs reduces with creas photodiode s capacitance. This paper presents an put stae based on a cross-coupled current conveyor structure. It creates zero differential impedance at the put node of a TIA [3]. This cross coupled structure also brs a hue improvement power consumption. The shunt-ductive peak [] and capacitive deeneration techniques [7] are also employed for bandwidth enhancement. In Section II, the detailed Cross Coupled Current Conveyor des and analysis is discussed; Section III, Transimpedance Amplifier with ductive peak technique is proposed and discussed. In Section IV, the simulation and measurement results of the proposed structure is presented and discussed. Fally, section V, conclusion is provided with possible future improvements.

3 ISSN 348-7X May 04 V a V b (4) When the current flow throuh node a is I+Δi and current flow throuh node b is I, the differential impedance across node a and b look to the circuit is as follows: ΔZ V i Va Vb i 0 0 (5) i Fi.. Conventional CMOS Current Conveyor II. Circuit Des and Analysis A. Cross-Coupled Current Conveyor Conventional CMOS current conveyor shown the Fi. [3] is use proposed circuit topoloy. When the four PMOS PM, PM, PM 3 and PM 4 are saturation reion, ideally V s V s3 V and V s V s4 V. () Suppose the bias voltae V B is 0-V first, the voltae at node a, V a and the voltae at node b, V b are V a V s + V s4 V + V () V b V s + V s4 V + V (3) Thus I+Δi I From (5), impedance is dependent of Δi and the parasitic capacitance of the four transistors thus, no matter how lare the current difference between node a and b is, ΔZ will be zero. This unique property of cross-coupled PMOS current conveyor is referred as Zero differential impedance. However, real implementation of this current conveyor, especially short channel device technoloy, the Zero differential impedance is difficult to achieve. To see zero differential impedance we have to consider ate source capacitance C s. The put impedance z becomes z ( sc s s ( s3 s ) ( m4 sc s s3 ) s4 m )( At f 0, z can be simplified to z m4 m4 m (7) s ) (6) From (7), the zero put impedance obtaed by perfect cancellation the numerator. But presence of C s (6) or other parasitic effect, + 38

4 ISSN 348-7X May 04 body effect, process variations and other factors make difficult to achieve zero put impedance reality. B. Cross-Coupled Current Conveyor Input Stae To des a cross-coupled current conveyor based differential TIA, we first need a differential put sal. However, differential photodiode is not available. Therefore, we des with a sle ended photocurrent, the unused put termal is loaded with the same capacitance as that of the true put termal. To obta the balanced put impedance, we can connect either a dummy photodiode kept the dark or a capacitor provid the same parasitic effect as the photodiode. This is termed as a balanced-tia [5], [4]. The cross-coupled current conveyor put stae for broadband TIA is then illustrated Fi. (a), where NMOS transistors are used for speed improvement over PMOS transistors. It is reasonable to assume that transistors M and M of cross-coupled pair have the same transconductance denoted as. (b) (c) Fi.. Proposed Cross Coupled Current Input Stae. (a) Circuit Schematic. (b) Equivalent Input Impedance Schematic. (c) Small Sal Analysis Model. Similarly, transistors M 3 and M 4 also have the same transconductance denoted as. Accord to the small-sal analysis model illustrated Fi. (b) and (c), the low frequency put impedance at the source of M is iven by i (a) r i r i where (8) V test itest m R 3 c sc (9) R c R // PD m 39

5 ISSN 348-7X May 04 In this des, R is chosen to be the rane of several hundred ohms, and C PD has a value of 0.5 pf, R c is the rane of several tens of ohms. From (8), it can be seen that r i can be adjusted to zero when transistors M and M 3 are properly biased to fulfill the follow equation : R c (0) The put impedance seen by i is the parallel impedance of C PD, R, and ri. As R is the order of hundred ohms, which is much larer than r i, the time constant at the put node is C PD r i. If the above condition (0) is fulfilled, ideally the put node would have fite bandwidth frequency response. Aa, exact zero put impedance is impractical to realize sce there is always a small discrepancy between the two puts of the crosscoupled structure due to a sle-ended supply current, and the value of Rc is frequency dependent. In addition as mentioned Section II-A, zero put impedance is hard to obta real implementation sce (8) nelects all the parasitic impedance, which can be sificant at hih frequency. Another consideration is that the zero put impedance may become neative impedance due to various undesirable effects, such as short-channel effect of transistors, variations of component values, or variations caused by physical layout. The amplifier may, therefore, become an oscillator. Thus, it is better to des R c slihtly larer than to compensate all the possible variations the practical des. The result r i described by (8) can be much smaller than the CG counterpart, which is usually the reciprocal of. In this way, the proposed put stae deed presents very low put impedance, which is low enouh to cope with the hih speed TIA requirements. With such a low put 40 impedance, the domant pole of this crosscoupled current conveyor-based TIA is located with the amplifier rather than at the put node. On the other hand, the cross-coupled structure of the current conveyor raises the circuit complexity by troduc additional poles and zeros. A small sal analysis yields () (6) of the summed currents at the respective circuit nodes S, D(S3), D3, D(S4), S, and D4 i (Y p + + ds +jωc s )V s ( +jωc s )V Y ds V x () 0 ( jωc d jωc d )V Y ( + ds )V S + ( ds + + ds3 +jωc s3 +jωc d +jωc d )V X ds3 V D3 jωc s V S () ( + ds ) V x (Y + jωc d3 + ds ) V D3 (3) 0 (jωc s4 + jωc s + jωc d + jωc d + ds4 + m4 + ds ) V Y jωc s V S - (jωc d m + jωc d )V X ds4 V D4 ( ds + m )V S (4) 0 ds V Y ( ds + m + Y P +jωc s )V S + ( m +jωc s )V X (5) ( ds4 + m4 )V Y ( ds4 + Y + jωc d4 ) V D4 (6) where mx is the ate-source transconductance, dsx is the output conductance, C sx is the atesource capacitance, and C dx is the ate-dra capacitance of transistor M x. The parameter Y denotes the admittance of resistor R, and Y p denotes the admittance of C PD parallel with R. For simplicity, dsx can be nelected sce mx is

6 ISSN 348-7X May 04 much reater than dsx, and Y is much reater than dsx. The existence of more than one path between the put and the output node usually creates a zero the transfer response []. By mathematical manipulations, the above six equations yield the follow transfer function for this cross-coupled current conveyor The complete transimpedance amplifier with ductive peak technique based on cross coupled current conveyor put stae is shown Fi. 3. V X H (0) R ( m R ) i R ( R ) ( ) (7) H (0) V X i m R ( m R ) ( ) R (8) VD H POV (0) 3 i m m 3R ( RR ( m R ) R ) ( ) (9) H ne (0) VD 4 i R R (0) R ( R ) ( m ) In (7) and (8), if ( ) is much smaller than the first term the denomator, we can further simplify them to v 3 H POV (0) D R () i H ne (0) v i R R D4 () From () and (), we can observe that the transimpedance at positive and neative outputs are different, which causes two output sals to have different sw manitudes. III. Proposed TIA with Inductive Peak Fi. 3. Proposed TIA Schematic It is the composition of four staes, namely a current conveyor put stae [3], an ter-stae source follower, a a stae with ductive peak technique[7], and output stae. The last stae of the TIA circuit is a source follower to offer a 50Ω output impedance match for measurement purposes. purpose. Aa the pole at last stae will not derade the overall performance so that the size of transistor at output stae select carefully. This shunt ductive peak is a well known technique for bandwidth enhancement [4]. An ductor is serted series with the load resistor that cancel out the deteriorat effect of bandwidth caused by the pole at last stae. The shunt-ductive peak technique here helps to enhance the tareted bandwidth. It also helps to reduce the combed effect of poles at hiher frequency. Besides boost the bandwidth shunt peak also 4

7 ISSN 348-7X May 04 improves the roll off characteristics[5]. By us on-chip spiral ductor bandwidth is creased up to 47%[]. IV. Result and Discussion The proposed TIA has been implemented 0.- µm.-v IC CMOS technoloy.l and L are implemented us on-chip spiral ductors for the purpose of monolithic implementation and area efficiency. The total power consumption of the circuit is 4. mw. To accurately demonstrate the capability of accommodat PD capacitance 0.5pF capacitor have been terated on the chip. Fi.4. Measured Transimpedance Ga of the Proposed TIA Des the put node. As shown (7), as the junction capacitance of photodiode C PD creases, R c will decrease and r i (8) will decrease accordly. Therefore, the time constant at the put load with creas C PD can still keep at a low value sce r i is mov the opposite direction. This property makes the usae of lare area photodiodes possible sce the TIA performance will not be that sensitive to the variations of C PD. With a larer area photodiode, a better sal power can be capture with acceptable deradation of the bandwidth [5]. Table I summarizes a detailed performance comparison of the proposed TIA with several other CMOS TIA des. The proposed TIA des has an apparent advantae power consumption. The lare improvement bandwidth is obtaed by implement hih Q ductor. Fi. 6 shows the power dissipation of TIA. A constant power dissipation of 4.mW over a wide rane of frequency after that the total power dissipation is slihtly creased. The advantae low power dissipation makes the proposed TIA an excellent candidate for hih speed, lare bandwidth and low power application. Fi.4 shows the measure a is 55.5dBΩ and 3- db frequency is.5 GHz, has maximum output sw is 6.8 mv. With 3-dB bandwidth, the proposed TIA is well suitable to optical fiber lk application, which needs wide dynamic rane requirement. One of the advantae of this cross-coupled current conveyor based TIA is its capability to tolerate lare variations of total capacitive load at Fi.5. Transient Simulation of Output Sal 4

8 ISSN 348-7X May 04 TABLE I: Performance Comparison of CMOS TIAs Technoloy [5] [5] [] 0.8- µm CM OS 0.8- µm SiGe BiCMO S 0.8- µm CMO S This Des 0.- µm CMOS C PD (pf) Ga(dBΩ) Bandwidth( GHz) Power consumptio n (mw) 6 Sl e struct ure 53.9 Differe ntial structur e 46 sl e- ende d 55.5 Differe ntial structur e With buffe r 70. Without buffer 9.6 With out buffe r 0.7 Without Buffer 4. V. Conclusion Transimpedance Amplifier with Inductive Peak Technique based on Cross-Coupled Current conveyor is proposed this paper. Crossed-coupled current conveyor stae provides very low put impedance, relax the bandwidth limitation at the put node and also facilitates the construction of a differential TIA circuit as well. Employ the ductive peak technique CMOS TIA reported here achieves a of 55.5 dbω with bandwidth of.5 GHz. The measured result shows that the proposed technique of bandwidth extension can improve bandwidth performance sificantly. The proposed bandwidth extension technique is suitable for CMOS devices to achieve broadband and low power characteristics simultaneously. References [] T. Koonen, Fiber to the home/fiber to the premises: What, where, and when?" Vol. 94, no. 5, pp , May Fi. 6 Power Dissipation [] A. Tzanakaki, Broadband build blocks [optical networks], Circuits and Devices Maaze, IEEE, Vol.0, no., pp. 3 37, Apr 004. [3] V. Ramamurti, J. Siwko, G. Youn, and M. Pepe, Initial implementations of pot-to-pot ethernet over SONET/SDH transport, IEEE Commun. Ma., Vol. 4, no. 3, pp , Mar [4] M. A. M. Madureira, P. M. P. Monteiro, R. L. Auiar, M. Violas, M. Gloance, E. Leclerc, and B. Lefebvre, Hih a GaAs 0 Gb/s transimpedance amplifier with terated bondwire effects, Proc. Int. Symp. Circuits Syst., Vol., pp Jun. 003.

9 ISSN 348-7X May 04 [5] E. Säcker, Broadband Circuits for Optical Fiber Communication New York: Wiley, 004. [6] F. Yuan, Low- voltae CMOS currentmode preamplifier: Analysis and des, IEEE Trans. Circuits Syst. I, Re. Papers, Vol. 53, no., pp.6 39, Jan [7] Chien Fen-Tso and Chan Yi-Jen, Bandwidth Enhancement of Transimpedance Amplifier by a Capacitive-Peak Des, IEEE Journal of Solid-State Circuits, Vol. 34, no. 8, pp , Auust 999. [8] Sunderarajan S. Mohan, Maria del Mar Hershenson, and Thomas H. Lee, Bandwidth Extension CMOS with Optimized On-Chip Inductors, IEEE Journal Of Solid-State Circuits, Vol. 35, No. 3, pp , March 000. [9] Rezaul Hasan, S. M. Des of a Low- Power 3.5 GHz Broad-Band CMOS Transimpedance Amplifier for Optical Transceivers, IEEE Transactions On Circuits And Systems I: Reular Papers, Vol. 5, No. 6, pp , June 005. [0] Chen Wei-Zen and Lu Chao-Hs, Des and Anaylsis of A.5-Gbps Optical Receiver Analo Front-End a 0.35-µm Diital CMOS Technoloy, IEEE Transactions on Circuits and Systems i: reular papers, vol. 53, no. 4, pp , April 006. [] E. S. A. M. Hasaneen, M. A. A. Wahab, and N. Okaley, Bandwidth extension of CMOS transimpedance amplifier us on-chip spiral ductor, Proc. nd Int. Des Test Workshop, pp , 007. IEEE Transactions, Vol., no. 8, pp , Au. 03. [3] Y. K. Sen, New current conveyor for hih-speed low-power current sens, IEE Proc.-Circuits, Devices Syst., Vol. 45, no., pp , Apr [4] B. Razavi, Des of Interated Circuits for Optical Communications, New York: McGraw-Hill, 003. [5] C.-H. Wu, C.-H. Lee, and S.-I. Liu, CMOS wideband amplifiers us multiple ductive-series peak technique, IEEE J. Solid-State Circuits, Vol. 40, no., pp , Feb [6] S. Goswami, T. Copani, B. Vermeire, and H. Barnaby, BW extension shunt feedback transimpedance amplifier us neative miller capacitance, Proc. IEEE Int. Symp. Circuit Syst, pp , Jun [] Dandan Chen, and Kiat Sen Yeo, Cross-Coupled Current Conveyor Based CMOS Transimpedance Amplifier for Broadband Data Transmission, Very Lare Scale Interation (VLSI) Systems, 44