ECE 902. Modeling and Optimization of VLSI Interconnects

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1 ECE 90 Modelig ad Optimizatio of VLSI Itercoects ( Istructor: Lei He Office: EH343 Telephoe: Office hour: TR :30-3pm Course Prerequisites No official prerequisites Maily self-cotaied Kowledge to help you appreciate more ECE30 Electrodyamics ECE555/755 Digital Circuits ad Compoets CS577 Itroductio to Algorithms

2 Refereces Cog et al., Performace Optimizatio of VLSI Itercoect Layout, Itegratio, the VLSI Joural ( Selected papers from TCAD, TODAES, ad major CAD cofereces such as DAC, ICCAD ad ISPD H. Bakoglu, Circuits, Itercoects, ad Packagig for VLSI, Addiso Wesley J. Rabaey, Digital Itegrated Circuits: A Desig Perspective, Pretice Hall Related VLSI CAD Cofereces ad Jourals ACM IEEE Desig Automatio Coferece (DAC Iteratioal Coferece o Computer Aided Desig(ICCAD IEEE Iteratioal Symposium o Circuits ad Systems (ISCAS Desig, Automatio ad Test i Europe (DATE Asia ad South Pacific Desig Automatio Coferece (ASP- DAC Iteratioal symposium o physical desig (ISPD IEEE Trasactios o CAD of Circuits ad systems (TCAD ACM Tras. o Desig Automatio of Electroic Systems (TODAES IEEE Trasactios o Circuits ad Systems (TCAS IEEE Tras. o VLSI Systems (TVLSI

3 Gradig Policy Homework 0% Quiz 0% Paper presetatio 5% Use trasparecies or video projector Graded by fellow studets Term project 45% Bous poits For active participatio Grade A for score > 85 Term Project Oe of the followig: Survey of selected papers ( perso, at most 40 poits Programmig project ( persos i a term Web-based bus modelig ad optimizatio A CAD tool to perform repeater plaig durig floor plaig Or a topic agreed by istructor Writig requiremets I a coferece paper style

4 Course Outlie Overview ad Itroductio ( lecture Itercoect Extractio ad Modelig (3 lectures Itercoect Delay Modelig (3 lectures Device Optimizatio (3 lectures Itercoect Topology Optimizatio ( lectures Itercoect Sizig ( lectures Simultaeous Device ad Itercoect Optimizatio ( lecture Itercoect Estimatio ad Plaig Course Outlie Noise Modelig, Avoidace ad Cotrol (4 lectures Itercoect Power Model ad Reductio (3 lectures System-level Itercoect Predictio ** ( lecture O-chip bus desig** ( lecture

5 Course Schedule Lectures oly o Wedesdays for the first two weeks i.e., lecture give by TA o Sept. th Meet Sept. 9 th ad st Meet three times a week startig Sept. 4 th Projects assiged o later tha Nov. 7 th Start to meet twice a week the Term report due o the last day of this semester With a grace period of two days Skills to Lear Itercoect modelig ad desig Programmig / writig / presetatio

6 Overview Moore s Law CMOS scalig theory Itercoect performace implied by NTRS 97 Need for a ew desig paradigm Basic Compoets I VLSI Circuits Devices Pad Via Meta l Metal u Trasistors u Logic gates ad cells u Fuctio blocks Itercoects sigals u Global sigals u Clock sigals u Power/groud etworks Data Path PLA I/O ROM/RAM u Local Radom logic A/D Coverter

7 Determiig Factors of System Performace Combiatioal Logic Clock Period Storage elemet t d-gates + t d-itercoects + t skew + t su + t ds t d-gates = gate delay i comb. logic t d-itercoects } = itercoect delay i comb. logic t skew = clock skew t su = set-up time t ds = delay withi storage elemets Itercoect delay Importace of VLSI Itercoect Desig Techology Treds: Deep sub-micro desig: < 0.8 micro CMOS techology High-Speed : Impact o VLSI System Desig > 500 MHz ~ 5 GHz Itercoect delay becomes the domiatig factor i system performace ocosumes 50%-70% clock cycle Distributed ature of itercoects becomes sigificat obecomes distributed RCL circuits or lossy trasmissio lies. Itercoect-Drive Desig

8 Moore s Law ad NTRS Moore s Law The mi. trasistor feature size decreases by 0.7X every three years (Electroics Magazie, Vol. 38, April 965 True i the past 30 years! Natioal Techology Roadmap for Semicoductors (NTRS 97 Techology (um Year # trasistors M M 40M 76M 00M 50M O-Chip Clock (MHz Area (mm Wirig Levels Ideal Scalig of MOS Trasistors W S G D X j t gox L eff B Figure. Metal-Oxide-Semicoductor Field-Effect Trasistor (MOSFET. The mai dimesios that determie device properties are gate oxide thickess t gox ; gate legth L, gate width W; ad juctio depth X j Assumptios: aall horizotal & vertical dimesios of a trasistor( W, L, t gox, X j are reduced by S aall voltages ( V oo, V TN, V TP are reduced by S asubstrate dopig (N sub is icreased by S a(v TN, V TP : threshold voltages of N ad P trasistors

9 TABLE. Scalig of MOS Trasistors Parameter Scalig Factor Dimesios Dimesios (W, (W, L, L, t t gox, j gox, X j Substrate Substrate dopig dopig (N (N SUB SUB S Voltages Voltages (V (V DD, TN, TP DD, V TN, V TP ox Curret per device (IDS W åox (VDD Curret per device (I DS t (VDD VT gox L tgox WL Gate capacitac e (Cg oxwl (VDD Gate capacitac e (C g = åox t (VDD VT gox tgox DD Trasistor o - resistace (Rtr VDD Trasistor o - resistace (R tr I DS IDS g Itrisic date delay (ô Cg V g Itrisic date delay (ô = I = RtrC g av Iav Power-dissipatio Power-dissipatio per per gate gate (P=IV (P=IV Power Power -delay -delayproduct per per gate gate (P (P ô ô 3 3 Area Area per per device device (A=WL (A=WL Power-dissipatio Power-dissipatio desity desity (P/A (P/A Curret Through a -chael MOS Trasistor I DS Liear V DS = V GS -V t V GS o FIGURE. I-V characteristics of a MOS trasistor Ios= â [( ] Vgs Vt Vos Vos/ ( V V â V V gs ds V V t gs V t (Cut-off gs t = Vds Vgs Vt w â = ì.c gox. L Gai Factor electro mobility å ô ox gox V DS (Liear i terms of V GS (Saturatio, idepedet of V DS geometric dimetsios of the trasistor

10 Ideal Scalig of VLSI Itercoects w sp wit Hit l it t ox Figure. Basic itercoectio parameters Assumptios: a Cross Sectioal dimesios ( Wit, Hit, Wsp, Tox are reduced by S a Die Size ad global itercoectio Legths are icreased by S c Table. Scalig of Local ad Global Itercoectios Parameter Scalig Factor Cross Cross sectioal sectioal Dimesios Dimesios (W (W it, it, sp, t ox it, H it, W sp, t ox uit legth (Rit it Resistaceper uit legth (R it = ñit it W S ith it S it Capacitac e per uit legth (Cit εoxw it Capacitac e per uit legth (C it = εox t ox tox RC RC costat costat per per uit uit legth legth (R (R it it S it C it S Local Local itercoectio itercoectio RC RC delay delay (l (l loc loc Local itercoe ctio RCdelay (Rit itl Local itercoe ctio RCdelay (R itc itl loc loc Die Die size size (D (D C C SS C C Global Global itercoectio itercoectio legth legth (l (l it it Global itercoe ctio RC delay (Rit itl Global itercoe ctio RC delay (R it itcitl it SS C C SS (S (S C C Trasistor Trasistor lie lie time time of of flight flight (l (l it /v c it /v c S C S C

11 Local Itercoects uder Differet Scalig Rules Table 5. Scalig of Local Itercoectios Parameter Ideal Ideal Qussi-Ideal Costat-R Geeralized Scalig Scalig Scalig Scalig / / S / / S / / S / / S / / S / / S Thickess Thickess (H (H it it H H Width Width (W (W it it W W Separatio Separatio (W (W sp sp sp sp Isulator Isulator thickess thickess (t (t ox ox ox ox Legth Legth (l (l loc loc Resistace Resistace (R (R it S S W S H /S it S S S W S H /S Capacitace Capacitace to to substrate substrate 3/ 3/ S S ox /SS W ox /SS W Capacitace betwee lies / Capacitace betwee lies / S S S sp /SS H sp /SS H RC delay (T / W H/S RC delay (T / S SW SH/S Voltage Voltage drop drop (IR (IR / S W S H /S / S S W S H /S Curret Curret desity desity (J (J S S W S H /S S S S W S H /S ot good for packig desity Global Itercoects uder Differet Scalig Rules Table 5. Scalig of Global Itercoectios Parameter Parameter Ideal Ideal Costat Costat Costat Costat Geeralized Scalig Scalig Dimesio Dimesio Delay Delay Scalig Scalig Thickess Thickess (Hit (Hit S C S C H H Width Width (Wit (Wit SC SC W W Separatio Separatio (Wsp (Wsp S C S C sp sp Isulator Isulator thickess thickess (t (t ox ox S C S C ox ox Legth (lloc SC SC SC SC Legth (lloc SC SC SC SC Resistace (R it S S C SC C S WSHS C Resistace (R it S S C SC C S WSHS C Capacitace (C it S C SC S C SC Capacitace (C it S C SC S C SC RC RC delay delay (T (T S (SC (SC SWS H(SC S (SC (SC SWS H(SC /S S S /S S: Scalig factor for device dimesios. S c :Scalig factor for chip size

12 Itercoect Parameters from NTRS 97 Techology (um Res. r (uw/cm Dielectric costat Mi. wire width Mi. wire spacig Metal aspect ratio.8:.8:.0:.:.4:.7: Via aspect ratio.:.:.4:.5:.7:.9: Vdd (V Capacitace Computatio C x C a C f Capacitace extractio usig a 3D field solver (FastCap

13 Derived Itercoect & Device Parameters Techology (um X mi. Ca (af/um width & Cf (af/um spacig Cx(aF/um X mi. Ca (af/um width & Cf (af/um spacig Cx(aF/um Buffer iput cap. (ff Buffer Rd (x0kw Buffer itri. delay (ps Impact of Itercoect Optimizatio o Future Techology Geeratios 0 mm cm DS Delay (s 0. cm BIS cm BISWS Itrisic gate delay Techology (u m

14 Impact of Itercoect Optimizatio o Future Techology Geeratios Techology (um mm (s cm DS (s cm BIS (s cm BISWS (s Sigificace of Couplig Capacitace Cx/Ctotal Mi. Spacig x Mi. Spacig Techology Geeratio (um

15 Couplig Noise Noise (% Vdd a pair of i-phase aggressors oe aggressor a pair of skewed Couplig oise from Techology two adjacet (m aggressors to the middle victim wire with x mi. spacig. Rise time is 0% of project clock period. Capacitive couplig depeds strogly o both spatial ad temporal relatios! Implicatios Commuicatio is more expesive tha computatio Itercoect performace has become the bottleeck of the overall circuit/system performace Itercoect modelig ad optimizatio has become very difficult due to the distributed ature of itercoects ad their spatial ad temporal iteractios A ew desig paradigm/flow is eeded to hadle itercoect-domiated desigs i the future

16 VLSI Desig Cycle System Specificatio Fuctioal Desig Logic Desig X=(AB*CD+(A+D+(A(B+C Y=(A(B+C+AC+D+A(BC+D Circuit Desig VLSI Desig Cycle (cot. Physical Desig Fabricatio Packagig

17 Need A New Paradigm for VLSI Desig Itercoectio Trasistors/Cells Trasistors/Cells Itercoectio Covetioal Approach New Approach Itercoect-Drive Desig Paradigm Chage i Software Desig Data Program Program Data/Object Covetioal Approach New Approach Data Base Desig Object-orieted desig

18 Summary Techology scalig accordig to Moore s Law has bee the drivig force behid the expoetial growth of the semicoductor idustry Itercoect (esp. global itercoect performace ad oise have become the bottleeck of the overall system desig Itercoect modelig ad optimizatio has become very importat, yet difficult A ew desig paradigm is eeded for itercoectdrive (or itercoect-cetric desig Homework (due Sept. 0 th outside EH343 Read ITRS 99 ORTC ad Itercoect (999 editio ORTC: overall roadmap techology characteristics Fid two categories of differeces betwee NTRS 97 (i this otes ad ITRS 99 itercoect characteristics, ad explai reasos for such chages A ope book quiz will be scheduled based o ITRS ORTC ad itercoect

(2) The MOSFET. Review of. Learning Outcome. (Metal-Oxide-Semiconductor Field Effect Transistor) 2.0) Field Effect Transistor (FET)

(2) The MOSFET. Review of. Learning Outcome. (Metal-Oxide-Semiconductor Field Effect Transistor) 2.0) Field Effect Transistor (FET) EEEB73 Electroics Aalysis & esig II () Review of The MOSFET (Metal-Oxide-Semicoductor Field Effect Trasistor) Referece: Neame, Chapter 3 ad Chapter 4 Learig Outcome Able to describe ad use the followig: