RAD-Hard HEXFET SURFACE MOUNT (LCC-28)

Transcription

1 IRHQ567 RADIATION HARDENED V, Combiatio 2N-2P-CHANNEL POWER MOSFET RAD-Hard HEXFET SURFACE MOUNT (LCC-28) 5 PD-9457D TECHNOLOGY Product Summary Part Number Radiatio Level RDS(o) ID CHANNEL IRHQ567 K Rads (Si).27Ω 4.6A N IRHQ563 3K Rads (Si).29Ω 4.6A N IRHQ567 K Rads (Si).96Ω -2.8A P IRHQ563 3K Rads (Si).98Ω -2.8A P Iteratioal Rectifier s RAD-Hard TM HEXFET MOSFET Techology provides high performace power MOSFETs for space applicatios. This techology has over a decade of prove performace ad reliability i satellite applicatios. These devices have bee characterized for both Total Dose ad Sigle Evet Effects (SEE). The combiatio of low RDS(o) ad low gate charge reduces the power losses i switchig applicatios such as DC to DC coverters ad motor cotrol. These devices retai all of the well established advatages of MOSFETs such as voltage cotrol, fast switchig, ease of parallelig ad temperature stability of electrical parameters. LCC-28 Features: Sigle Evet Effect (SEE) Hardeed Low RDS(o) Low Total Gate Charge Simple Drive Requiremets Ease of Parallelig Hermetically Sealed Ceramic Package Surface Mout Light Weight ESD Ratig: Class A per MIL-STD-75, Method 2 Absolute Maximum Ratigs (Per Die) Parameter N-Chael P-Chael Uits VGS = ±2V, TC = 25 C Cotiuous Drai Curret VGS = ±2V, TC = C Cotiuous Drai Curret IDM Pulsed Drai Curret À TC = 25 C Max. Power Dissipatio 2 2 W Liear Deratig Factor.. W/ C VGS Gate-to-Source Voltage ±2 ±2 V EAS Sigle Pulse Avalache Eergy 47 Á 7 ² mj IAR Avalache Curret À A EAR Repetitive Avalache Eergy À.2.2 mj dv/dt Peak Diode Recovery dv/dt 6. Â - 7. ³ V/s TJ Operatig Juctio -55 to 5 TSTG Storage Temperature Rage C For foototes refer to the last page Pckg. Moutig Surface Temp. 3 (for 5s) Weight.89 (Typical) g 5//5 A

2 IRHQ567 Electrical Characteristics For Each N-Chael Tj = 25 C (Uless Otherwise Specified) Parameter Mi Typ Max Uits Test Coditios BVDSS Drai-to-Source Breakdow Voltage V VGS = V, ID =.ma BVDSS/ TJ Temperature Coefficiet of Breakdow.3 V/ C Referece to 25 C, ID =.ma Voltage RDS(o) Static Drai-to-Source O-State.3 VGS = 2V, ID = 4.6A Resistace.27 Ω VGS = 2V, ID = 2.9A Ã VGS(th) Gate Threshold Voltage V VDS = VGS, ID =.ma gfs Forward Trascoductace 3.3 S VDS = 5V, IDS = 2.9A Ã IDSS Zero Gate Voltage Drai Curret VDS = 8V, VGS = V µa 25 VDS = 8V, VGS = V, TJ = 25 C IGSS Gate-to-Source Leakage Forward VGS = 2V A IGSS Gate-to-Source Leakage Reverse - VGS = -2V Qg Total Gate Charge 3 VGS = 2V, ID = 4.6A Qgs Gate-to-Source Charge 4. C VDS = 5V Qgd Gate-to-Drai ( Miller ) Charge 3.9 td(o) Tur-O Delay Time 2 VDD = 5V, ID = 4.6A, tr Rise Time 24 VGS = 2V, RG = 7.5Ω s td(off) Tur-Off Delay Time 32 tf Fall Time 9 LS + LD Total Iductace 6. H Measured from the ceter of drai pad to ceter of source pad Ciss Iput Capacitace 37 VGS = V, VDS = 25V Coss Output Capacitace 8 pf f =.MHz Crss Reverse Trasfer Capacitace 3. Source-Drai Diode Ratigs ad Characteristics (Per Die) Parameter Mi Typ Max Uits Test Coditios IS Cotiuous Source Curret (Body Diode) 4.6 ISM Pulse Source Curret (Body Diode) À 8.4 A VSD Diode Forward Voltage.2 V Tj = 25 C, IS = 4.6A, VGS = V Ã trr Reverse Recovery Time 73 s Tj = 25 C, IF = 4.6A, di/dt A/µs QRR Reverse Recovery Charge 863 C VDD 5V Ã to Forward Tur-O Time Itrisic tur-o time is egligible. Tur-o speed is substatially cotrolled by LS + LD. Thermal Resistace (Per Die) Parameter Mi Typ Max Uits Test Coditios RthJC Juctio-to-Case.8 C/W RthJA Juctio-to-Ambiet 6 Typical socket mout Note: Correspodig Spice ad Saber models are available o Iteratioal Rectifier Website. For foototes refer to the last page 2

3 IRHQ567 Electrical Characteristics For Each P-Chael Tj = 25 C (Uless Otherwise Specified) Parameter Mi Typ Max Uits Test Coditios BVDSS Drai-to-Source Breakdow Voltage - V VGS = V, ID = -.ma BVDSS/ TJ Temperature Coefficiet of Breakdow -.3 V/ C Referece to 25 C, ID = -.ma Voltage RDS(o) Static Drai-to-Source O-State.2 Ω VGS = -2V, ID = -2.8A Ã Resistace.96 VGS = -2V, ID = -.8A VGS(th) Gate Threshold Voltage V VDS = VGS, ID = -.ma gfs Forward Trascoductace.6 S VDS = -5V, IDS = -.8A Ã IDSS Zero Gate Voltage Drai Curret - VDS= -8V, VGS=V µa -25 VDS = -8V, VGS = V, TJ = 25 C IGSS Gate-to-Source Leakage Forward - VGS = -2V A IGSS Gate-to-Source Leakage Reverse VGS = 2V Qg Total Gate Charge VGS = -2V, ID = -2.8A Qgs Gate-to-Source Charge 3. C VDS = -5V Qgd Gate-to-Drai ( Miller ) Charge 4.2 td(o) Tur-O Delay Time 2 VDD = -5V, ID = -2.8A, tr Rise Time 24 VGS = -2V, RG = 7.5Ω s td(off) Tur-Off Delay Time 32 tf Fall Time 9 LS + LD Total Iductace 6. H Measured from the ceter of drai pad to ceter of source pad Ciss Iput Capacitace 377 VGS = V, VDS = -25V Coss Output Capacitace 2 pf f =.MHz Crss Reverse Trasfer Capacitace 7. Source-Drai Diode Ratigs ad Characteristics (Per Die) Parameter Mi Typ Max Uits Test Coditios IS Cotiuous Source Curret (Body Diode) -2.8 ISM Pulse Source Curret (Body Diode) À -.2 A VSD Diode Forward Voltage -5. V Tj = 25 C, IS = -2.8A, VGS = V Ã trr Reverse Recovery Time 38 s Tj = 25 C, IF = -2.8A, di/dt -A/µs QRR Reverse Recovery Charge 555 C VDD -5V Ã to Forward Tur-O Time Itrisic tur-o time is egligible. Tur-o speed is substatially cotrolled by LS + LD. Thermal Resistace (Per Die) Parameter Mi Typ Max Uits Test Coditios RthJC Juctio-to-Case.8 C/W RthJA Juctio-to-Ambiet 6 Typical socket mout For foototes refer to the last page 3

4 IRHQ567 Iteratioal Rectifier Radiatio Hardeed MOSFETs are tested to verify their radiatio hardess capability. The hardess assurace program at Iteratioal Rectifier is comprised of two radiatio eviromets. Every maufacturig lot is tested for total ioizig dose (per otes 5 ad 6) usig the TO-3 package. Both pre- ad post-irradiatio performace are tested ad specified usig the same drive circuitry ad test coditios i order to provide a direct compariso. Table. Electrical Characteristics For Each N-Chael Tj = 25 C, Post Total Dose Irradiatio ÄÅ Parameter K Rads(Si) 3K Rads (Si) 2 Uits Test Coditios Mi Max Mi Max BV DSS Drai-to-Source Breakdow Voltage V V GS = V, I D =.ma VGS(th) Gate Threshold Voltage VGS = V DS, I D =.ma I GSS Gate-to-Source Leakage Forward A V GS = 2V I GSS Gate-to-Source Leakage Reverse - - V GS = -2 V I DSS Zero Gate Voltage Drai Curret µa V DS = 8V, V GS =V R DS(o) Static Drai-to-Source Ã Ω VGS = 2V, I D = 2.9A O-State Resistace (TO-39) R DS(o) Static Drai-to-Source Ã Ω VGS = 2V, I D = 2.9A O-State Resistace (LCC-28) V SD Diode Forward Voltage Ã.2.2 V V GS = V, IS = 4.6A. Part umber IRHQ Part umber IRHQ563 Iteratioal Rectifier radiatio hardeed MOSFETs have bee characterized i heavy io eviromet for Sigle Evet Effects (SEE). Sigle Evet Effects characterizatio is illustrated i Fig. a ad Table 2. Table 2. Typical Sigle Evet Effect Safe Operatig Area (Per Die) LET Eergy Rage VDS (V) (MeV/(mg/cm 2 )) (MeV) = V -5V -V -5V -2V 38 ± 5% 3 ± 7.5% 38 ± 7.5% 6 ± 5% 33 ± 7.5% 3 ± % ± 5% 35 ± % 28 ± 7.5% Bias VDS (V) Bias VGS (V) -5-2 LET=38 ± 5% LET=6 ± 5% LET=84 ± 5% For foototes refer to the last page Fig a. Typical Sigle Evet Effect, Safe Operatig Area 4

5 IRHQ567 Iteratioal Rectifier Radiatio Hardeed MOSFETs are tested to verify their radiatio hardess capability. The hardess assurace program at Iteratioal Rectifier is comprised of two radiatio eviromets. Every maufacturig lot is tested for total ioizig dose (per otes 5 ad 6) usig the TO-3 package. Both pre- ad post-irradiatio performace are tested ad specified usig the same drive circuitry ad test coditios i order to provide a direct compariso. Table. Electrical Characteristics For Each P-Chael Tj = 25 C, Post Total Dose Irradiatio Š Parameter K Rads(Si) 3K Rads (Si) 2 Uits Test Coditios Mi Max Mi Max BV DSS Drai-to-Source Breakdow Voltage - - V V GS = V, I D = -.ma VGS(th) Gate Threshold Voltage VGS = V DS, I D = -.ma I GSS Gate-to-Source Leakage Forward - - A V GS = -2V I GSS Gate-to-Source Leakage Reverse V GS = 2 V I DSS Zero Gate Voltage Drai Curret - - µa V DS = -8V, V GS =V R DS(o) Static Drai-to-Source Ã Ω VGS = -2V, I D = -.8A O-State Resistace (TO-39) R DS(o) Static Drai-to-Source Ã Ω VGS = -2V, I D = -.8A O-State Resistace (LCC-28) V SD Diode Forward Voltage à V V GS = V, IS = -2.8A. Part umber IRHQ Part umber IRHQ563 Iteratioal Rectifier radiatio hardeed MOSFETs have bee characterized i heavy io eviromet for Sigle Evet Effects (SEE). Sigle Evet Effects characterizatio is illustrated i Fig. a ad Table 2. Table 2. Typical Sigle Evet Effect Safe Operatig Area (Per Die) LET Eergy Rage VDS (V) (MeV/(mg/cm 2 )) (MeV) = V 5V V 5V 2V 38 ± 5% 27 ± 7.5% 35 ± 7.5% ± 5% 33 ± 7.5% 3 ± 7.5% ± 5% 35 ± 7.5% 28 ± 7.5% Bias VDS (V) Bias VGS (V) LET=38 ± 5% LET=6 ± 5% LET=84 ± 5% For foototes refer to the last page Fig a. Typical Sigle Evet Effect, Safe Operatig Area 5

6 IRHQ567 N-Chael Q,Q4 I D, Drai-to-Source Curret (A) VGS TOP 5V 2V V 9.V 8.V 7.V 6.V BOTTOM 5.V 5.V I D, Drai-to-Source Curret (A) VGS TOP 5V 2V V 9.V 8.V 7.V 6.V BOTTOM 5.V 5.V 2µs PULSE WIDTH. T J = 25 C. V DS, Drai-to-Source Voltage (V) 2µs PULSE WIDTH. T J = 5 C. V DS, Drai-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics I D, Drai-to-Source Curret (A) T J = 5 C T J = 25 C V DS= 25V 2µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) R DS(o), Drai-to-Source O Resistace (Normalized) 2.5 I D = 4.6A V GS = 2V T J, Juctio Temperature ( C) Fig 3. Typical Trasfer Characteristics Fig 4. Normalized O-Resistace Vs. Temperature 6

7 I D, Drai-to-Source Curret (A) IRHQ567 N-Chael Q,Q4 C, Capacitace (pf) 8 VGS = V, f = MHz Ciss = Cgs + Cgd, C ds SHORTED Crss = Cgd Coss = Cds + Cgd 6 C iss 4 C oss 2 C rss V DS, Drai-to-Source Voltage (V) V GS, Gate-to-Source Voltage (V) I = D 4.6A V DS = 8V V DS = 5V V DS = 2V FOR TEST CIRCUIT SEE FIGURE Q G, Total Gate Charge (C) Fig 5. Typical Capacitace Vs. Drai-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage I SD, Reverse Drai Curret (A) T J = 5 C T J = 25 C V GS = V V SD,Source-to-Drai Voltage (V). Tc = 25 C Tj = 5 C Sigle Pulse OPERATION IN THIS AREA LIMITED BY R DS (o) ms ms V DS, Drai-toSource Voltage (V) Fig 7. Typical Source-Drai Diode Forward Voltage Fig 8. Maximum Safe Operatig Area 7

8 IRHQ N-Chael Q,Q4 V DS R D I D, Drai Curret (A) Fig a. Switchig Time Test Circuit V DS 9% R G V GS V GS Pulse Width µs Duty Factor. % D.U.T. + - V DD T C, Case Temperature ( C) % V GS t d(o) t r t d(off) t f Fig 9. Maximum Drai Curret Vs. Case Temperature Fig b. Switchig Time Waveforms Thermal Respose (Z thja ) D = Notes: SINGLE PULSE. Duty factor D = t / t 2 (THERMAL RESPONSE) 2. Peak T J= P DM x Z thja + TA t, Rectagular Pulse Duratio (sec) PDM t t2 Fig. Maximum Effective Trasiet Thermal Impedace, Juctio-to-Ambiet 8

9 IRHQ567 N-Chael Q,Q4 V DS R G 2V V GS I AS tp.ω 5V L DRIVER Fig 2a. Uclamped Iductive Test Circuit V (BR)DSS tp. D.U.T + - V DD A E AS, Sigle Pulse Avalache Eergy (mj) TOP BOTTOM I D 2.A 2.9A 4.6A Startig T, Juctio Temperature ( J C) Fig 2c. Maximum Avalache Eergy Vs. Drai Curret I AS Fig 2b. Uclamped Iductive Waveforms Curret Regulator Same Type as D.U.T. 5KΩ Q G 2V.2µF.3µF 2 V Q GS Q GD D.U.T. + V - DS V G V GS 3mA Charge I G I D Curret Samplig Resistors Fig 3a. Basic Gate Charge Waveform Fig 3b. Gate Charge Test Circuit 9

10 IRHQ567 P-Chael Q2,Q3 -I D, Drai-to-Source Curret (A) VGS TOP -5V -2V -V -9.V -8.V -7.V -6.V BOTTOM -5.V -5.V 2µs PULSE WIDTH. T J = 25 C. -V DS, Drai-to-Source Voltage (V) -I D, Drai-to-Source Curret (A) VGS TOP -5V -2V -V -9.V -8.V -7.V -6.V BOTTOM -5.V -5.V 2µs PULSE WIDTH. T J = 5 C. -V DS, Drai-to-Source Voltage (V) Fig. Typical Output Characteristics Fig 2. Typical Output Characteristics -I D, Drai-to-Source Curret (A) T J = 25 C T J = 5 C V DS= -5V 2µs PULSE WIDTH V GS, Gate-to-Source Voltage (V) R DS(o), Drai-to-Source O Resistace (Normalized) I D = -2.8A V GS= -2V T J, Juctio Temperature ( C) Fig 3. Typical Trasfer Characteristics Fig 4. Normalized O-Resistace Vs. Temperature

11 -I D, Drai-to-Source Curret (A) IRHQ567 P-Chael Q2,Q3 C, Capacitace (pf) VGS = V, f = MHz Ciss = Cgs + Cgd, C ds SHORTED Crss = Cgd Coss = Cds + Cgd C iss C oss 4 FOR TEST CIRCUIT C rss SEE FIGURE V DS, Drai-to-Source Voltage (V) Q G, Total Gate Charge (C) -V GS, Gate-to-Source Voltage (V) I = D -2.8A V DS =-8V V DS =-5V V DS =-2V Fig 5. Typical Capacitace Vs. Drai-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage -I SD, Reverse Drai Curret (A) T J = 5 C T J = 25 C V GS = V V SD,Source-to-Drai Voltage (V). Tc = 25 C Tj = 5 C Sigle Pulse OPERATION IN THIS AREA LIMITED BY R DS (o) ms ms -V DS, Drai-toSource Voltage (V) Fig 7. Typical Source-Drai Diode Forward Voltage Fig 8. Maximum Safe Operatig Area

12 IRHQ567 P-Chael Q2,Q3 3. V DS R D -I D, Drai Curret (A) R G V GS V GS Pulse Width µs Duty Factor. % D.U.T. Fig a. Switchig Time Test Circuit + - V DD T C, Case Temperature ( C) Fig 9. Maximum Drai Curret Vs. Case Temperature t d(o) t r t d(off) t f % 9% V DS Fig b. Switchig Time Waveforms Thermal Respose (Z thja ) D = Notes: SINGLE PULSE. Duty factor D = t / t 2 (THERMAL RESPONSE) 2. Peak T J= P DM x Z thja + TA t, Rectagular Pulse Duratio (sec) PDM t t2 Fig. Maximum Effective Trasiet Thermal Impedace, Juctio-to-Ambiet 2

13 IRHQ567 P-Chael Q2,Q3 Fig 2a. Uclamped Iductive Test Circuit I AS V DS L R G D.U.T. V DD IAS A -2V V GS DRIVER tp.ω 5V E AS, Sigle Pulse Avalache Eergy (mj) I D TOP -.3A -.8A BOTTOM -2.8A Startig T, Juctio Temperature ( J C) Fig 2c. Maximum Avalache Eergy Vs. Drai Curret tp V (BR)DSS Fig 2b. Uclamped Iductive Waveforms Curret Regulator Same Type as D.U.T. -2V Q G -2V.2µF 5KΩ.3µF Q GS Q GD D.U.T. + V DS - V G V GS -3mA Charge I G I D Curret Samplig Resistors Fig 3a. Basic Gate Charge Waveform Fig 3b. Gate Charge Test Circuit 3

14 IRHQ567 Foototes: À Repetitive Ratig; Pulse width limited by maximum juctio temperature. Á VDD = 25V, startig TJ = 25 C, L= 4.4mH, Peak IL = 4.6A, VGS =2V Â ISD 4.6A, di/dt 3A/µs, VDD V, TJ 5 C Ã Pulse width 3 µs; Duty Cycle 2% Ä Total Dose Irradiatio with VGS Bias. 2 volt VGS applied ad VDS = durig irradiatio per MIL-STD-75, method 9, coditio A Å Total Dose Irradiatio with VDS Bias. 8 volt VDS applied ad VGS = durig irradiatio per MlL-STD-75, method 9, coditio ² VDD = - 25V, startig TJ = 25 C, L=7.8mH, Peak IL = - 2.8A, VGS = -2V ³ ISD - 2.8A, di/dt - 263A/µs, VDD -V, TJ 5 C Total Dose Irradiatio with VGS Bias. -2 volt VGS applied ad VDS = durig irradiatio per MIL-STD-75, method 9, coditio A Š Total Dose Irradiatio with VDS Bias. -8 volt VDS applied ad VGS = durig irradiatio per MlL-STD-75, method 9, coditio A Case Outlie ad Dimesios LCC-28 Q2 Q Q3 Q4 Q3 Q4 Q2 Q IR WORLD HEADQUARTERS: N. Sepulveda Blvd, El Segudo, Califoria 9245, USA Tel: (3) IR LEOMINSTER : 25 Crawford St., Leomister, Massachusetts 453, USA Tel: (978) TAC Fax: (3) Visit us at for sales cotact iformatio. Data ad specificatios subject to chage without otice. 5/25 4