HEXFET MOSFET TECHNOLOGY

Transcription

1 PD C POWER MOSFET THRU-HOLE (TO-257AA) IRFY340C,IRFY340CM 400V, N-CHANNEL HEXFET MOSFET TECHNOLOGY Product Summary Part Number RDS(o) ID Eyelets IRFY340C 0.55 Ω 8.7A Ceramic IRFY340CM 0.55 Ω 8.7A Ceramic HEXFET MOSFET techology is the key to Iteratioal Rectifier s advaced lie of power MOSFET trasistors. The efficiet geometry desig achieves very low o-state resistace combied with high trascoductace. HEXFET trasistors also feature all of the well-established advatages of MOSFETs, such as voltage cotrol, very fast switchig, ease of parallelig ad electrical parameter temperature stability. They are well-suited for applicatios such as switchig power supplies, motor cotrols, iverters, choppers, audio amplifiers, high eergy pulse circuits, ad virtually ay applicatio where high reliability is required. The HEXFET trasistor s totally isolated package elimiates the eed for additioal isolatig material betwee the device ad the heatsik. This improves thermal efficiecy ad reduces drai capacitace. Features: TO-257AA Simple Drive Requiremets Ease of Parallelig Hermetically Sealed Electrically Isolated Ceramic Eyelets Ideally Suited For Space Level Applicatios Absolute Maximum Ratigs Parameter Uits VGS = 10V, TC = 25 C Cotiuous Drai Curret 8.7 VGS = 10V, TC = 100 C Cotiuous Drai Curret 5.5 A IDM Pulsed Drai Curret ➀ 35 TC = 25 C Max. Power Dissipatio 100 W Liear Deratig Factor 0.8 W/ C VGS Gate-to-Source Voltage ±20 V EAS Sigle Pulse Avalache Eergy ➁ 520 mj IAR Avalache Curret ➀ 8.7 A EAR Repetitive Avalache Eergy ➀ 10 mj dv/dt Peak Diode Recovery dv/dt ➂ 4.0 V/s TJ Operatig Juctio -55 to 150 TSTG Storage Temperature Rage Lead Temperature 300(0.063i./1.6mm from case for 10 sec) o C Weight 4.3 (Typical) g For foototes refer to the last page 1 4/18/01

2 Electrical Tj = 25 C (Uless Otherwise Specified) Parameter Mi Typ Max Uits Test Coditios BVDSS Drai-to-Source Breakdow Voltage 400 V VGS = 0V, ID = 1.0mA BVDSS/ TJ Temperature Coefficiet of Breakdow 0.46 V/ C Referece to 25 C, ID = 1.0mA Voltage RDS(o) Static Drai-to-Source O-State 0.55 Ω VGS = 10V, ID = 5.5A Resistace ➃ VGS(th) Gate Threshold Voltage V VDS = VGS, ID = 250µA gfs Forward Trascoductace 4.9 S ( ) VDS > 15V, IDS = 5.5A ➃ IDSS Zero Gate Voltage Drai Curret 25 VDS= 320V,VGS=0V µa 250 VDS = 320V, VGS = 0V, TJ = 125 C IGSS Gate-to-Source Leakage Forward 100 VGS = 20V A IGSS Gate-to-Source Leakage Reverse -100 VGS = -20V Qg Total Gate Charge 65 VGS =10V, ID = 8.7A Qgs Gate-to-Source Charge 10 C VDS = 200V Qgd Gate-to-Drai ( Miller ) Charge 40.5 td(o) Tur-O Delay Time 25 VDD = 200V, ID = 8.7A, tr Rise Time 92 RG = 9.1Ω s td(off) Tur-Off Delay Time 79 tf Fall Time 58 LS + LD Total Iductace 6.8 H Measured from drai lead (6mm/0.25i. from package) to source lead (6mm/0.25i. from package) Ciss Iput Capacitace 1400 VGS = 0V, VDS = 25V Coss Output Capacitace 350 pf f = 1.0MHz Crss Reverse Trasfer Capacitace 230 Ω Source-Drai Diode Ratigs ad Characteristics Parameter Mi Typ Max Uits Test Coditios IS Cotiuous Source Curret (Body Diode) 8.7 ISM Pulse Source Curret (Body Diode) ➀ 35 A VSD Diode Forward Voltage 1.5 V Tj = 25 C, IS = 8.7A, VGS = 0V ➃ trr Reverse Recovery Time 600 S Tj = 25 C, IF = 8.7A, di/dt 100A/µs QRR Reverse Recovery Charge 5.6 µc VDD 50V ➃ to Forward Tur-O Time Itrisic tur-o time is egligible. Tur-o speed is substatially cotrolled by LS + LD. Thermal Resistace Parameter Mi Typ Max Uits Test Coditios RthJC Juctio-to-Case 1.25 RthCS Case-to-sik 0.21 C/W RthJA Juctio-to-Ambiet 80 Typical socket mout Note: Correspodig Spice ad Saber models are available o the G&S Website. For foototes refer to the last page 2

3 Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 8.9A Fig 3. Typical Trasfer Characteristics Fig 4. Normalized O-Resistace Vs. Temperature 3

4 8.9A 3 Fig 5. Typical Capacitace Vs. Drai-to-Source Voltage Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage Fig 7. Typical Source-Drai Diode Forward Voltage Fig 8. Maximum Safe Operatig Area 4

5 V DS R D R G V GS D.U.T. + - V DD 10V Pulse Width 1 µs Duty Factor 0.1 % Fig 10a. Switchig Time Test Circuit V DS 90% Fig 9. Maximum Drai Curret Vs. Case Temperature 10% V GS t d(o) t r t d(off) t f Fig 10b. Switchig Time Waveforms Fig 11. Maximum Effective Trasiet Thermal Impedace, Juctio-to-Case 5

6 15V V DS L DRIVER R G 20V 1 tp D.U.T. I AS 0.01Ω + - V DD A Fig 12a. Uclamped Iductive Test Circuit tp V (BR)DSS Fig 12c. Maximum Avalache Eergy Vs. Drai Curret I AS Fig 12b. Uclamped Iductive Waveforms Curret Regulator Same Type as D.U.T. 50KΩ 10 V Q GS Q G Q GD 12V 0.2µF.3µF D.U.T. + V - DS V G V GS 3mA Charge I G I D Curret Samplig Resistors Fig 13a. Basic Gate Charge Waveform Fig 13b. Gate Charge Test Circuit 6

7 Foototes: ➀ Repetitive Ratig; Pulse width limited by maximum juctio temperature. ➁ VDD = 50V, startig TJ = 25 C, L= 13mH Peak IL = 8.7A, VGS = 10V ➂ ISD 8.7A, di/dt 120A/µs, VDD 400V, TJ 150 C ➃ Pulse width 300 µs; Duty Cycle 2% Case Outlie ad Dimesios TO-257AA IR WORLD HEADQUARTERS: 233 Kasas St., El Segudo, Califoria 90245, USA Tel: (310) TAC Fax: (310) Visit us at for sales cotact iformatio. Data ad specificatios subject to chage without otice. 04/01 7