Features. Description. Table 1: Device summary Order code Marking Package Packing STP5N80K5 5N80K5 TO-220 Tube

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1 N-channel 800 V, 1.50 Ω typ., 4 A MDmesh K5 Power MOSFET in a TO-220 package Datasheet - production data Features Order code VDS RDS(on) max. ID STP5N80K5 800 V 1.75 Ω 4 A Industry s lowest RDS(on) x area Industry s best FoM (figure of merit) Ultra-low gate charge 100% avalanche tested Zener-protected Figure 1: Internal schematic diagram Applications Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. Table 1: Device summary Order code Marking Package Packing STP5N80K5 5N80K5 TO-220 Tube May 2016 DocID Rev 2 1/13 This is information on a product in full production.

2 Contents STP5N80K5 Contents 1 Electrical ratings Electrical characteristics Electrical characteristics (curves) Test circuits Package information TO-220 type A package information Revision history /13 DocID Rev 2

3 Electrical ratings 1 Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VGS Gate-source voltage ± 30 V ID Drain current (continuous) at TC = 25 C 4 A ID Drain current (continuous) at TC = 100 C 2.3 A ID (1) Drain current (pulsed) 16 A PTOT Total dissipation at TC = 25 C 60 W dv/dt (2) Peak diode recovery voltage slope 4.5 dv/dt (3) MOSFET dv/dt ruggedness 50 V/ns Tj Tstg Operating junction temperature range - 55 to 150 C Storage temperature range Notes: (1) Pulse width limited by safe operating area (2) ISD 4 A, di/dt = 100 A/μs; VDS peak < V(BR)DSS, VDD = 640 V (3) VDS 640 V Table 3: Thermal data Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case 2.08 C/W Rthj-amb Thermal resistance junction-ambient 62.5 C/W Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR Avalanche current, repetitive or not repetitive (pulse width limited by Tjmax) 1.2 A EAS Single pulse avalanche energy (starting Tj = 25 C, ID = IAR, VDD = 50 V) 165 mj DocID Rev 2 3/13

4 Electrical characteristics STP5N80K5 2 Electrical characteristics TC = 25 C unless otherwise specified Table 5: On/off-state Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 1 ma 800 V VGS = 0 V, VDS = 800 V 1 µa IDSS Zero gate voltage drain current VGS = 0 V, VDS = 800 V 50 µa TC = 125 C (1) IGSS Gate body leakage current VDS = 0 V, VGS = ±20 V ±10 µa VGS(th) Gate threshold voltage VDD = VGS, ID = 100 µa V RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 2 A Ω Notes: (1) Defined by design, not subject to production test. Table 6: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit Ciss Input capacitance pf Coss Output capacitance VDS = 100 V, f = 1 MHz, VGS = 0 V pf Crss Reverse transfer capacitance pf Co(tr) (1) Co(er) (2) Equivalent capacitance time related Equivalent capacitance energy related VGS = 0, VDS = 0 to 640 V pf 12 pf Rg Intrinsic gate resistance f = 1 MHz, ID=0 A Ω Qg Total gate charge VDD = 640 V, ID = 4 A nc Qgs Gate-source charge VGS= 10 V nc Qgd Gate-drain charge (see Figure 15: "Test circuit for gate charge behavior") nc Notes: (1) Co(tr) is a constant capacitance value that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. (2) Co(er) is a constant capacitance value that gives the same stored energy as Coss while VDS is rising from 0 to 80% VDSS. 4/13 DocID Rev 2

5 Electrical characteristics Table 7: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) Turn-on delay time VDD= 400 V, ID = 2 A, RG = 4.7 Ω ns tr Rise time VGS = 10 V ns td(off) Turn-off delay time (see Figure 14: "Test circuit for resistive load switching times" and ns tf Fall time Figure 19: "Switching time waveform") ns Table 8: Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current - 4 A ISDM (1) Source-drain current (pulsed) - 16 A VSD (2) Forward on voltage ISD = 4 A, VGS = 0 V V trr Reverse recovery time ISD = 4 A, di/dt = ns Qrr Reverse recovery charge A/µs,VDD = 60 V (see Figure 16: "Test circuit µc IRRM Reverse recovery current for inductive load switching and diode recovery times") - 12 A trr Reverse recovery time ISD = 4 A, di/dt = 100 A/µs ns Qrr Reverse recovery charge VDD = 60 V, Tj = 150 C (see Figure 16: "Test circuit µc IRRM Reverse recovery current for inductive load switching and diode recovery times") A Notes: (1) Pulse width limited by safe operating area (2) Pulsed: pulse duration = 300 µs, duty cycle 1.5% Table 9: Gate-source Zener diode Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)GSO Gate-source breakdown voltage IGS= ± 1mA, ID= 0 A ± V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection, thus eliminating the need for additional external componentry. DocID Rev 2 5/13

6 Electrical characteristics 2.1 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance STP5N80K5 Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance 6/13 DocID Rev 2

7 Figure 8: Capacitance variations Electrical characteristics Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Maximum avalanche energy vs starting TJ Figure 13: Source-drain diode forward characteristics DocID Rev 2 7/13

8 Test circuits STP5N80K5 3 Test circuits Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior V DD RL V GS I G = CONST 100 Ω D.U.T. pulse width 2200 μf kω 47 kω V G 1 kω AM01469v10 Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform 8/13 DocID Rev 2

9 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK is an ST trademark. DocID Rev 2 9/13

10 Package information 4.1 TO-220 type A package information Figure 20: TO-220 type A package outline STP5N80K5 10/13 DocID Rev 2

11 Package information Table 10: TO-220 type A mechanical data mm Dim. Min. Typ. Max. A b b c D D E e e F H J L L L L øp Q DocID Rev 2 11/13

12 Revision history STP5N80K5 5 Revision history Table 11: Document revision history Date Revision Changes 19-Nov First release. 02-May Modified: Table 2: "Absolute maximum ratings", Table 3: "Thermal data", Table 5: "On/off-state", Table 6: "Dynamic", Table 7: "Switching times" and Table 8: "Source-drain diode". Updated: Figure 15: "Test circuit for gate charge behavior". Updated: Section 5.1: "TO-220 type A package information". Added: Section 3.1: "Electrical characteristics (curves)". Minor text changes. 12/13 DocID Rev 2

13 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document STMicroelectronics All rights reserved DocID Rev 2 13/13

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