Design of FPGA Based SPWM Single Phase Inverter

Transcription

1 Proceedigs of MUCEET2009 Malaysia Techical Uiversities Coferece o Egieerig ad Techology Jue 20-22, 2009, MS Garde,Kuata, Pahag, Malaysia MUCEET2009 Desig of FPGA Based SPWM Sigle Phase Iverter Afarulrazi Abu Bakar, Md Zarafi Ahmad ad Farah Salwai Abdullah Abstract Nowadays power iverter serves as a importat emergecy power supply system i evets of mais power supply failure. The AC output voltage of a power electroic iverter is usually o-siusoidal ad hece has a high harmoic cotet. Siusoidal Pulse Width Modulatio (SPWM) scheme is ormally used to covert the DC power supply ito AC power supply by comparig the referece voltage waveform with the triagular waveform kow as carrier. SPWM provides a way to reduce the total harmoic distortio of load curret. The objective of this paper is to demostrate a SPWM switchig by usig Altera DE2 board. I this SPWM, a siusoidal referece voltage waveform is compared with the triagular carrier voltage to geerate the o ad off switchig scheme. These switchig schemes will trigger the gate of the power switch. I this paper, the SPWM switchig strategies will be develop usig Altera DE2 (Cycloe II EP2C35F672C6) with 6 bit serial cofiguratio devices. The switchig betwee referece ad carrier waveforms of SPWM is obtaied by usig Matlab software. Simulatio o the desig pulses is coducted usig Quartus II software tools provided by Altera. The output frequecy of SPWM is 50 Hz ad the desig is limited to two levels of modulatio idex which are 0.5 ad Keywords: SPWM-Siusoidal Pulse Width Modulatio, FPGA- Field Programmable Logic Array, VHDL- Very High Descriptio Laguage. P I. INTRODUCTION ulse width modulatio (PWM) is the most popular switchig method used to several types of coverter with a appropriate switchig scheme to produce a desired switchig patter. PWM is oe of the switchig techiques used for coverter to produce a AC output sigal fed from DC iput []. PWM makes the iverter output waveforms made up of may pulses with certai rules ad goals through. supplyig DC voltage for the iverter [2]. The o ad off scheme based o the itersectio of the carrier sigal (triagular) ad referece sigal (costat DC). PWM still cotais a harmoics ad aother approach is SPWM switchig techique [3]. This paper presets work carried out i developig cotrol sigal usig bipolar SPWM to produces a switchig scheme which oly a sigle siusoidal waveform (referece) used with the triagular (carrier) [4]. I SPWM a fixed triagular is compared with siusiodal waveform ad the amplitude ca be varied from []. The o ad off switchig scheme will be produce whe the istataeous value of the referece sigal is larger tha the triagular carrier, the output is at positive ad whe the referece is less the carrier output is at egative as show i figure. I order to demostrate SPWM switchig usig Altera DE2 board, the switchig iterval betwee each crossig obtaied usig Matlab software. The crossover of the sigal the trasferred ito a table. The switchig scheme should be able to be implemeted to the four switches at the iverter with a differet timelie. This project presets the implemetatio of FPGA techology i desigig the SPWM switchig sigal. Altera Cycloe II FPGA is used i this project. It aslo provide a wide rage of desity, memory, embedded multiplier, ad packagig optios i a customer-defied FPGA feature set optimized for low-cost applicatios. Besides that, Cycloe II FPGA also supports a wide rage of commo exteral memory iterfaces ad I/O protocols commo i low-cost applicatios. The use of FPGA will produce better cotrol sigal for sigle phase full bridge iverter. The modulatio idex, umber of pulses over a period ad the output frequecy ca easily chaged usig the program. The desiged of the switchig pulse ca be altered without ay chages i hardware. This is the mai advatages of this project that applied the FPGA techology where there is the flexibility of ay chages o the switchig parameter ad directly elimiates the complexity of the hardware. Figure : Sigle phase full-bridge iverter.

2 II. MATLAB PROGRAMMING A program is developed from the fudametal cocept of the SPWM switchig techique by usig Matlab M-File. The programmig is capable to produce the SPWM waveform characteristic from the several rages of frequecies, modulatio ad umber of pulses for half period of referece sigal. The iput data will be processed through a mathematical programmig ad the itersectio betwee referece sigal ad carrier sigal geerates PWM pulses for the period of α to ß i each pulse as show i figure 2. Accordig to figure 2, is the umber of pulse for half cycle of referece sigal. This strategy is implemeted usig Matlab/M-file programmig ad ca be fulfilled through six steps as demostrated i figure carrier referece t depicted i Table (a) ad (b) respectively. The recorded data are take over oe complete cycle of referece sigal. For the first, the data recorded are i degree scale ad the coverted to time scale. Thus it ca be used easily to geerate PWM sigal digitally ad implemeted usig Quartus II software. From the table, it ca be observed that the width of each pulse at the begiig ad ed for every half cycle of referece sigal have the same scale. For istat, i the positive half cycle of referece sigal the width of the pulse t is equal with the pulse of t 20. The period of the referece iput frequecy is T f For the half cycle ref () T (2) 2 vod t t2 t3 t4 t5 t6 t7 t8 t9 t0 The value of α, β ad the width of the pulses expressed i term of time ca be determied by equatios (3), (4), ad (5) respectively. α α2 α3 α4 β β2 β3 β4 α5 α6 α7 α8 β5 β6 β7 α9 α0 β8 β9 β0 t T / 2 ( t) ( ) (3) 80 Figure 2: Geeratio of SPWM switchig scheme. T / 2 ( t) ( ) (4) 80 Width (5) All the itersectio value for α ad β is recorded i Table (a) ad (b). The last itersectio betwee the referece sigal ad carrier sigal is occurs at β 40 which is equal to 9.76ms ad this is happe at the last pulse over oe cycle of 20ms. Figure 3: Block diagram of Matlab Programmig. I this paper, the proposed frequecy of the output iverter is 50Hz with two modulatio idex which is 0.75 ad 0.5. The output of PWM sigal is recorded based o time scale ad degree scale. These data are used to produce the SPWM switchig scheme whereas the time will be digitized. III. SWITCHING STRATEGIES The proposed coverter is use a IGBT as a switchig device. The IGBT s have simpler drivig circuits tha other power trasistors devices ad used due to its popularity amog researchers that could lead to high-power applicatio. The coverter cosists of four IGBTs. The data of the referece frequecy of 50Hz with the modulatio idex of 0.5 ad 0.75 are obtaied from Matlab software the (a) 2

3 Before the programmig ca be uploaded ito the DE2 board, the simulatio usig Waveform Editor of Quartus II is implemeted to perform the SPWM sigal. Figure 5 preset the output waveform from the clock divider while figure 6 presets the output SPWM sigal to trigger switches for 0.5 ad 0.75 modulatio idexes. I this stage, the measured velue of the estimated differece betwee the observed or calculated value of the timig compared to its true value. The behavior of the SPWM at high speeds for short iterval ca be observed by usig compress optio to compress the waveform.the output of the SPWM the assiged to the expasio header of the DE2 board through Pi Plaer. The expasio headers coect directly to 36 pis of the Cycloe II FPGA. Table 2 show the output of the cotrol sigal which coected to expasio header pis. (b) Table : (a) ad (b): Data obtaied from Matlab for modulatio idex 0.5 ad IV. VHDL PROGRAMMING USING QUARTUS II By usig Quartus II 8.0 sp software provided by Altera, the data obtaied from the Matlab are digitized to be able to implemet i Quartus II eviromet. Figure 4 illustrate the block diagram of the complete SPWM geerator for modulatio idex 0.5 ad The block diagram cosists of altpll which be able to geerate 25 MHz clock output from 50 MHz iteral clock of Altera DE2 board. The altpll megafuctio ca be used to reduce the clock delay ad geerate aother iteral clocks to be operates at multiples of system frequecy. The clock divider is applied to divide the the iteral clock of Altera DE2 board ito several frequecy rages. As a example the iteral clock frequecy ca be divided to 25 MHz, MHz, 00 khz, khz ad etc. The, the MHz of the output frequecy of clock divider is coected to the lpm_couter which will be coutig from 0 to 9999 over oe complete cycle. This meas, oe cycle of this frequecy represet the period of μs. The lpm_couter megafuctio is actually a biary couter that either ca be cout up, dow, or up ad dow together. The o ad off sigal is created by VHDL programmig ad the coverted ito block diagram. The VHDL for 0.75 ad 0.5 modulatio idex are created by employig four switches which are operate i pair for a time (S-S2 ad S3-S4). Figure 5: Output from the clock divider. Figure 6: Cotrol sigal for 0.5 ad Modulatio Expasio Switch Idex (ma) Header S PIN N_ S2 PIN N_29 S3 PIN M_22 S4 PIN M_2 S PIN N_ S2 PIN N_22 S3 PIN L_2 S4 PIN L_22 Table 2: Output of SPWM coected to expasio header DE2 board. The Assembler which is the compiler module that completes project processig will geerate a device programmig image. For the FPGAs, this programmig image is i the form of oe or more Programmer Object Files (.pof) ad SRAM Object Files (.sof). With the Active Serial programmig iterface, programmig hardware used to dowload the cofiguratio data for programmig serial cofiguratio devices. The voltage level of the iput ad output o the expasio header ca be adjusted to 3.3V, 2.5V or.8v. Figure 4: Block diagram of SPWM geerator. 3

4 V. RESULTS Tektroix four chael digital oscilloscope TDS3054B is used to measure the experimetal result from the DE2 board. The experimet also coducted for two modulatios which is 0.5 ad Figure 7 ad Figure 8 demostrate the width differece for modulatio 0.5 ad 0.75 respectively. Practically the above sigal of figure 7 ad figure 8 are used to cotrol the turig o/off of the power switch SS2 while the below is to cotrol power switch of S3S4 of the iverter. The width of both pulses from t to t 40 is aalyzed ad compared with the simulated sigal usig Quartus II software. From the simulatio results ad experimet results its give the acceptable rages of PWM sigal betwee desig ad practical. Thus it ca be said that the accuracy of the iteral clock of the DE2 board is very precise. Figure 9: Dead time for 0.5 modulatio idex. S,S2 S3,S4 Figure 7: Output sigal for modulatio idex 0.5. Figure 0: Dead time for 0.75 modulatio idex. Figure 9 ad figure 0 show the dead time applied betwee switch SS2 ad S3S4 for the modulatio idex of 0.5 ad 0.75 respectively. From these figure it ca be observed that the dead time for modulatio idex 0.5 ad 0.75 is 420µs ad 460µs respectively. The occurs of dead time betwee the SS2 ad S3S4 shows that the sigal are possible to be implemeted to cotrol the IGBTs switch of the iverter. The SPWM sigal with the modulatio idex of 0.5 ad 0.75 has the amplitude of 3.3 V ad 3.24 V respectively ad demostrated i Figure ad Figure 2. Figure 8: Output sigal for modulatio idex 0.75 Figure : Output sigal for SS2 ad S3S4 with modulatio idex= 0.5 4

5 Figure 2: Output sigal for SS2 ad S3S4 with modulatio idex= 0.75 VI. CONCLUSIONS This paper outlied ad illustrated a method to obtai the switchig strategies i geeratig a SPWM sigal for a sigle-phase iverter. The SPWM sigal has bee developed ad tested successfully usig Quartus II software ad implemeted o Altera DE2 Board. The developed SPWM is uploaded o a sigle chip of Altera Board ad it is capable to provide flexibility, relibitily ad ease to program i order to cotrol a sigle-phase iverter. ACKNOWLEDGEMENT The author/authors would like to thak Uiversiti Tu Hussei O Malaysia for supportig this research uder the Short Term Research Grat. REFERENCES [] Muhammad, H. Rashid. Power Electroics Circuits, Devices ad Applicatio. Upper Saddle River, NJ: Pretice Hall, [2] Huo B., Zhao Z., Meg S., Liu J. ad Su X, Compariso of Three PWM Strategies-SPWM, SVPWM & Oe-cycle Cotrol. Dept. of Electrical Egieerig, Tsighua Uiversity, Beijig, Chia, IEEE Explore, 2003.z [3] M. N. Md Isa, M.I. Ahmad, Sohiful A.Z. Murad ad M. K. Md Arshad, FPGA Based SPWM Bridge Iverter, America Joural of Applied Scieces 4 (8), 2007, pp [4] Moha, Udelad ad Robbis. Power Electroic coverters, applicatios ad desig, 2 d ed. Caada: Joh Wiley & Sos Ic,