Modelig the Curret Profile Switchig capacitace is oe of the factors that determie dyamic power cosumptio. Power estimatio tools ca be categorized by t

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1 Aalyzig Software Iflueces o Substrate Noise: A ADC Perspective ByugTae Kag, N. Vijaykrisha, Mary Jae Irwi Samsug, Korea, byugtae.kag@samsug.com Dept. of CSE, Pe State Uiversity, Uiv. Park, PA, USA, vijay@cse.psu.edu, mji@cse.psu.edu Abstract Substrate oise affects the performace of mixed sigal itegrated circuits. Power supply (di/d oise is the domiat source of substrate oise. There have bee various attempts at the circuit ad software levels to estimate this oise. Software-level oise estimatio is especially importat, as desigig oise tolerat circuits for all circumstaces may be prohibitively expesive. I this paper, we propose a ew software approach for estimatig di/dt oise ad icorporate it ito a power simulator i order to ivestigate the ifluece of software o substrate oise. As a case study, we ivestigate how a aalog-to-digital coverter (ADC) ca be desiged to adapt its resolutio i the presece of substrate oise geerated by a embedded processor core. The proposed strategies prevet uexpected ADC performace degradatios. INTRODUCTION Aalog circuits are beig implemeted i CMOS ad itegrated alog with high speed digital circuits - such as microprocessor cores - for may multimedia applicatios. I these mixed-sigal itegrated circuits, the digital circuits geerate oise whe they are switchig. This oise, called substrate oise, is propagated to the aalog circuits through a shared substrate, ad deteriorates the performace of the aalog circuits. This substrate oise comes from two major sources: ) oise couplig from the switchig trasistors ad 2) oise couplig from the power supply (di/dt oise). Sice di/dt oise is the domiat source of substrate oise [], the estimatio of di/dt oise is a importat issue i desigig reliable, mixed-sigal IC. There have bee attempts to accurately estimate di/dt oise at the circuit-level [e.g., 3]. However, these techiques ca t estimate the oise that the executio of the software may cause. Software-level oise estimatio is especially importat i wireless commuicatio systems because i such systems, may hardware blocks are replaced by software blocks ad the high performace processor that executes these software blocks is itegrated alog with the aalog circuits o a sigle chip. Therefore, accurate estimatio of the oise geerated by the software is a importat tool for desigig reliable, mixed sigal chips. Software-level oise estimatio was the focus of recet work preseted by Grochowski et.al. [4]. By modifyig the Wattch toolset [5], they extract the curret profile i advace ad estimate the oise. The magitude of the oise pulse was determied by the estimatig the power cosumed i a sigle clock cycle while the curret shape was modeled as a rectagular pulse. This approach is a simple ad effective way to quickly calculate the software oise effects. However, it uderestimates di/dt oise sice, i reality, the shape of curret is ofte quite varied [8]. Therefore, a more accurate approximatio is eeded. I this paper, we propose a ew approach to estimate di/dt oise ad icorporate it ito a power simulator (Simple- Power [7]) for a simple RISC processor core i order to ivestigate the ifluece of software o substrate oise. Sice SimplePower is cycle-accurate, software-level oise ca be accurately estimated. As a case study, we ivestigate how a ADC ca be desiged to adapt its resolutio i the presece of substrate oise. We believe that our tool ca be used to evaluate the impact of software o other aalog compoets i a similar fashio. The remaider of this paper is orgaized as follows. I the ext sectio, we describe our ew approach for estimatig di/dt oise ad explai how to use it to measure oise at the software-level. The, we describe the adaptive resolutio ADC, aalyze its performace degradatio due to substrate oise, ad propose strategies to avoid serious performace degradatio. Fially, we provide cocludig remarks. ESTIMATING di/dt NOISE I large digital circuits such as microprocessors, draiig the high-peak currets creates rigig i the RLC compoets of the power delivery system. The power delivery system is composed of several blocks, e.g., the power supply, motherboard, sockets, package, bodwires, ad the die capacitaces. Each has parasitics that geerate di/dt oise. This oise is capacitively coupled ito the chip s substrate from Vdd via -well juctio capacitaces ad resistively coupled from the bulk cotacts (we cosider oly the resistive couplig sice it is the domiat effec. The, this oise is propagated to the aalog circuits i mixed-sigal ICs through the low resistive substrate. To estimate this substrate oise, three aspects must be modeled. The first aspect is the curret profile that describes how the curret peaks vary with time. Secod are the parasitics of the power delivery system. Third is the substrate model that describes the resistive couplig /4/$2. 24 IEEE. 96

2 Modelig the Curret Profile Switchig capacitace is oe of the factors that determie dyamic power cosumptio. Power estimatio tools ca be categorized by the kid of simulatio used to extract the switch capacitace (e.g., circuit, logic, architecture). Amog these, architecture-level simulatio is appropriate for estimatig the power cosumptio of the microprocessor whe executig software. O the other had, curret variatio is key i estimatig di/dt oise. If the relatioship betwee the switchig capacitace ad the curret variatio ca be defied, architectural-level power estimators ca be evolved ito oise estimators. We discuss below how a curret profile model is built based o switch capacitace. Wheever a CMOS gate is switchig, the load capacitace is charged or discharged formig a curret path from the exteral power supply to the gate. Figure (a) shows the curret path that is established by a sigle CMOS iverter s dischargig activity [8]. The capacitace is assumed to be distributed evely betwee chargig ad dischargig. The equivalet circuit is show i Figure (c). I calculatig the peak curret, we assume that v c ( is fully charged to Vdd ad that the peak curret occurs at i(αd). From these assumptios, we ca derive the peak curret, Ipeak, as i Eq-. The curret shape is modeled as i Figure (b). v ( c t = o i( τ) dτ Ipeak Ipeak i( = t ( u( u( t αd)) + ( t D) ( u( t αd) u( t D)) αd ( α) D Ipeak=2Vdd*Csw/D Eq- (D: delay of the gate, α: a circuit-complexity coefficie Figure. Modelig a sigle CMOS gate Differet types of digital circuits were simulated to see if the curret shape of a sigle CMOS gate ca be directly exteded to multiple CMOS gates. We selected five sample circuits: a sigle array multiplier cell, a 6x6 array multiplier, a sigle flip-flop (FF), a 8-bit register, ad a sigle multiplier cell with a 4-bit register. These circuits were desiged i.8 micro techology ad simulated with HSPICE. Figure 2 shows the curret shapes for these five circuits. The solid lies are from HSPICE simulatio ad the dotted lies are the modeled curret shapes from Eq- ad Figure (b). Table cotais the data required for calculatig Ipeak. Curret (ma) 3.mA 5s Curret (ma).9ma 5.s (a) Sigle FF I PEAK=2.9mA 5.22s I PEAK=.78mA 2s s t(s) (c) Sigle array multiplier cell Curret (ma) 25s Curret (ma) t(s) B 26mA 5s Curret (ma) mA I PEAK=23.6mA (b) 8-bit register t(s) 6s 62.75s 65.5s t(s) (d) 6x6 array multiplier A A 5.s t(s) (e) Sigle multiplier cell with 4-bit register 5.22s I PEAK=96.6mA Figure 2. Curret shapes of five sample circuits As show i Figure 2(a) ad (b), the modeled curret shape for sequetial circuits is close to that of circuit simulatio. This is because most of a FF s gates switch withi a short period time of the FF s active clock edge. Also, as Figure 2(b) shows, the curret of multiple FFs is the sum of the sigle FF s curret (Ipeak=3.mA for a sigle FF ad Ipeak=26mA for a 8-bit register). Table. Measured Csw ad calculated Ipeak Circuits D (s) Csw (pf) Ipeak (ma) Sigle FF bit Reg Sigle mult cell x6 multiplier bit Reg with sigle mult cell However, the more complex circuits as show i Figure 2(d) ad (e) are ot as easily modeled. Thus, we must develop a alterative approach to model their curret shapes. If the circuit is composed of both sequetial ad combiatioal logic, as i Figure 2(e), the curret shape is modeled as the sum of the models of the sequetial circuits (modeled by Eq- ad Figure (b)) ad of the combia- 97

3 tioal circuits (modeled as a fixed curret step as i [4]). This results i the curret shape of lie B i Figure 2(e) - much closer to the simulated shape tha that from just Eq- (lie A). We applied this curret estimatio procedure to Simple- Power, a architectural-level power estimator [7]. Simple- Power provides the cycle-accurate switchig capacitace of a simple five-stage, sigle-issue microprocessor core. At each clock cycle, SimplePower extracts the switchig capacitace of each pipelie stage by addig up the switchig capacitaces of each of the stage s active fuctioal uits. The switchig capacitace is trasitio-sesitive i that the pre-calculated switchig capacitaces are iput vector depedet. Usig SimplePower, we ca accurately separate the switchig capacitace of sequetial ad combiatioal circuits at every clock cycle. As described above, the curret shape of the sequetial circuitry active withi each clock cycle ca be accurately modeled from its switchig capacitace. However, the combiatioal circuits i a microprocessor core are eve more complex tha the combiatioal circuits modeled above ad their switchig activities are usually radomly distributed withi a clock cycle. Therefore, we assumed that the curret shape for combiatioal circuits is uiformly distributed withi a clock cycle ad we model it as a fixed curret step [4]. We itegrated these curret shape models ito SimplePower. Figure 3 shows the curret profile geerated by ruig bechmark, bsrch.c, o our modified SimplePower. The right-had side of the graph is a elargemet of the curret shape for a few clock cycles. The triagles are from sequetial circuit activity ad rectagles are from combiatioal circuit activity. Figure 4. Parasitic model of the power delivery system To calculate the trasiet respose, two cases must be cosidered. The first case is whe I IC is triagular correspodig to sequetial circuit activity ad the secod is whe I IC is rectagular correspodig to combiatioal circuit activity. Eq-2 represets the trasiet resposes of V ( for the triagular shape (a) ad the rectagular shape (b). V ( = ((.475 cos( θ.75 si( θ ) exp( τ Eq-2(a) t +.475) ( 2u( t t ) + u( t t )) 4 = (( 2 cos( θ +.2si( θ ) exp( τ V ( +.2) ( u( t t )) Eq-2(b) (where θ=9.695e8, τ=5e7, t =.5s, t =s, t 2 =s) Because it is a liear circuit, the RLC circuit has the property of liearity such that f(ax+by) = af(x)+bf(y). This property makes the calculatio easier; we ca calculate the two trasiet resposes separately ad the add them. This power delivery system modelig approach is validated i Figure 5 that shows a compariso betwee SPICE simulatios ad the results of Eq-2 calculatios for the modeled bsrch.c curret profile. Whe the curret shape is modeled as simple a rectagular pulse, the respose is uderestimated by 63% i the RMS sese (see Figure 5(c)) Voltage (V) Curret (A) No. of cycle Curret (A) No. of cycle Figure 3. Curret profile of bsrch.c ( cycles) 5 5 Cycle (a) Spice simulatio result Modelig the Parasitics The ext step i estimatig di/dt oise is to model the. power delivery system. The major oise sources are the voltage regulator (Vreg), mother board ad socket (MF),. 5 the package (PKG), ad the bodwires. May oise reductio optimizatio methods have bee proposed [e.g., ], for example the use of decouplig capacitors. However, -. 5 optimizig the bodwires would require very areaexpesive -. o-chip decouplig capacitors. Therefore, we 5 C y c le 5 assume that all oise sources except the bodwires have (b) Eq-2 modelig results bee optimized. Figure 4 illustrates our resultig parasitic model. The RLC values are derived from [9, 3]. Voltage (V)

4 Voltage (V) C y c le 5 (c) The result of rectagular shape as i [4] Figure 5. Trasiet respose of V ( for bsrch.c Usig the property of liearity, Eq-2, ad the curret profiles, the di/dt oise geerated from ruig a piece of code ca be calculated. For example, te cycles of di/dt oise for bsrch.c are illustrated i Figure 6. Voise(mV) bits by as much as 2%. Thus whe a ADC is embedded with a microprocessor core o a sigle chip, its resolutio will be impacted because a microprocessor core geerates switchig oise ad because the level of the geerated oise varies with the software ruig o the core. If the resolutio of ADC ca be varied adaptively i respose to the substrate oise level, the deterioratio i the resolutio of the ADC ca be mitigated. I this sectio, a adaptive resolutio ADC (Power ad Resolutio Adaptive ADC (PRA-ADC) [6]) will be used to formulate strategies that ca be used to avoid resolutio degradatio due to substrate oise assumig that SimplePower s microprocessor core is embedded o the same chip as the PRA-ADC. A Adaptive Resolutio ADC The PRA-ADC uses a very differet voltage comparator tha a covetioal ADC. PRA-ADC s Threshold Iverter Quatizatio (TIQ) comparator is illustrated i Figure 7(b). The operatio of the TIQ is related to the iverter threshold voltage, V m. I Figure 7(b), V m plays the same role as the threshold voltage of the differetial amplifier (Figure 7(a)). The built-i threshold voltage of the CMOS iverter acts as the referece voltage i the comparator ad the resistor ladder circuit that geerates the referece voltages ca be elimiated. Thus, the TIQ comparator is simple ad fast cycle Figure 6. The oise shape of bsrch.c ( cycles) Modelig the Substrate To determie how di/dt oise is propagated to the aalog circuits, we also eed to model the substrate. Quite complicated algorithms are required to extract the exact substrate resistace. However, because the resistace of the heavily doped p + bulk i a typical epitaxial substrate is very low, such substrates ca be modeled as a sigle ode whe the distace betwee where the oise is ijected ad where it is sesed is a few times larger tha the epitaxial layer thickess [4]. I this case, the substrate oise is approximately uiform throughout the heavily doped substrate. We used the substrate model proposed i [5]. Whe we assume that the distace betwee two the digital ad aalog cotacts is over 5um, the atteuatio of oise is uder 5%. I other words, the di/dt oise geerated by the digital circuitry (as i Figure 6) is atteuated by less tha 5% of V ( without the distortio of phase respose. DESIGNING A NOISE TOLERANT ADC I this sectio, we discuss how oise affects the performace of a aalog circuit ad how these effects ca be cotrolled usig the oise modelig preseted above. A ADC is a aalog compoet commoly embedded with a microprocessor core o a mixed-sigal chip, e.g., the basebad modem used i wireless termials. Y. Zizius et al. [] showed that the ADC s performace (i terms of resolutio) is affected by substrate oise. They determied that substrate oise ca degrade the ADC s effective umber of Figure 7. The TIQ comparator of the PRA-ADC V m is adjusted by chagig the ratio of (W/L) p ad (W/L). The threshold of the comparators is determied by Eq-3. V m ( V DD VTp ) + VT µ pw p Eq-3 r =, + r r = µ W Aalyzig the ADC s Noise Error V m fluctuates whe the threshold voltage of the PMOS or NMOS trasistors chage due to substrate oise. I geeral, the threshold voltage is determied by Eq-4. V V + γ ( φ + V ) Eq-4 T = T SB φ V T is iflueced at ru- time by variatios i V SB (sice the other parameters are determied by the semicoductor techology). V SB ca be modeled as i Eq-5 []. = V = A si( ω t + ϕ) Eq-5 SB (A : a variable with uiform distributio for the magitude of V SB, ω : the harmoic of digital switchig frequecy, φ: phase shift variable uiformly distributed from to 2π) This variatio i V SB, ad thus V m, is directly related to the substrate oise. Thus, the TIQ comparator is vulerable to 99

5 substrate oise. Figure 8 illustrates a simplified equivalet circuit for digital oise ijectio i the TIQ comparator. As show i the figure, ay disturbace ijected from the microprocessor core is coupled through the substrate ad chages the body bias (V SB ) of the TIQ comparator. Variace Figure (a) shows the distributios of three comparators i a PRA-ADC (V m (i-) is from the lower ad V m (i+) is from the higher bit comparators). Assume that the iput voltage, V i, is less tha the mea of V m (i-). Whe V m (i) is i Regio, the i th comparator outputs a. This is obviously a error ad causes the ADC to overestimate the output value. For the opposite case, the ADC outputs a uderestimatig the output value. These errors cotribute to the quatizatio error. The probability of error is deterthe quatizatio error. The probability of error is determied by Eq-6. P e =.5(P e (regio ) + P e (regio 2)) Eq-6 Figure (b) shows the probability of error defied by Eq-6 for a 6-bit PRA-ADC with up to 3 TIQ comparators. It ca be clearly see that the larger the oise, the greater the probability of error. (a) The distributio of V m Figure 8. Digital oise ijectio The mea ad variace of V m (ad, thus, the accuracy of the least sigificat bit of the TIQ comparator) ca be estimated usig Eq-3 ad Eq-4. Figure 9 shows the estimated distributio of V m alog with the level of oise for a usec (, samples) period at a GHz samplig rate (assumig.8 micro techology with a.8v supply). All magitudes of oise are RMS values. From Table 2, which summarizes the mea ad variace values, it ca be observed that while the mea chages oly slightly, the variace icreases as V SB icreases. This implies that the larger the V SB, the larger the errors. For simplicity, we assume that the distributio of V m is Gaussia ad that each TIQ comparator s distributios are idepedet. Number of samples Vm (V) Figure 9. The distributio of V m Table 2. The mea ad variace with V SB V SB (RMS) 22.9mV 32.6mV 65.2mV 98.6mV Mea (V) Probability of error mV 32,7mV 65.4mV 96.8mV 2 3 Number of comparators (b) The probability of error Figure. The probabilistic error aalysis Strategies for Desigig Noise Tolerat ADC s I this sectio, we discuss how we ca cotrol the resolutio of the PRA-ADC to avoid the serious performace degradatio due to oise. We agai use a probabilistic approach, except that the oise model of Eq-5 is replaced by the determiistic model extracted from SimplePower. We chose three bechmark codes that have differet RMS distributios. I Figure, the RMS of haoi.c is cocetrated i the rage. to.2; the RMS of is cocetrated i the rage. to.3. The RMS of matmult.c is also cocetrated i the rage. to.2 but has a secod critical oise rage from. to.2. Thus, we ca expect that executig haoi.c will icur less PRA-ADC error tha. For matmult.c, the overall probability of error is less tha but it has critical poits that may cause ADC errors. I Figure 2, the probabilities of error for each bechmark are sorted by the various PRA-ADC resolutios. Our PRA- ADCs use 5-bit, 6-bit, ad 7-bit resolutio. We assume that serious performace deterioratio takes place whe the probability of error is over -4 (chose based o bearable error rates i cellular systems [2]). Figure 2(a) is the probability of error for the 5-bit resolutio PRA-ADC ad all error rates are uder -9. Figure 2(b) is the probability of error for the 6-bit resolutio PRA-ADC. I this case, oly matmult.c passes. For ad haoi.c we should, 92

6 istead, use a 5-bit resolutio PRA-ADC. Figure 2(c) is the result of 7-bit PRA-ADC which fails to achieve bearable error rates for all three bechmarks. Whe pipelie register gatig is eabled, SimplePower selectively gates uused subsets of the pipelie registers thereby reducig the eergy cosumptio of the pipelie registers. This techique ca also be used to reduce substrate oise (as the sequetial circuits are a large cotributor to oise). Figure 2(d) shows the probability of error of the 7-bit resolutio PRA-ADC whe pipelie register gatig is eabled. I this case, we ca use always the 7-bit PRA-ADCs for matmult.c. Thus, if we kow the software that will be executed o the embedded core, we ca determie the resolutio of the PRA-ADC that gives bearable error rates. We ca desig to avoid uexpected errors i the ADC as well as to lower eergy cosumptio. This is a fixed mode approach sice the ADC resolutio is fixed before ruig the software. If we ca chage the PRA-ADC resolutio i real time istead of fixig the resolutio before had, we ca obtai more performace from the ADC whe higher resolutio is required. Figure 3 represets the probability of error per clock cycle. From the result of Figure (b), it was determied that we caot use a 6-bit resolutio PRA-ADC for. I Figure 3(a), the error profile of is show. If we ca dyamically select the resolutio based o this profile, we ca use the 6-bit resolutio except for several cycle duratios that are over -4. I case of matmult.c, a 7-bit PRA-ADC ca be used except durig a few time periods. I this case, the oise profile geerated from SimplePower idicates whe the PRA-ADC ca be used at its optimal resolutio durig the executio of a program. CONCLUSIONS We have preseted a di/dt oise estimatio method usig a modified SimplePower power simulator that allows us to study the ifluece of ruig software o substrate oise i mixed sigal systems. A ew model for accurately determiig the curret profile (eeded to estimate di/dt oise) was developed. We also established oise maagemet strategies for adaptive resolutio ADCs with which we ca reliably cotrol the performace of the ADC i the presece of substrate oise. Give that aalog compoets each have their ow uique characteristics i respose to substrate oise, we are curretly ivestigatig how other aalog compoets ca be similarly adapted. ACKNOWLEDGMENTS This work was supported i part by the GSRC DARPA/MARCO Focus Ceter ad by NSF grats NSF9385 ad NSF haoi.c r.m.s. (V) (a) haoi.c r.m.s. (V) (b) matmult.c r.m.s. (V) (c) matmult.c Figure. Noise distributios of the three bechmarks REFERENCES [] M.V.Heijige, et.al., High-level simulatio of substrate oise geeratio icludig power supply oise couplig, Proc. of DAC, 446~45, 2. [2] Y.Jiag, et.al. Estimatio of maximum power supply oise for deep sub-micro desigs, Proc. of ISLPED, ~2, 998. [3] Y.Eo, et.al., New Simultaeous switchig oise aalysis ad modelig for high-speed ad high-desity CMOS IC package desig, IEEE Tras. o Advaced Packagig, 23(2):33~32, 2. [4] E.Grochoswski, et.al., Microarchitectural simulatio ad cotrol of di/dt-iduced power supply voltage variatio, Proc. of HPCA, 2~, 22. [5] 92

7 .2 x -9.4 Probability of error haoi.c Probability error haoi.c No. of comparators.2 x -3 (a) 5-bit without gatig N o. o f co m parato r 4 x -7 (c) 7-bit without gatig Probability error haoi.c Probability of error haoi.c No. of comparator (b) 6-bit without gatig Figure 2. Probability of error No. of comparators (d) 7-bit with gatig Probabilty of Error Probability of Error cycle (a) 6-bit () [6] J.Yoo, et.al. A power ad resolutio adaptive flash aalogto-digital coverter, Proc. of ISLPED, 233~236, Figure 3. The probability per clock cycle cycle (b) 7-bit (matmult.c) [] M.Gustavsso, et.al, CMOS data coverters for commuicatios. Kluwer, 2~59, 2. [7] [2] [8] P.Larsso, Power supply oise i future IC s: A crystal ball readig, Proc. of CICC, 467~474, 999. [9] A.Waizma, C.Chug, Resoat free power etwork desig usig EAVP methodology, IEEE Tras. o Advaced Packagig, 24(3):236~244, 2. [] Y.Zizius, et.al, Aalyzig the impact of substrate oise o embedded aalog-to-digital coverters, Proc. of ICCSC, 26~28, 22. [3] D. Su, et.al, Experimetal results ad modelig techiques for substrate oise i mixed-sigal itegrated circuits, IEEE J. Solid State Circuits, 28(4):42~429, 993. [4] D. Ozis, et.al, A efficiet modelig approach for substrate oise couplig aalysis, Proc. os ISCAS, vol. 5, ,