Outline. Supply system EM, IR, di/dt issues (2-34) - Topologies. - Area pads - Decoupling Caps - Circuit failures - Can CAD help?

Transcription

1 Outlie Supply system EM, IR, di/dt issues (2-34) - Topologies - Area pads - Decouplig Caps - Circuit failures - Ca CAD help? q Sigal Itegrity (35-53) RC effects Capacitive Couplig Iductace CAD solutio Advaced process solutios (54) Coclusio (55)

2 Supply System Itegrity - Layout Domai Where RLC ad EM come ito play - IR degrade voltage levels o gates supplies >> Speed reductio, fuctioal failures - L*di/dt cause rigig o supply lies >> Ca cause fuctioal failures >> Supply lies collapse - EM ca cause discoects ad failures i the field Page -3- Voltage Drop To Gate (Treds) Vcc=3.3V 1998 Vcc=2.5V x2001 Vcc=l.8V 2004 vcc=1.5v 2007 Vcc=l.2V Supply Error Ldildt Tester Error Pad to Block Block to Gate

3 Supply etworks - Layout Domai Supply system s topology l Area pads Decouplig capacitors Page -5- Supply system s topology l Requiremets >> Miimize IR drops ad EM problems >> Elimiate the eed to model iductace (tight curret loops) >> Miimize impact o floor pla Miimum area hit Allow hierarchical desig ad last miute chages Do ot obstruct other critical sigals >> Allows physical access to lower layers for test Much lower priority. We almost lost it ayhow

4 Supply System Topologies. Grid System Routed System Page -7- Routed System + Floor pla friedly Does ot plate the top layer with metal ad allow top layer routig, util... Fial EM IR simulatio are complete, may violatios revealed - Log curret loops (I practice we do t kow how to model iductace of the o-chip supply systems. Eve if we ca, we do t kow how to fix iductace problem if we fid oe) - Area Pads eeded o large chips Power must be supplied from the ceter to miimize EM IR effects :: Page -8-

5 Routed System (co t) - Curret crowdig; lots of IR & EM problems Lie Curret = I Lie Lie Curret = 3*I Page -9- r I a I I Area Pads Extra supplies ito the core *Narrower supply lies ca be used Smaller area pealty *Greater floor pla of di/dt, EM, IR effects (Depeds o how may are placed) Disadvatages *Locatio kow late i the desig Solutio: Force them from start ad desig aroud them Complicates iitial debug (Coect oly supplies to these pads!) Solutio: Debug without them at slower speed *Alpha Particles are back!! *Packagig cost (Keep away from SRAM arrays) Page

6 Grid System + Short curret loops, Lower iductace + Uiform curret distributio, less IR, EM problems - Restrictive floor pla, hard to place blocks ad route top layer sigals But you kow it i advace ad work aroud it Power System Layout (Compariso) Gridded System Routed System Iductace + IR Drops EM Floor Pla Area Pads usage Very restrictive. Allows local Griddig l More floor-pla flexibility + Everythig looks great util about 2 moths before tapeout. Slglficat area reductio. I some cases, the oly eabler to route a reliable supply system Page-12-

7 Power Network di/dt a Geerated gates by simultaeously switchig Assisted by package iductace Most of it is aroud the clock edges Page-13- Power Network - di/dt Issues -Lots of di/dt Large decouplig cap Noise aroud clock Lowest oise tolerace Should. we separate their power supplies from each other? P age -14-

8 Shortig I/O to Core supply l I/O ijects commo mode oise ito the core system However: l l l As speed requiremets go up ad Vcc dow I/O swig(curret) gets smaller With area pads package L is very small O chip decouplig cap might be helpful for the I/O circuits Page -15- Isolatio of Power Networks (co t) Solutio: We do t eed to decide Layout two separate systems (I/O ad Core) ad allow for top level short, i selected locatios. This way you keep your optios ope (For separate I/O supply; icrease umber of I/Os per Vcc/Vss pair - 4 is a good umber) - I/O ca be separated from the core o the tester to see what works best - Critical had shake sigals, to other chips, should always have their ow supply Miscellaeous - l/o is also a very coveiet locatio for Core s decouplig capacitors placemet...

9 Isolatio of Power Networks (Memories) Large memory arrays have the highest i itrisic decouplig cap/area - Ca cotribute to the core decouplig cap -> Short to core - But what about the sese amps? -> Isolate from Core - Desigers solutio => Desig sese amps with high commo mode oise rejectio ad short the supplies. If you ca t sleep at ight, do the l/o trick. PLL ad other aalog circuits - Normally separated all the way to the board, reasos: - Very high accuracy required (phase shifts, bias circuits etc...) - Very few circuit guys ca wi a argumet with a aalog desiger - Take ito cosideratio the voltage level differeces of the sigal o the iterface ito the chip s core circuitry Overcomig di/dt problems - O Chip Decouplig Capacitors + Bypass the package iductace durig istataeous switchig - Normally made out of gate cap, ca impact yield - Must be take ito cosideratio durig chip plaig How much you eed to add: 1st order depedecies: - Clock distributio style (umber of bufferig stages, edge rates ad swigs) less clock buffers -> more oise - Total memory ad logic o chip (itrisic decouplig cap) - Architecture: Number of flops ad their size Page-17- Page-18-

10 Decouplig Capacitor Sizig (Simulatio Setup) vcc Clk Clk Clk Clk 1 -> 0 0-> 1 1 -> 1 0 -> 0 Pad vss Lead (L) / # pads 1/4 of the trasitio X -> Y 1/8 of the gates o chip Vss Vss Decouplig Capacitor Sizig (Co't) Half of the bits i all the memories level Page -2O-

11 Decouplig Capacitor (Itrisic) Rough estimate of how much itrisic cap your ext chip will have: - Take similar existig chip (if you have oe) - Measure its capacitace betwee Vcc ad Vss - Multiply by trasistor cout ratio betwee the chips Decouplig Capacitors Implemetatio - Gate capacitace of trasistor i accumulatio cadidate is a good >> Watch for yield impact!! Vcc Vss Psub Nwell l Keep L arrow to reduce resistace l Tile multiple decouplig cap cells Page-21- Page-22-

12 Power Network layout - Ca CAD Help? Power et aalysis for EM ad IR - There are commercially available tools >> Iput: Layout, Block s curret cosumptio or simulatio vectors >> Output: Violatios dow to the cotact layer >> Missig: I some cases its ot clear what eeds to be doe i order to fix a problem - Area Pad Placemet Advisor >> Miimizes IR drop, does ot hadle di/dt Page -23- Supply System Itegrity Circuit Techiques ad Pitfalls Page -24-

13 Supply System Itegrity - Circuit Domai (I/O) - Cotrol edge rate of I/O drivers for peak curret reductio - Reduce umber of I/O buffers per Vcc/Vss pair - Reduce I/O swig >> Off Chip I/O sigal itegrity become a issue Example: 300mv differetial are used for 1Gb/sec media chael (Source ad load termiated, o chip) Page -25- Regeerative Structures l Supply of all the gates must be shorted, respectively together to the same metal wire Noise here will flip the latch Vccl BAD - Noise is differetial Supply oise might flip the latch GOOD - Noise is commo Ca hadle ay supply oise

14 Latchup JJ JJ *Well ad Source of P pull-up must be shorted to the same metal lie La chup trasistor ca ope "P trasistor Loss of data due to differet supply levels across the chip JJ JJ vcc2 Low = Vss1 Precharged Node *If Vss>Vss2 the ode + will discharge eve whe the iput is Low I Vss2 *If Vss1 <Vss2 or Vcc1>Vcc2 the pass gate will ope ad the latch will loose data Page -28-

15 Solutio: Supply Adjustmet ERC Rule: Sigals that come from a differet block or from large distace must have their supply adjusted Iputs to pass gates ad precharged logic caot be placed directly o block s iputs ad must be buffered Simultaeously switchig buffers All the drivers ca switch together The large drop o the local Vcc ca cause sesitive circuits to fail Data Path drivers Dyamic Gate Solutio: Do t share the wire at the lowest level Page-30-

16 Short Circuited Muxes ad tri state buffers El E Tri-State Drivers *If El ad E2 overlap Large Short Circuit curret will flow ad ca cause IR ad EM problems *Problem is worse i Tri State drivers because they ormally drive global sigals. These sigals rarely have a ower Vcc MUX L El E2 *Solutio: *Strict timig methodology *Assig ower for Tri Stated global sigals JJ Precharged Nodes: Sigle Eded Sese Amplifiers Problem Solutio: Retetio Device Page -32-

17 Takig EM ito cosideratio (SPICE) First step: get the data (curret/uit width per layer) 3 umbers are required >> Uidirectioal curret (Supply lie simulatio) >> Bi-directioal curret (Sigals lie simulatio) Lie s resistace helps here ad limits the curret >> Peak curret Simulate the circuits at the highest operatig temperature (EM) - Lowest temperature for Peak curret (most desigers do t ru the simulatio ad simply multiply Average by 10 ad see if thev pass) Page -33- Takig EM ito cosideratio (CAD) Geeric Power Svstem CAD tool Iput: - Blocks curret cosumptio - EM limits per layer - Layout Process: - Replace all gates with curret sources - Replace power system with resistors (dow to the cotact level) output: - Poits EM, IR violatios (the good tools, show it i the layout) But... - How do I fix a problem whe I fid oe?? JJ Page -34-

18 Sigal Itegrity Page -35- Capacitive Couplig *Sigals do ot see the groud aymore Coupled oise ca drag the sigal half the supply supply swig up/dow Severe problem for physically log sigals *Very sigificat delay icrease *Noise couplig ca lead to fuctioal failures P age -36-

19 Metal Couplig Total Capacitace Icrease 4.0 I % total % total % total cap cap cap icrease icrease icrease (M4) (M3) (M2) % total cap icrease (Ml) Wirig Treds (High-Ed VLSI) Exteral Supply Number of Layers Number of o-chip I/Os (xlooo)[chip to Package] wire legth(km) + Wire Delay (s/cm) u u 0.25u Geeratio u Page -38-

20 Capacitive Couplig (delay) Work aroud Simulate for it - Use a library of macros for SPICE that represet various switchig coditios aroud the wire - Map the couplig effect ito icreased capacitace Spice Wire Segmet l L T T T = Layer type: Ml,2,3,4,5 U = % Coverage of ext layer up D = % Coverage of ext layer dow M = % of layers up/dow/side that switch i the opposite directio Capacitive Couplig (delay) - Work aroud (Co t) - If topology is ot kow assume the followig 30% Coverage N+2 70% Coverage Layer N C o v e r a g e 30% Coverage N-2 With 2 parallel lies ( oe is switchig i the opposite directio) Page-39- Page40-

21 Wire RC Icrease - Repeaters Lie delay f(legth 2 ) I theory use the followig scheme Page -41- Repeaters (co't) l Real world : Repeaters ed up beig placed where there is room, hopefully close to where they really eed to be l Real world: use double bufferig for repeaters l Sigle repeater ivert the logic level -> verificatio -3 ightmare (Iserted towards the ed of the project; mostly the case) l Verilog descriptio, of the block that eeds to place the repeater, eeds to chage Page -42-

22 Circuit desig solutios for wire s RC - Drive from both sides: Ed Of The Lie amplifier *If the lie is pre-charged or is the clock, the circuit ca provide some speedup ad sharpe the edge at the destiatio *If the lie is CMOS, the amplifier will kill the delay due to spurious trasitios Dealig With RC delay (tred) Today Chip to Chip Delay, Chip iteral Delay Short Delay betwee blocks Block to Block Delay Block Iteral Delay Block Tomorrow Chip Block Architecture chages to 1 Page

23 Lie Couplig (Noise) Ca (does) cause fuctioal failures Solutios: - Layout >> Shieldig, Spacig - Circuit Log lies MUST be drive at all time, the driver will resist the oise (still a problem i the ed of a log lie) If a log lie is precharged it has to be physically isolated Set the trip poit of a log lie receiver at half Vcc Differetial sigalig (oise is commo) Noise suppressio circuits CAD ca help a lot here Sigal Couplig Failure Mechaism Groud bouce make it much worse Most of the supply failure circuits show up here Page -46-

24 Circuit desig solutios for couplig - Resist to chage at the destiatio: Ed Of The Lie filter l Circuit will slow dow the ode i retur for some more oise margi CAD (layout) Solutios Wide wire routig (Less R but more C) Cross talk predictor ad aalyzer - Combie timig ad LPE data to detect victims ad adjust spacig Before Aggressor Victim Aggressor Aggressor S p a c e Victim Space Aggressor. Shieldig for clock ad log bus lies.... vss Spacig Wire Virtual wire Wire for routig vss After Shieldig + short retur path (Low

25 CAD Solutios (Co t) Layer N+1 *Eforce orthogoal routig scheme *Miimizes chaces for log parallel sigals betwee layers Drive Placemet for Std. Cells a lot of statistics for wire load =f(faout) for accurate estimates Clock distributio: Exercise i RLC, EM ad IR optimizatio q Cotributors to clock skew >> RC: Skew i clock wires >> IR: Skew betwee clock drivers that are coected to differet supplies >> EM: Will fuse your wire if its too arrow (but oly later, after a recall will be a real disaster) Page -5O-

26 Clock - Some solutios L IR Matchig wire legth Cotrollig topography (spacig from other wires, shieldig) Poisso solver tools for delay aalysis Routig adjacet Vss lies -> tighter loops Add bufferig stages to the fial load -> di/dt reductio Clock gatig, maily for power reductio, also helps here Cotrol clock edge rate - Add IR impact to the clock skew budget EM (the oly failure that your customer helps you fid) - Aalysis tools o fial layout - Take lots of margis! Page -51- Sigal Iductace Fuctio of curret loop area Extremely hard to model i practical cases - Wires are brachig ad have distributed loads - Curret loops through the substrate Log wide lies are at risk Fuctio of R+jwL where w is harmoics of clock frequecy Great source for lots of scietific articles but circuit desigers will do whatever it takes to exclude o chip L from cosideratios Page

27 I I Coclusio Supply system - CAD tools must tur from critics to cosultats - Topology should eable the omissio of o chip iductors from the game - Circuitry must be very robust for commo mode supply oise (because it will be there) - Adjust supply levels whe travelig log distaces - O Chip Decouplig Caps become a must Sigal itegrity - Accurate prelayout parasitic estimate eeded - Timig drive placemet of std. cells - Couple timig ito global routers for oise aalysis Page -55- Coclusio (Co't) Post layout oise aalyzers ad optimizers required Push repeaters placemet to early desig stages Architecture chages for miimizig log distace travel across the chip Ivest time i circuit ad layout techiques that will avoid dealig with sigals iductace, it will be less tha the time spet i iductace modelig ad its related bug fixes Page -56-