A 100 ma Fractional Step-Down Charge Pump with Digital Control

Transcription

1 A 100 ma Fractioal Step-Dow Charge Pump with Digital Cotrol Valter A. L. Sádio 1,2, Abílio E. M. Parreira 2, Marcelio B. Satos 1,2,3 1 IST / 2 INESC-ID, Rua Alves Redol 9, Lisboa, Portugal Silico Gate, UPTEC Rua Actor Ferreira da Silva, Porto, Portugal, ABSTRACT A switched capacitor step-dow DC-DC coverter (charge pump) is proposed. High efficiec is achieved b combiatio of fractioal coversio ratios (differet step-dow modes of operatio), output voltage sesig ad pulse skippig based digital cotrol techiques. Two cotrol techiques were implemeted with automatic chage betwee modes ad their results are discussed ad compared. The power module has 9 switches, implemeted with 14 power trasistors, ad a curret limit circuit to mitigate the i-rush curret i startup phase. This circuit has bee desiged i AMS C35B4 (0.35um) CMOS process. The charge pump was desiged to provide a maximum load curret of 100mA. The peak-to-peak output voltage ripple is less tha 20mV with two 3uF flig capacitors ad oe 22uF output capacitor. Peak ad average efficiecies, with maximum load curret, are about 75% ad 67%, respectivel. Kewords: charge pump, DC-DC coverter, self adaptive, digital cotrol, curret limitig, load trasiet, efficiec. 1. INTRODUCTION I recet ears, iductorless switched capacitor DC-DC coverters have become more attractive i compariso to tpical iductor based DC-DC coverters due to their simple cotrol, good cost/efficiec relatio, high power desit, low EMI ad fast developmet time. A charge pump DC-DC coverter is a simple ad low cost solutio to covert uregulated batter voltage to a costat regulated voltage i itegrated circuits. Differet coversio ratios ca be implemeted i a step dow charge pump ad the efficiec achieved is strogl depedet o the vout/vi versus the coversio ratio relatio. Limitig the umber of exteral flig capacitors to two, there are four possible modes of operatio that correspod to differet coversio ratios: 1/3, 1/2, 2/3 ad 1/1. The mai purpose of this work is to show that, b self adaptig the operatio mode to the load curret ad iput voltage, charge pumps ca exceed iductor based DCDC coverters efficiec, especiall for light loads, while presetig lower area ad lower retargetig costs. Several methods are used owadas to regulate output voltage i charge pumps, each with advatages ad disadvatages. Costat frequec cotrol [1] with two sequeced phases of operatio is used with a trascoductace amplifier that compares the output voltage with a voltage referece ad cotrols the amout of charge ijected i the flig capacitors. The output capacitor is charged whe the output voltage is too low. This cotrol scheme has a well defied oise frequec spectrum that ca be filtered, but has poor efficiec with light loads. Curret mode cotrol [2, 3] ca be implemeted with a curret sesig circuit, usuall a series sesig resistor, with large power loss, or with a curret sesig trasistor i parallel with the power trasistor that demads additioal circuitr. This kid of cotrol is used with dut ccle close to coversio ratio to achieve low output voltage ripple i high load coditios. Pulse skippig [4] is used with costat switchig frequec ad costat dut ccle with charge ad discharge modes of operatio. The charge pump operates o charge mode whe the output voltage drops below a pre-determied threshold voltage, otherwise operates with miimum suppl curret i discharge mode, where the output capacitor supplies charge to the load. This cotrol method is ver good to improve efficiec with light loads ad has fast respose to load variatios but produces high output voltage ripple.

2 Burst Mode [5] is a cotrol methodolog that, whe the load curret load is less tha a prescribed threshold, the clock is tured o ad off for a umber of clock ccles that deped o the curret absorbed b the load. This method allows high efficiec with light loads but produces high output voltage ripple ad high toal spectrum. The charge pump preseted i this work operates with differet fractioal ratio modes ad has two pulse skippig alterative digital cotrol blocks implemeted. These alterative cotrol techiques are discussed ad compared regardig their associated costs; achieved efficiec ad output voltage ripple with differet iput voltages ad output currets. A soft-start circuit that limits the irush curret at the startup phase is also preseted. The ol exteral compoets required for the charge-pump operatio are the two flig ad oe output capacitor. The structure of this paper is the followig: i sectio 2 a diagram block is preseted with the architecture of the complete sstem, the fractioal modes are preseted ad the power module ad the curret limit circuit are explaied; sectio 3 presets the two digital cotrol strategies that self adapt the mode of operatio to the iput voltage ad output curret; i sectio 4 the simulatio results of the overall sstem are preseted ad sectio 5 presets the coclusios of the work. 2.1 Sstem Descriptio 2. CHARGE PUMP TOPOLOGY The structure of the charge pump is preseted i Figure 1. The digital cotrol uses four digital iputs provided b four differet comparators: oe that compares Vout with a referece voltage ad three comparators that compare 2/3, 1/2 ad 1/3 of Vi to the referece voltage, providig the iformatio of which mode is theoreticall possible. I fact, the lower mode idetified b these comparators ma ot be possible if the load curret is high. Therefore, the cotrol methods preseted i sectio 3 are required to costatl adapt the mode of operatio to the iput voltage ad load curret. Figure 1. Charge pump topolog.

3 The power module ad the two exteral capacitors implemetatio of the differet modes is discussed i sectio 2.2. The power switches allow differet itercoectios betwee the iput voltage, the flig capacitors ad the output load, implemetig differet fractioal coversio ratios. 2.2 Power Module ad fractioal modes of operatio Figure 2 presets the power block structure. It is composed b ie switches with fourtee MOS trasistors ad with two exteral flig capacitors. Figure 2. Schematic of the power switches used i the charge pump. SW1 ad SW3, coectig the flig capacitors to the iput voltage were implemeted with PMOS power trasistors, i order to eable full rage operatio whe Vi is also used to suppl the charge pump drivers. Switches that coect flig capacitors termials to groud were implemeted with NMOS trasistors, allowig lower area implemetatio for equivalet RDS resistace. The remaiig switches were implemeted with NMOS ad PMOS trasistors i parallel, implemetig a low equivalet R durig startup ad ormal operatio i all modes. Sice the process used is sigle well, NMOS trasistors have their bulk i a commo substrate biased to groud. The - well of all PMOS trasistors could be coected to Vi, however, i trasistors where the source is at a lower voltage, bod effect rises the threshold ad resistive losses icrease or the area must be icreased. Therefore, the bulk of PMOS trasistors was tied to Vi ol whe this ode is alwas the source or whe there is o other ode at a higher or idetical potetial the the source. As a cosequece of this aalsis, the -well of SW2 ad SW9 PMOS trasistors are biased to ode B, reducig bod effect, ad without bulk curret. This power module ca be cofigured to implemet four coversio ratios: 1/3, 1/2, 2/3 ad 1/1. Each coversio ratio cosists i oe mode of operatio that correspods to a capacitive divisio betwee the iput ad output voltage. I the first three modes listed, coversio ratios are obtaied alteratig betwee two clock phases with differet switches cofiguratio. The switches tured o i each phase for each mode of operatio are idetified i Table 1.

4 Table 1. Power switches cofiguratios. Ratio Phase 1 Phase 2 Off 1 / 3 1, 4, 7 2, 6, 8, 9 3, 5 1 / 2 1, 5 2, 6 3, 4, 7, 8, 9 2 / 3 1, 3, 5, 8 2, 4, 9 6, 7 1 Alwas O : 1, 2, 3, 9 4, 5, 6, 7, 8 Table 2 shows the voltages i the flig capacitors for the switches cofiguratios preseted i Table 1 whe Iout = 0. Trasitios betwee modes 1/3 ad 1/2 have o impact i the flig capacitors voltages. However, sice mode 2/3 is the ol oe with lower voltages i the flig capacitors, whe leavig this mode the flig capacitors eed to be recharged. The procedure implemeted to solve this problem is described i sectio 3. Table 2. Voltage i the flig capacitors at each mode of operatio with Iout = 0. Mode {cm1 cm0} Ratio C1 C / 3 Vout Vout / 2 Vout Vout / 3 Vout / 2 Vout / NC NC 2.3 Curret Limit circuit I order to limit the Joule power losses, power switches are desiged to exhibit low equivalet resistace (earl 3 Ohm). Whe the charge pump is powered with the flig capacitors ad output capacitor discharged, the curret would be i the order of magitude of amps. I order to limit this irush curret durig the startup phase a curret limitig circuit was implemeted i the power trasistors coected to the suppl source, sw1 ad sw3. This circuit is represeted i Figure 3. Figure 3 shows the schematic of the driver ad curret limitig circuit for SW1, implemeted b MP1, cotrolled b sw iput sigal. MP2, MP3, MP4, MN0 ad MN6 implemet a sesor of the curret i trasistor MP1. Sice MP1 is i the triode regio, MP2 ca ol mirror its curret if both source to drai voltages preset similar values. MP3 ad MP4 have the purpose to brig the drai of MP2 voltage ear the voltage of the MP1 drai. This is accomplished b desigig MN0 ad MN6 with the same ratio as MP4 ad MP3. Therefore, MN0 ad MN6 force currets that cause the same gate to source voltages i MP3 ad MP4 ad sice their gate is commo; their sources will preset similar voltages. The saturatio curret of MN6 is compared with the curret mirrored b MP2 ad the iput of a voltage amplifier, A, is pulled dow or pulled up depedig o the relative values of these currets. Whe MP1 curret is lower the the limit, the ratio to MP2 is lower the the curret i MN6 ad the iput of A is pulled dow, allowig miimum RDS i MP1. If the curret i MP1 exceeds the limit, MP2 pulls up the iput of amplifier A ad limits the curret i MP1. I order to esure stabilit, a AC ope loop aalsis was performed ad compesatio was added. For cleaess, the correspodig RC compoets were omitted i Figure 3. MP39 ad R3 slow dow the tur off of MP1 b itroducig two phases. Whe sw chages from high to low logic level, turig o MP45, the iitial reductio o the VSG of MP1 is helped b MP39. However, whe MP1 starts to cut-off, so does MP39 ad the secod phase of VGS reductio is accomplished b R3 aloe, limitig di/dt i the Vi bodig wire ad therefore the iteral suppl voltage peak caused b turig off the iput curret.

5 MP43, MP44 ad MP45 are used to limit MP1 curret i the startup phase. MN3 turs off the referece curret whe sw turs off MP1 ad the curret limitig cell is disabled i power dow mode, with all curret mirrors tured off. MN44 ad MP6 short, respectivel, to groud ad to suppl voltage the gates of the idle curret mirrors. Figure 3. Curret limitig circuit. 3. DIGITAL CONTROL The major challeges i the fractioal charge pump cotrol desig are: 1) mode optimizatio; 2) output voltage ripple miimizatio ad 3) area ad power cosumptio miimizatio. Mode optimizatio has high impact i efficiec sice a higher mode, tha the miimum required, causes uecessar Joule losses while trasferrig charges betwee capacitors with sigificatl differet voltages. Two cotrol algorithms were implemeted ad are described i the followig subsectios. Their criteria for chagig modes are differet ad will be prelimiaril evaluated i sectio 4. Output ripple eeds to be miimized i order to fulfill the purpose of the work: to prove that a charge pump ca be a replacemet for a iductor based DCDC coverter, sice the output filter of buck DCDC coverters ca limit the ripple to a miimum, especiall if the output capacitor has low ESR. Both cotrols implemeted use equivalet techiques to miimize output ripple based o omittig Phased 1 (of Table 1) util the charge of the flig capacitors becomes isufficiet to recharge Cout.

6 Area ad power miimizatio is a geeral cocer while desigig microelectroic circuits. However, i the desig of a DCDC coverter, the cosumptio of the cotrol circuitr has a major height i the efficiec at light loads sice the cotrol cosumptio compares to the load useful power. Therefore, the two cotrols use two radicall differet logic stles: schroous ad aschroous, i order to evaluate the relative impact of the cotrol power cosumptio. Additioall, the power cosumptio was miimized at sstem level b disablig the three comparators o the top of Figure 1 as well as turig off a switch i series with the voltage divider of Vi ad eablig this circuitr ol whe the miimum possible mode eeds to be sesed. Therefore, ol the output voltage comparator is permaetl eabled, ad this is a switched comparator that sources less the 1uA. 3.1 Cotrol Desig I vout > vref? vout recovered i m ccles? vout < vref durig k ccles? "mode -1" possible? chage mode up chage mode dow Figure 4. Diagram of cotrol I. Figure 4 presets the block diagram with the fuctioalit of the first cotrol implemeted. As show i Figure 4, the criteria for chagig to a mode able to provide higher voltage ( chage mode up ) is based o the umber of clock ccles with the output voltage below the referece value. The criterio to chage to a lower mode has two coditios: if the lower mode is possible ad if, after Vout < Vref, Vout recovers to Vout > Vref i oe or two clock ccles. A schroous, 1MHz clock, state machie was desiged with this fuctioalit, with the refereced costats made programmable via SPI. The trasitio betwee mode 2/3 ad mode 1/2 was treated as a special situatio sice, as explaied i sectio 2.2, flig capacitors i mode 2/3 preset a voltage equal to Vout/2 while i mode 1/2 preset voltage Vout. Mode 1/1 was implemeted accordig to Table 1, with the flig capacitors off, ad therefore, the trasitio from mode 2/3 to mode 1/1 was ot problematic. Whe chagig from mode 1/2 to mode 2/3 there is o impact o Vout ripple sice the excess of charge i the flig capacitors will be delivered progressivel to the output capacitor as required b the load. O the

7 cotrar, whe chagig from mode 2/3 to mode 1/2, the lack of charge i the flig capacitors would cause excessive ripple if Phase 2 of mode 1/2 was forced (see Table 1). Therefore, i order to avoid the excessive output ripple, ad to allow the flig capacitors to recover the required charge, the iitial W ccles i mode 1/2 istead of Phase 2 will have repeated Phase Cotrol Desig II The secod cotrol block diagram is preseted i Figure 5. The criteria to optimize the mode of operatio cosists o trig the miimum, sesed b the resistive divider of Vi, ad if it fails to pump Vout to the required value, after k clock ccles, the ext mode is used util the required Vout value is achieved. The criterio for gettig back to the miimum mode is based o tr ad error : the miimum mode is restores after m clock ccles ad if it proves to be isufficiet (due to the load curret), after k clock ccles of Vout < Vref, the followig mode is restored. Additioall this cotrol was desiged as a aschroous circuit, miimizig power cosumptio (ol seve registers are used). vout > vref? vout > vref j ccles? vout < vref durig p ccles? chage to miimum mode possible chage to miimum mode possible +1 Figure 5. Diagram of cotrol II. 4. RESULTS 4.1 Laout Figure 6 presets the laout of the aalog part of the charge pump. The two digital cotrols, the SPI iterface ad a digital multiplexer, for debug purposes, were placed i the ceter of the test chip, fillig a L shape free space betwee cores [6]. Figure 6 shows the placemet of the power devices, curret limitig cells ad comparators. Sice a sigle well techolog was used, a major cocer was to limit the substrate oise usig the ol available wa to iterrupt the chael stop that reduces sigificatl the substrate surface resistace: a -well rig was desig aroud the power devices.

8 Figure 6. Charge Pump laout. 4.2 Lie regulatio Figure 7 Modes of operatio for cotrol I durig a Vi sweep with Iout = 60mA. Figures 7 ad 8 show simulatio results for Vref=1.2V whe Vi chages from 1.6V to 4.8V with a load of 60mA, for cotrol I ad II, respectivel. Sigals cm0 ad cm1 idetif the mode of operatio accordigl to Table 2. For this output

9 curret, with cotrol I, mode 1/3 is sustaiable for Vi > 4V, mode 1/2 was used for 4V < Vi < 2.75V, switchig betwee modes 1/2 ad 2/3 occurs whe 2.75V < Vi < 2.5V, mode 2/3 is selected whe 2.5V < Vi < 2.25V, switchig betwee modes 2/3 ad 1/1 occurs whe 2.25V < Vi < 2V, mode 1/1 is selected whe Vi < 2V. Cotrol II causes similar decisios. Vout ripple caused b cotrol II is higher i Figure 8, whe switchig betwee modes 2/3 ad 1/1, due to the iclusio of the flig capacitors also i mode 11 i this cotrol. However, this is easil solvable i the test chip sice the switchig cofiguratio active for each mode is programmable via the SPI iterface. As the load curret icreases, the rage of Vi whe mode 2/3 is stable is sigificatl reduced ad at the maximum curret of 100mA, the charge pump does ot lock i this mode at all. 4.3 Load regulatio ad load trasiet Figure 8 Modes of operatio for cotrol II durig a Vi sweep with Iout = 60mA. Figure 9 presets the simulatio results for a load trasiet with Vi = 3V ad a Iout sweep from 0 to 100mA. Mode 1/2 is used i almost all the rage of Iout. Vout spikes i each clock ccle are due to the presece of bodig wires, to a realistic ESR for the output capacitor, to the use of the substrate as the referece poit for all voltages i the simulatio. The time betwee the requiremet of Phase 1 is progressivel reduced as the output curret icreases. Figure 10 shows a load trasiet with Vi = 2.2V ad a Iout chagig from 100mA to 1mA ad back to 100mA. It ca be see that iitial mode of operatio is a togglig betwee modes 2/3 ad 1/1 ad whe the load curret drops the mode 11 is ot required. The mode 1/2 is ot tried because it is theoreticall impossible for a 2.2V iput voltage ad a 1.2V output voltage. The curret limitig cells activit is clearl see i Figure 10. While operatig i mode 2/3, ol oe curret limitig cell is active ad, each time a Phase 1 occurs, the iput curret is limited to 120mA. While i mode 1/1, two curret limitig cells are active ad, each time a Phase 1 occurs, the iput curret is limited to 240mA. The output voltage does ot preset a sigificat drop due to the load trasiet ad the output voltage ripple is lower tha 20mV.

10 Figure 9 Load trasiet with Vi = 3V ad a Iout sweep from 1mA to 100mA. Figure 10 - Load trasiet for worst lie coditios.

11 4.4 Efficiec results Figures 11 ad 12 show the efficiec obtaied b simulatios of 500us, with differet Vi values, for Iout = 1mA, 10mA ad 100mA, for both cotrols implemeted. As previousl show i Figures 7 ad 8, both charge pump cotrols adapt to the iput voltage ad load coditio similarl a therefore the preset quite similar efficiecies. Moreover, the simulatio of 500us is ot eough to obtai a accurate value for the efficiec ad therefore it is ot clear if the differeces betwee the results are real. The simulatio is a ver time cosumig process ad ol the silico (ow i the lab) will provide clear coclusios about the usefuless of togglig flig capacitors i Phase 1 or/ad Phase 2; optimized values for each costat i the cotrol algorithm ad major efficiec differeces betwee cotrol modes. However, the major coclusios ca be obtaied: efficiecies are alwas much higher tha with a Low Drop-Out (LDO) liear regulator ad, for low currets, the most frequet situatio for most of the circuits, efficiec is i the same order of magitude as iductor based DCDC coverters. 100,00% 95,00% 90,00% 85,00% Efficiec 80,00% 75,00% Iload = 100mA Iload = 10mA Iload = 1mA 70,00% 65,00% 60,00% 1,5 2 2,5 3 3,5 4 4,5 5 5,5 Iput Voltage [V] Figure 11. Efficiec results for cotrol I with Iout = 1mA, 10mA ad 100mA. Efficiec 100,00% 95,00% 90,00% 85,00% 80,00% 75,00% 70,00% 65,00% 60,00% 55,00% 50,00% 45,00% 40,00% 1,5 2 2,5 3 3,5 4 4,5 5 5,5 Iput Voltage [V] Iload = 100mA Iload = 10mA Iload = 1mA Figure 12. Efficiec results for cotrol II with Iout = 1mA, 10mA ad 100mA.

12 5. CONCLUSION A fractioal, step-dow charge pump was desiged ad evaluated with the purpose to compare it with the most commol used DCDC solutios: LDOs ad buck DCDC coverters. The desig targeted a maximum output curret of 100mA sice this was the expected order of magitude for which a charge-pump could preset advatages over a PFM buck DCDC. The power devices topolog was preseted ad the curret limitig cells schematic was aalzed. Two cotrol methods were idepedetl desiged that led to idetical optimized modes of operatio for differet iput voltages ad output currets. Lie ad load regulatio ad load trasiet results were preseted showig that this chargepump adapts ver quickl to all possible chages of workig coditios, presetig output voltage trasiets equivalet to the ripple observed for operatio uder costat coditios below 20mV for the output capacitor used. Efficiecies are alwas much higher tha with a Low Drop-Out (LDO) liear regulator ad, for low currets, the most frequet situatio for most of the circuits, efficiec is i the same order of magitude as iductor based DCDC coverters. 6. ACKNOWLEGDMENT This work was partiall fuded b the Portuguese research project PTDC/EEA-ELC/71412/2006. [1] [2] [3] [4] [5] REFERENCES Gregoire, B.R., "A Compact Switched-Capacitor Regulated Charge Pump Power Suppl," Solid-State Circuits, IEEE Joural, vol.41, o.8, pp , Aug Shao Bi; Yag Yujia; Wag Yig; Hog Zhiliag, "High efficiec, iductorless step-dow DC/DC coverter," ASIC, ASICON th Iteratioal Coferece, vol.1, o., pp , 24-0 Oct Cheug Fai Lee; Mok, P.K.T., "A moolithic curret-mode CMOS DC-DC coverter with o-chip curret-sesig techique," Solid-State Circuits, IEEE Joural of, vol.39, o.1, pp. 3-14, Ja Saiz-Vela, A.; Miribel-Catala, P.; Puig-Vidal, M.; Samitier, J., "A electro mobilit idepedet pulse skippig regulator for a programmable CMOS charge pump," Circuits ad Sstems, ISCAS IEEE Iteratioal Smposium o, vol., o., pp Vol. 1, Ma Budaes, M.; Goras, L., "Burst Mode Switchig Mechaism for a Iductorless DC-DC Coverter," Semicoductor Coferece, CAS Iteratioal, vol.2, o., pp , Oct Sept [6] Nuo Dias, Agelo Moteiro, Marcelio Satos, Gabriel Satos, J.Paulo Teixeira, Desig-for-Debug of Mixed Sigal Cores, submitted for publicatio i the Europea Test Smposium 2009.