A Low Spurious Level Fractional-N Frequency Divider Based on a DDS-like Phase Accumulation Operation

Transcription

1 A Low Spurious Level Fractioal-N Frequecy Based o a DDS-like Phase Accumulatio Operatio Julie Juyo, Ioa Burciu, Teddy Borr, Stéphae Thuries, Éric Tourier To cite this versio: Julie Juyo, Ioa Burciu, Teddy Borr, Stéphae Thuries, Éric Tourier. A Low Spurious Level Fractioal-N Frequecy Based o a DDS-like Phase Accumulatio Operatio. MIXDES, Ju 2011, Gliwice, Polad. pp , HAL Id: hal Submitted o 3 Jul 2012 HAL is a multi-discipliary ope access archive for the deposit ad dissemiatio of scietific research documets, whether they are published or ot. The documets may come from teachig ad research istitutios i Frace or abroad, or from public or private research ceters. L archive ouverte pluridiscipliaire HAL, est destiée au dépôt et à la diffusio de documets scietifiques de iveau recherche, publiés ou o, émaat des établissemets d eseigemet et de recherche fraçais ou étragers, des laboratoires publics ou privés.

2 A low spurious level fractioal-n frequecy divider based o a DDS-like phase accumulatio operatio J. Juyo, I. Burciu, T. Borr, S. Thuries, E. Tourier CNRS-LAAS, Toulouse, Frace UPS, Uiversité de Toulouse, Frace AXESS Europe, Toulouse, Frace Abstract This paper presets a ovel architecture of a low spurious level fractioal-n frequecy divider. It has already bee show i previous work that the use of a direct digital sythesizer (DDS) represets a promisig solutio to the mitigatio of the fractioal spurs that appear at the output of fractioal frequecy dividers, but with the drawback of causig a o-liear cotrol of the divisio ratio. The DDS-based architecture proposed i this paper recovers the beefit of havig a liear tuig of the divisio ratio, while still havig similar performace i terms of fractioal spurs. Idex Terms Phase accumulator; fractioal-n frequecy divider; phase error; frequecy divisio ratio; Direct digital sythesis. f ref PFD f div Up Dow Charge Pump Figure 1. Filter Frequecy Phase-locked loop VCO f out I. INTRODUCTION The Phase Lock Loop (PLL) structure implemets a feedback loop techique that forces the phase of a geerated sigal to follow the phase of a referece sigal. I the radiocommuicatio domai, the major advatage of implemetig this techique relies o the improvemet of the phase oise (PN) performace of a voltage cotrolled oscillator (VCO). Studies show that the PN of a VCO based frequecy sythesizer is sigificatly improved whe usig PLL architecture i order to lock the phase of the VCO to that of the output of a low frequecy referece [1]. Moreover, i order to be able to take profit of the low frequecy referece PN at a high frequecy, the PLL architecture acts as a frequecy multiplier by icludig a frequecy divider i the feedback loop (Figure 1). The phase of the sigal preset at the divider output is the compared with the oe of the referece sigal by the Phase Frequecy Detector (PFD). The polarity of the phase differece measured by the PFD is used to charge ad discharge the filter with the Charge Pump (CP). This amout of charge is proportioal to the phase differece measured by the PFD ad will tur ito voltage that cotrols the VCO. Whe the loop reaches the lock coditios, the phase of the VCO output sigal will be the same tha that of the referece sigal. I order to obtai a frequecy tuig of the VCO output, the commoly used solutio relies o the use of a frequecy divider with a programmable divisio ratio. Whe speakig of Iteger-N Frequecy sythesizer, the programmig of the frequecy divider is doe oly by usig iteger values for the divisio ratio. As a cosequece, the sythesizable frequecies will be multiples of the frequecy of the referece sigal. The mai costrait of the iteger- N sythesizers is the fact that the miimum frequecy step size is equal to the frequecy of the referece sigal. I order to improve frequecy resolutio of PLL based frequecy sythesizers, we have two types of solutios: lowerig the frequecy of the referece sigal while usig a iteger-n frequecy divider i the feedback loop. keepig costat the frequecy of the referece sigal while usig a fractioal-n frequecy sythesizer i the feedback loop [2]. Each of these two solutios has its drawbacks. The decrease of the referece sigal frequecy implies a icrease of the PLL lock time, while the use of fractioal-n frequecy sythesizers geerates parasitic spurs (also called fractioal spurs) i the output sigal of the CP that will automatically degrade the PN of the global frequecy sythesizer [3], [4]. I this paper we are assessig the coceptio ad the desig of frequecy fractioal dividers as well as the impact that these ca have o the global performace of a PLL. I the secod sectio, a presetatio of differet types of fractioal frequecy dividers will be made. The third sectio will be dedicated to a ovel architecture we propose i order to realize a fractioal frequecy divider based o a DDS-like phase accumulator operatio. I the fourth sectio, we preset several simulatio results that were doe i order to validate the theoretical study cocerig the ovel architecture we propose. Fially, coclusios about this study are draw ad the follow-up to this work is provided.

3 f ref PFD Up Dow Charge Pump Filter VCO f out Divisio by P Divisio by P+1 Ideal ε f div Fractioal-N Basic out P / P+1 Basic i out V i P / P+1 ΣΔ Sigma Delta i Add msb out Reg FCW i Accumulator Compesated time Figure 3. Temporal evolutio of the phase error for three differet scearios depedig o the implemeted fractioal frequecy divider architecture. Figure 2. Fractioal-N frequecy Sythetiser ad the differet existig fractioal frequecy divider architectures. II. FRACTIONAL-N FREQUENCY DIVIDERS A. Digital Fractioal-N Frequecy Sythesis Oe of the most commo used methods for achievig a digital fractioal N-frequecy sythesis is based o divisio ratio averagig over time. I order to obtai a fractioal frequecy divisio ratio, a output sigal is geerated from a iput sigal by alteratig two or more iteger divisio ratio over time. The global divisio ratio is therefore a oiteger which value depeds o the ratios used ad o their appearace duratio as show i: N.F = N 1 P 1 +N 2 P N k P k (1) Where N.F deotes the average divisio ratio, ad Ni ad Pi are each iteger divisio ratio ad their appearace duratio. The upper part of the schematic preseted i Figure 2 shows the architecture of a digital fractioal-n frequecy divider based PLL. I the lower part we preset differet architectures that are commoly used i order to implemet the digital fractioal-n frequecydivider. For the first two implemetatio sceario, the fractioal frequecy divider architecture is based o a techique that ivolves the use of a multiple modulus iteger frequecy divider. The divisio ratio is dyamically switched over time through the use of a simple modulus cotroller. The implemetatio of this block varies depedig o the umber of iteger divisio ratios that ca be used. I fact, a simple digital phase accumulator (first order sigma delta modulator) ca be used for a sceario where the divisio ratio ca vary betwee oly two iteger values [1]. If the sceario implies the use of several iteger divisio ratios, the most suited modulus cotroller architecture is cosidered to be that of a high order (superior to oe) Sigma Delta Modulator (SDM) [5]. The third type of architecture that allows implemetig the fractioal-n frequecy divider relies oly o the use of a accumulator. The accumulator is clocked by the iput sigal while the output is geerated by the register Most Sigificat Bit (MSB) [6]. The frequecy cotrol word (FCW) imposes the icremet step. As show i [6], if the value chose for the FCW is ot a power of two, the time betwee two successive overflows of the register is ot costat over time. As a cosequece, the output sigal will have a period that varies betwee two values. Therefore, thisaccumulator based architecture is aturally switchig over time the frequecy divisio ratio betwee two iteger values. The averaged frequecy of the output sigal fout is defied by: f out = f i 2 FCW Where f i is the frequecy of the iput sigal, is the umber of bits used for the register desig ad FCW is the cotrol word. B. Fractioal Spurs If the divisio ratio is costat over time for the ideal fractioal frequecy divider sceario, the averagig techique used to implemet the fractioal-n frequecy divider imposes a variable frequecy divisio ratio. The period of the output is therefore oscillatig betwee two cosecutive multiples of the iput sigal s period. As a cosequece, a phase error appears whe comparig the divider s output ad the ideal divided sigal. The schematics show i Figure 3 show the evolutio of this error over time: each of the arrows represet the ed of a period of the divider s output. The phase error sigal is represeted by the evolutio over time of the ε quatity. For a ideal fractioal frequecy divider this phase error is costatly equal to zero while it evolves for a average techique based divider. From the PLL poit of view, the phase error sigal i the output sigal of the fractioal frequecy divider is detected by the PFD. As a cosequece, this phase error gives rise to a parasitic curret sigal at the output of the CP. This parasitic curret is trasformed ito a voltage parasitic sigal by the loop filter. If a periodicity characterizes the phase error waveform, the parasite voltage waveform will share this periodicity. Therefore, the spectrum of the VCO iput sigal will cotai parasitic compoets that deped o the phase error periodicity. Cosequetly, spurs appear i the PLL output as the VCO (2)

4 is modulated periodically. The magitude of the periodic waveform is large compared to radom jitter i the divider based o the average techique. As preseted i [3], the fractioal spurs geerated by the phase error are yieldig at typical values of 20 or 30 dbc. Various methods of mitigatig the ifluece of this phase error have bee proposed [4]. Three types of correctio ca be metioed: curret ijectio based fractioal compesatio, sigma delta oise shapig ad use of Iterpolatio Zero Crossig method applied to a DDS output. The curret compesatio of the phase error is realized by ijectig a curret pulse trai to the itegratig capacitor i the loop filter [7]. This curret pulse trai has the same width but opposite sig tha the curret sigal geerated by the phase error. This method is accurate but sesitive to the temperature variatio. The sigma delta oise shapig correctio is based o a spread of the eergy i the low frequecy of the phase error sigal towards higher frequecy. This oise shapig is realized by destroyig the periodicity of the phase error whe usig a high order sigma delta modulator i order to switch the divisio ratio betwee several iteger values. As a cosequece, the loop filter will be able to filter easily the frequecy compoets preset i the oise shaped phase error waveform as they are rejected at high frequecy [5]. Fially, the third method of realizig a spur compesated fractioal frequecy divisio is based o the itegratio of a phase accumulator like i direct digital sythesizer architecture. This method is developed i [6]: the phase iformatio geerated by the accumulator is coverted ito a waveform by usig a predefied table ad a digital to aalog coverter (DAC). The aalog sigal is the filtered by a low pass filter. As a cosequece, the amplitude of the phase error sigal at the output of this compoet is greatly reduced. III. DIGITAL N-FRACTIONAL FREQUENCY DIVIDER BASED ON A DIRECT SIGNAL GENERATION As metioed i the previous sectio, oe promisig solutio of realizig a high frequecy resolutio PLL relies i the use of a DDS based fractioal frequecy divider. Nevertheless, if this solutio offers a better performacecomplexity tradeoff compared with PLL usig sigma delta compesated dual modulus divider, its major drawback relies i a o-liear evolutio of the PLL output frequecy depedig o the evolutio of the FCW ijected at the iput of the DDS. As metioed i [6], whe implemetig a phase accumulator fractioal frequecy divider, the divisio ratio (DR) depeds o the umber N of the accumulator s bits ad o the FCW as follows: DR = f f out = 2 FCW Where f out is the frequecy of the output sigal ad f is the frequecy of the sigal that is drivig the accumulator. The cotrol of the divisio ratio is realized by chagig the (3) fi Accumulator Add MUX Reg msb Couter FCW 1 FCW 2 A B Figure 4. S reset Comparator S>A i i i S>B D DFF Phase accumulator based architecture FCW. Whe the PLL reaches the lock coditios, the output frequecy f PLLout of the VCO will be equal to the referece frequecy f ref multiplied by the fractioal divisio ratio: f PLLout = f ref DR = f ref (4) FCW Kowig that the referece frequecy ad the umber of bits of the accumulator are costat, it becomes obvious that the evolutio of the output frequecy of the PLL is ot liear depedig o the evolutio of the FCW. I order to tackle this liearity evolutio issue, this paper aims at proposig ad at assessig a ovel phase accumulator based fractioal frequecy divider architecture. The authors cosider that this architecture is meat to replace the sigle phase accumulator of the DDS used to realize a frequecy divider similar to that preseted i [6]. Figure 4 shows the phase accumulator based architecture that is proposed i order to obtai a liear evolutio of the DR. The mai iovatio of this proposed architecture is the fact that the FCW that cotrols the phase accumulator is o more costat over time but is switchig betwee two FCW. The cotrol of this switchig operatio is realized by implemetig a loop through a couter, a comparator ad a switch. As show i the schematic model, the clock iput of the couter is drive by the MSB of the phase accumulator. This correspods to a coutig of the phase accumulator overflow. The output of the couter is tied to the iput of the dual comparator. Depedig o the result of the comparisos betwee the value forwarded by the couter ad the A ad B values, the two outputs of the comparator will be eabled. As log as the couter output exceeds the A or B value, the comparator will eable the output correspodig to A or B, respectively. While the output correspodig to the compariso withb is used to drive the reset iput of the couter, the output that correspods to the A value compariso is used to drive the switch betwee two FCW. Based o the umber of the phase accumulator s overflows, the FCW that cotrols the step icremet of this block is chaged over time. Moreover, the global system output is geerated usig the compariso with the B value through the use of a flip-flop. 2 Q Q fout

5 Whe aalyzig the output sigal of the proposed architecture, the evaluatio of its period s mea value has to take ito accout the fact that the FCW ijected ito the phase accumulator is switched twice durig this period. As a cosequece, whe evaluatig the time betwee two cosecutive overflows of the phase accumulator, two scearios appear depedig o the value of the FCW that is ijected. As log as the compariso betwee the umber of overflows does t exceed the A value, the mea value of the time betwee two cosecutive overflows of the phase accumulator ca be evaluated as DR 1 periods of the iput sigal. Based o (3), the DR 1 is defied by: DR 1 = 2 FCW 1 (5) I a similar way, as log as the couter outputs a umber betwee the A ad B value, the mea value of the time betwee two cosecutive overflows of the phase accumulator ca be evaluated as DR 2 periods of the iput sigal, where: DR 2 = 2 FCW 2 (6) Therefore, based o (5) ad (6), the mea global frequecy divisio ratio ca be defied by: [ DR GLOBAL = 2 A 2 2 ] +(B A) FCW 1 FCW 2 For the proposed fractioal frequecy divider the tuig of the divisio ratio is cotrolled through the A iput sigal; the B, FCW 1 ad FCW 2 iput sigals are costat over time. It ca be observed that the DR evolutio becomes liear, at the opposite of the simple phase accumulator architecture. Therefore, the resolutio of the divisio ratio is defied by the relatio show i (8). This is realized by icremetig A ad by developig the differece betwee the two DR thus obtaied: [ ] DR GLOBAL = 2 +1 FCW2 FCW 1 (8) FCW 1 FCW 2 IV. RESULTS I order to validate the results of these theoretical studies, simulatios were doe usig realistic models of a classical phase accumulator, ad the proposed phase accumulatio dedicated architecture. The software used i order to realize these simulatios is the Cadece system simulatio ad aalysis [8]. Moreover, the implemetatio of the two compared structures is modeled by usig the IBM BiCMOS 0.13 µm techology. The first series of simulatios aims at validatig the liear divisio ratio evolutio regardig the cotrol value. The differet parameters characterizig the desig of the electroic compoet ad the test set-up are show i Table (7) Table I DIVISION RATIO EVOLUTION TEST PARAMETERS USED TO MODEL THE PROPOSED PHASE ACCUMULATION DEDICATED STRUCTURE Number of bits of the accumulator 9 FCW 1 50 FCW 2 51 A 64 B 1 to 64 Frequecy of the iput sigal 10 GHz Figure 5. Evolutio of the frequecy at the output of the proposed strucutre depedig o the evolutio of the cotrol value A. The freqeucy of the iput sigal is equal to 10 GHz. I. The Figure 5 shows that the evolutio of the output frequecy is liear ad that the frequecy resolutio is equal to 2 khz for the cosidered sceario. Table II DESIGN AND TEST PARAMETERS OF THE PROPOSED PHASE ACCUMULATION DEDICATED STRUCTURE THAT WAS CHOSEN TO BE COMPARED TO A EQUIVALENT SINGLE ACCUMULATOR STRUCTURE Number of bits of the accumulator 8 FCW 1 40 FCW 2 41 A 64 B 1 to 64 Frequecy of the iput sigal 10 GHz Cocerig the proposed phase accumulatio dedicated structure, the parameters used durig the modelig stage are preseted i Table II. A secod fractioal frequecy divisio structure with a sigle 20 bits accumulator was chose. This accumulator size of 20 bits is chose i such a maer that the divisio ratio performace is similar to those obtaied whe usig the proposed architecture. The value of the FCW ijected i this simple phase accumulator was chose to be equal to For both compared structures, the frequecy of the iput sigal is equal to 10 GHz. The output sigal s frequecy is of MHz ad MHz for the implemetatio sceario of the proposed architecture ad the sigle 20 bits accumulator respectively. The phase error sigals geerated whe usig each of the two phase accumulatio dedicated architectures are cosimulated by Cadece/Matlab. The time differece is evaluated betwee the risig edges of the output sigals of each of the two fractioal frequecy dividers ad referece sigals havig

6 Figure 6. CDF of the phase error correspodig to a use of the simple 20 bits phase accumulator (up) ad to the proposed phase accumulatio dedicated structure (dow). costat frequecies of MHz ad MHz respectively. The phase error is aalyzed by usig a probabilistic approach ad by a comparative study of the frequecy spectrums. The probabilistic approach is doe by evaluatig the Cumulative Distributio Fuctio (CDF) realized over a large populatio of phase error values. The CDF fuctio ca be therefore defied by: F(x) = CDF(err) = Probability(err < x) (9) where err represets the phase error variable. The graphics of Figure 6 show the CDF of phase error populatios issued of implemetatio scearios of the two aalyzed fractioal frequecy dividers. It ca be see that the time evaluated values of the phase error are liearly distributed betwee the same levels for the two implemetatio scearios. Moreover, the frequecy spectrums of the sigals correspodig to the phase error geerated by the use of each of the two frequecy dividers are preseted by the charts of Figure 7. It ca be see that the power levels of the spurs geerated by the phase error are similar for the two scearios. V. CONCLUSION This paper presets a ovel DDS-based fractioal frequecy divider with a phase accumulatio dedicated structure. Ulike a sigle accumulator architecture that is commoly implemeted i the DDS structure i order to realize the phase accumulatio operatio, the itegratio of this block allows a liear cotrol of the divisio ratio whe usig the DDS as a fractioal frequecy divider. It has bee Figure 7. Frequecy spectrums of the phase error correspodig to a use of the simple 20 bits phase accumulator (up) ad to the proposed phase accumulatio dedicated structure (dow). show that the performace of the proposed architecture is similar to that of a sigle accumulator structure but with a sigificatly reduced complexity. It ca be cocluded that the proposed architecture offers a much better performacecomplexity-power cosumptio trade-off whe compared to a sigle accumulator structure. REFERENCES [1] Skworks, Basic of Dual Fractioal-N Sythesis, Applicatio Note, [2] A. Swamiatha, K.J. Wag, I. Galto, A Wide-Badwidth 2.4 GHz ISM Bad Fractioal-N PLL With Adaptive Phase Noise Cacellatio, IEEE Iteratioal Solide-State Circuits Coferece, pp , February [3] B. Razavi, RF Microelectroics, Preice Hall PTR, [4] D. Baerjee, PLL Performace: Simulatio ad desig Lavoisier, [5] M. Kozak, I. Kale, Rigorous aalysis of delta-sigma modulators for fractioal-n PLL frequecy sythesis, IEEE Trasactios o Circuits ad Systems I, vol. 51, pp , Jui [6] Y-D Wu, C-M Lai, C-C Lee, P-C Huag, A Quatizatio Error Miimizatio Method Usig DDS-DAC for Widebad Fractioal-N Frequecy Sythesizer, IEEE Joural of Solid-State Circuits, vol. 45, pp , November [7] H. Huh et al, A CMOS dual-bad fractioal- sythesizer with referece doubler ad compesated charge pump, IEEE Iteratioal Solide-State Circuits Coferece, pp , February [8]