Reconfigurable architecture of RNS based high speed FIR filter

Transcription

1 Idia Joural of Egieerig & Materials Scieces Vol. 21, April 214, pp Recofigurable architecture of RNS based high speed FIR filter J Britto Pari* & S P Joy Vasatha Rai Departmet of Electroics Egieerig, MIT Campus, Aa Uiversity, Cheai 6 25, Idia Received 28 Jauary 213; accepted 3 Jauary 214 I this paper, a high speed recofigurable FIR filter with multiple taps usig accumulator based radix-4 multiplier is proposed. The 3-bit biary iput is coverted ito three residues usig biary to residue umber system (RNS) coverter ad the processed i three FIR sub filters costructed i direct form. The filter structure is implemeted with a multiply ad accumulate (MAC) architecture usig accumulator based radix-4 multiplier. The recofigurable structure is achieved by combiig power of two (PoT) FIR sub modules ad the coefficiets are altered durig rutime. The proposed desig is tested ad implemeted for 2-tap FIR filter. The architecture is implemeted usig VHDL ad sythesized usig Altera cycloe II EP2C35F672C6. The performace results show that the architecture achieves low power ad high speed ad variable tap flexibility. Keywords: FIR filter, Residue umber system, Higher radix multiplier, Recofigurable architecture, Power of two FIR filters are the most importat i the desig aspect of low power digital sigal processig system i multimedia ad mobile computig applicatios. Recetly with the advet of software defied radio (SDR), the research has bee focused o recofigurable realizatio of FIR filters 1-5 due to the eed of flexibility ad low complexity. The recofigurable FIR filters are geerally desiged based o programmable multiply-accumulate (MAC) architecture 4, distributed arithmetic (DA) based architecture 1,5 or programmable shift method (PSM) 3. The performaces of the desigs are aalyzed i terms of hardware complexity, low power ad high speed. The DA based architectures preseted i refs 1,5 occupy larger area. The digit based recofigurable architecture preseted i ref. 2 provides a flexible ad low-power solutio to FIR filters with a wide rage of precisio ad tap legth. The work preseted i ref. 4 show that eve though the programmable MAC architectures or dedicated architectures cosume low power with the reduced supply voltage, they require large area. The filter is iteded to perform as a digital frot-ed of SDR which requires highest samplig frequecy while desigig the chael filters. May researchers 1-5 addressed the problem of reducig the hardware complexity, low power ad icrease speed of operatio. PSM based recofigurable architecture 3 achieves low complexity ad cosiderable *Correspodig author ( brittopari@yahoo.co.i) speed due to the presece of programmable shifters, but ot useful for chael filter desig. The speed of operatio ad parallelism of digital filters is improved by the cocept of residue umber system (RNS) 6,7. I RNS based system, a set of moduli is used to covert the biary system to RNS system for efficiet implemetatio of arithmetic operatios i which the carry propagatio is miimized by breakig a operatio ito smaller operatios. Several researchers 8-1 have attempted to implemet the RNS based digital filter. I bit or 2 bit adder based implemetatios for residue coverters described i ref. 11 surmouts the moduli sets used i LUT based approach 12, o comparig the above methods, the former takes advatage of achievig improvemet i both area ad speed. The efficiet implemetatio of multiplier decides the speed ad power i FIR filters Booth s bit pair recodig algorithm allows faster multiplicatio by recodig the umber that is multiplied 16 ad is used to reduce the umber of partial products. Radix-4 based Booth multiplier is used for reducig partial products to /2 16 where is the umber of bit. Radix multipliers are commoly used i FIR filter desig because of lesser umber of computatios, lesser adders ad lesser iterative steps. Whe comparig with serial multiplier, radix multiplier occupies lesser space. I this paper, the FIR filters are implemeted usig accumulator based radix-4 multiplier whose iputs are i residue format ad coefficiets of multiplier are

2 234 INDIAN J. ENG. MATER. SCI., APRIL 214 represeted i fixed poit biary. The residue umber system used is based o three moduli set 7,17,18, 2-1, 2, These three residues are processed i the FIR sub filters which are implemeted i recofigurable maer where the umber of taps ca be varied based o select lies ad the coefficiets are give durig rutime. The performace is aalyzed i terms of area, power ad speed by varyig the umber of taps. Prelimiaries This sectio provides brief techical backgrouds o RNS ad higher radix booth multiplier that are ecessary to uderstad the rest of paper. Residue umber system Residue umber system decomposes a iteger ito smaller parts to perform parallel idepedet operatios which leads to the reductio i carry propagatio. A residue umber system 17 has a set of relative prime umbers {m 1, m 2,... m r }. Let X be a ordered set of residues {x 1, x 2 x r }, where x i = X mod m i. The iteger should satisfy the dyamic rage {, M}, where M is the product of set of moduli, m 1.m 2..m r. The choice of moduli sets ad the coversio of residue to biary umbers are importat issues for residue arithmetic 6,11,17,18. The residue umber system used i this study is based o set of moduli 7 (2-1, 2, 2 +1). The coversio of biary to RNS is obtaied by dividig 3-bit biary iput iteger ito three equal sized parts ad the performig modulo additio o those. The three residues, (2-1).(2 ).(2 +1) are -bit biary itegers except for the residue correspodig to modulo 2 +1 which is a (+1)-bit iteger. The 3-bit biary represetatio of X is k = X 1...X k = X X k2 = X X 2 The RNS represetatio X(i.e.{x 1,x 2,x 3 } is calculated through modulo operatios. p 1 = k2 + k = p1 + k1 2 1 x x 2 = k p k 2 = 2 + k x (1) 3 = p2 k The RNS to biary coverter calculates the 3-bit biary iteger X from the three output residues y 1, y 2, ad y 3 obtaied from the FIR sub-filters ad is implemeted usig ROM-less adder based coverter described i ref. 11. Z = y Y (2) where Y = A + 2. B A = (( y 1 + ( y1 y3 ).2 ) + (2 1 y3 ) + (2 1)) / 2 B = (( y + ( y1 y3 ).2 ) + y3 + 2(2 1 y 2 )) / 2 1 where y 1 ad y 3 are the least sigificat bits of y 1 ad y3 respectively. Accumulator based radix-4 multiplier Realizig high-speed multipliers helps to ehace parallelism, which helps to reduce the umber of subsequet stages. Booth s bit pair recodig algorithm is the way to icrease the speed of the operatio by reducig the umber of partial products. The origial versio of Booth algorithm (radix-2) for -bit umbers has umber of partial products. For higher computatioal speed of operatio, partial products should be reduced which could be achieved through radix-4 modified booth algorithm. This algorithm recodes the pair of three bits of the multiplier ad geerates the partial products simultaeously. Therefore, total umber of partial products gets reduced. I this paper, accumulator based radix-4 multiplier is used ad it geerates the umber of partial products as /2 for ( )-bit multiplicatio. It is a architecture to which accumulatio has bee combied with the carry look ahead adder (CLA) that accumulates partial products. Hece, we coclude that the speed of the operatio is icreased by reducig the partial product with the help of accumulator based radix-4 multiplier. The multiply ad accumulate (MAC) architecture executes the multiplicatio operatio ad accumulates the result for every clock cycle. The iputs of MAC are oe of the three residues obtaied from biary to RNS coverter ad the filter coefficiet represeted i fixed poit biary. The proposed accumulator based architecture is show i Fig. 1.

3 PARI & RANI: RECONFIGURABLE ARCHITECTURE OF RNS BASED HIGH SPEED FIR FILTER 235 RNS based Recofigurable FIR Filter Proposed RNS based FIR filter The structure of the FIR filter realized i direct form has the multipliers i the form of MAC structure ad delay blocks as the mai buildig blocks.the direct form structure of FIR filter is show i Fig. 2. The performace of the DSP algorithms etirely depeds upo multipliers i terms of critical path. Hece the speed of the operatio is icreased by usig accumulator based radix-4 multiplier ad It reduces the partial products to /2 with 3-bit pair recodig which results the partial product set of, ±1M, ±2M, where M is the multiplicad. Let X() ad Y() be the iput ad output sequeces of the FIR filter respectively. Cosider a N-tap FIR filter that ca be formulated as Y N = 1 k = ( ) h X ( k ) k (3) where h k is the k th coefficiet of the filter impulse respose. Subsequetly, the FIR filter is partitioed ito r sub filters, each correspods to oe residue x i for a give moduli set {m 1, m 2, m r }. Hece, the sub filter iput is i its residue format as give i Eq. (1) ad is deoted as, x y = X i = 1, 2,,r (4) i k m i i The output of the sub filter is calculated as i Eq. (5), N = 1 k = ( ) h x ( k ) k i (5) From Eq. (5), it ca be oted that the decomposed set of residues are processed i three sub filters ad all the three filters use the same set of filter coefficiets represeted i fixed poit biary. The RNS based FIR filter structure is show i Fig. 3. The results obtaied from FIR sub filters are coverted back ito biary. The ROM-less -bit adder based coverter is used for RNS to biary coverter, derived from ew CRT algorithm proposed i ref. 11 It improves the hardware complexity ad speed sice it ca be implemeted usig fast parallel adders ad multiplexers. Proposed recofigurable FIR architecture The filter fuctios of FIR sub filter are performed i parallel which will icrease the speed ad subsequetly the chages i the umber of taps is very difficult i hardware implemetatio. Recofigurable FIR filter is the high performace computig circuit leads to the flexibility of varyig the taps. Applyig Z-trasform o both sides of Eq. (3), we get the trasfer fuctio of FIR filter. It is described as, Y ( Z) = X ( z) H ( z) (6) H ( z) ca be writte as H ( z) = h + h z + h z + h z h z (7) Now Eq. (6) will be ( 1) Fig. 1 Block diagram of MAC architecture Fig. 2 Direct form structure of FIR filter Fig. 3 Block diagram of RNS based recofigurable FIR Filter

4 236 INDIAN J. ENG. MATER. SCI., APRIL 214 Y 1 z X z h z i ( ) = ( ) i (8) i= where h, h 1, h 2,, h -1 are the FIR filter coefficiets ad the z -i represets the delay elemets. This trasfer fuctio ca be decomposed ito PoT sub modules i which the umber of coefficiets is the icreasig powers of 2 as i Eq. (9). Now the trasfer fuctio i Eq. (7) ca be rewritte as H( z) = h + z ( h + h z ) + z ( h + h z + h z + h z ) z ( h + h z + ( 1/2) 1 1/2 + 1/2 ( 1/2)... + h 1z ) Let us take the sub modules as, (9) H(2 ) = h, H(2 1 ) = h 1 +h 2 z -1, H(2 2 ) = h 3 +h 4 z - 1 +h 5 z -2 + h 6 z -3 ad so o. Hece for N=2 m+1-1 tap where m=,1,2,3 H( z) H(2 ) H(2 ) z H(2 ) z H(2 ) z = m 4 15 m (2 1) H(2 ) z H(2 ) z (1) It ca be cocluded from Eqs (9) ad (1), for ay N-tap filter, the sub modules ca be combied with appropriate delay elemets. For example, for 1-tap filter, umber of filter coefficiets is oe ad hece H ( 2 ) = h. For a 2- tap filter, umber of filter coefficiets is 2, whose trasfer fuctio is described 1 1 as H (2 ) = h + h z. A 3-tap filter ca be implemeted by combiig H (2 ) ad H (2 ) sub modules as give i Eq. (11). The coefficiets of 3-tap filter are give durig rutime through coefficiet memory. filter structure is show i Fig. 4. As show i Fig. 4, oe of the 2 m outputs is obtaied at the ecoder output Y based o the m select lies. The proposed N-tap FIR filter structure provides flexibility where idividual sub modules will make ay structure that satisfies the applicatio specific eeds. Durig rutime the filter coefficiets are chaged from the coefficiet memory ad the correspodig coefficiets are idetified with the same select lies of ecoder. Results ad Discussio The proposed RNS based recofigurable FIR filter has bee simulated usig VHDL ad tested with Altera FPGA device Cycloe II EP2C35F672C6. The simulatio waveform of recofigurable FIR filter is show i Fig. 5. The proposed architecture of recofigurable FIR filter is implemeted i direct form. Recofiguratio is tested for the umber of taps from 1 to 2 with the select sigal of 5-bits. The select lies will eable the ecessary sub modules to obtai the output of ay oe of the recofigurable filter with the varyig tap of 1 to 32. For example, selects the H(2 ) module to obtai 1-tap filter output, 1 selects 2-tap, 1 selects 3-tap ad similarly the biary combiatio of five select bits correspod to 1 to 2-tap selects the respective output. I Fig. 5, it is clearly show that the outputs of 5-tap ad 18-tap filter are obtaied by varyig two differet 1 1 H ( z) = z H (2 ) + H (2 ) (11) Similarly, 5-tap filter is obtaied by combiatio of 2 H (2 ) ad H (2 ) sub modules with delay elemet z -1. It has described i Eq. (12). 1 2 H ( z) = z H (2 ) + H (2 ) (12) Hece it ca be oted that the recofiguratio of ay tap FIR filter ca be implemeted by eablig the correspodig sub modules with additio of suitable delay elemets. The proposed recofigurable FIR Fig. 4 Recofigurable 2 m tap FIR sub-filter

5 PARI & RANI: RECONFIGURABLE ARCHITECTURE OF RNS BASED HIGH SPEED FIR FILTER 237 Fig. 5 Simulatio waveform of recofigurable FIR filter for 5-tap ad 18-tap Table 1 RNS FIR filter without recofiguratio No. of taps Logic elemets Delay (s) Power (mw) select lies (sel). Figure 6 shows the RTL schematic of recofigurable FIR filter with 2-tap. It displays a schematic view of the desig etlist after sythesis is performed by the QuartusII software. To implemet the proposed RNS based recofigurable FIR filter, 6512 logic elemets are used. The RNS FIR filter has bee implemeted usig Altera Quartus Cycloe II EP2C35F672C6. The performace results of RNS FIR filter is give i Table 1. From Table 1 we observed that the icrease i the umber of taps provides liearly favorable reductio i area ad power. This is possible because of resource sharig amog idetical logical elemets, which are preset i higher tap FIR structure ad RNS coversio overhead remais uchaged irrespective of the umber of filter taps. This has bee show i Figs 7 ad 8. This shows that this filter is suitable where fixed tap FIR filters are used. But SDR applicatios requires FIR filter of varyig umber of taps to support differet applicatios i wireless techology. This lead to the developmet of recofigurable based RNS FIR filter. For a 4-tap recofigurable FIR filter, H(z) is split ito H(2 ), H(2 1 ) ad H(2 2 ) accordig to Eq. (1) as a sub module for variable tap implemetatio from tap 1 to 4. Similarly 8-tap ad 16-tap recofigurable FIR filter is implemeted. Eve though orecofiguratio structure gives better result i terms of area ad delay, the recofiguratio structure achieves flexibility i varyig the taps with oly a margial icrease i area ad delay. The performace results of 2-tap RNS FIR filter architecture are give i Table 2. While aalyzig with accumulator based radix-4 multiplier, it is observed that area gets reduced, because the same resources are used for all the additio processes i the accumulatio ad speed is icreased by the reductio i the partial products. The speed of the operatio also improved due to parallel operatio by decomposig the iteger ito three residues usig RNS structure. The results are also aalyzed with Xilix virtex II 2v 3ff FPGA for compariso purposes. Table 3 depicts the sythesis results of the 2 tap recofigurable RNS architecture whe implemeted o Xilix virtex-ii2v 3ff FPGA. The speed performace of the 2 tap filter implemeted usig RNS architecture is 2 times better tha the 2 tap filter implemeted usig PSM method proposed i ref. 1 The proposed recofigurable RNS architecture has achieved high speed due to the parallelism of RNS structure. Durig iitializatio, the coefficiets are stored i the memory. Size of the ecoder is directly proportioal to the umber of taps beig cofigured. The advatage of the proposed method is the powers of two sub modules beig programmed to

6 238 INDIAN J. ENG. MATER. SCI., APRIL 214 Fig. 6 RTL schematic of recofigurable 2-tap FIR filter structure

7 PARI & RANI: RECONFIGURABLE ARCHITECTURE OF RNS BASED HIGH SPEED FIR FILTER 239 Table 3 Compariso of proposed accumulator based radix-4 filter with existig architecture with Xilix VirtexII 2v3ff1152-4) Parameters PSM 1 Proposed without recofiguratio Proposed with recofiguratio No. of taps No. of iput bits Data arrival time (s) Samplig frequecy (MHz) implemet ay tap filter, thereby reducig the total area. The recofiguratio time is depedet o the sub modules ad it is miimized based o how the modules are beig orgaized. Fig. 7 Taps versus delay Coclusios A high speed recofigurable RNS based FIR filter usig accumulator based radix-4 multiplier has bee proposed ad ca be used for implemetig N-tap filters. The N-tap filter is implemeted oly by combiig PoT (2 m ) sub modules thereby reducig the hardware resources ad the power cosumed i recofigurable RNS filter is mw with the maximum frequecy of MHz. All the PoT modules have bee implemeted i parallel ad hece it improves the speed of operatio. The sigificat power reductio ad high speed is achieved also by usig RNS umber system ad the accumulator based radix multiplier. The proposed recofigurable architecture is flexible ad programmable with o extra cotrol sigals, sice it allows recofiguratio by coectig PoT sub modules with ecessary delay elemets ad the correspodig output is selected through ecoder ad hece it is well-suited for VLSI implemetatio. Fig. 8 Taps versus power Table 2 Performace results of 2-tap accumulator based radix-4 FIR filter with Altera Cycloe II EP 2C35F672C6 parameters with recofiguratio without recofiguratio No. of iput bits No. of logic elemets Delay (s) Frequecy (MHz) Power (mw) Refereces 1 Aderso David V & Özalevli Erha, IEEE Tras Circuits Syst-I, 55(2) (28). 2 Kua Hug & Tzi Dar, IEEE Tras Circuits Syst, 53 (26). 3 Mahesh R & Viod A P, IEEE Tras Comput Aided Des Itegrated Circuits Syst, 29 (Feb 21) 4 Solla T & Vaiio O, Compariso of programmable FIR filter architectures for low power, i Proc. 28th Europea Solid-State Circuits Cof, Sept 22, pp Meher Pramod Kumar, IEEE Tras Circuits Syst, 57(3) (21). 6 Wag Y, IEEE Tras Circuits Syst II, (2) Viakota B & Bapeswara Rao V V, IEEE Tras Circuits Syst, 41(12) (1994). 8 Shabhag Naresh R & Sifred Raymod E, IEEE J Solid State Circuits, 26(5) (1991).

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