Design of modulo 2 n -1 multiplier Based on Radix-8 Booth Algorithm using Residue Number System

Transcription

1 Desig of modulo 2-1 multiplier Based o Radix-8 Booth Algorithm usig Residue Number System K.RAMAMOHAN REDDY M.Tech Studet, Dept. of ECE Vaagdevi Istitute of Techology & Sciece,Proddatur, Kadapa (Dt.), A.P. V.RAMESH Assistat Professor, Dept. of ECE Vagdevi Istitute of Techology &Sciece,Proddatur,Kadapa(Dt) A.P. C.Md.ASLAM HOD, Dept. of ECE Vagdevi Istitute of Techology & Sciece,Proddatur,Kadapa(Dt) A.P. ABSTRACT Modular arithmetic operatios (iversio, multiplicatio ad expoetiatio) are used i several cryptography applicatios. A special moduli set of forms {2-1, 2, 2 +1} are preferred over the geeric moduli due to the ease of hardware implemetatio of modulo arithmetic fuctios as well as system-level iter-modulo operatios, such as RNS-to-biary coversio ad sig detectios. With this precept, a family of radix-8 Booth ecoded modulo 2-1 multipliers, with delay adaptable to the RNS multiplier delay, is proposed. The first-ever family of low-area ad low-power radix-8 Booth ecoded modulo 2-1 multiplier whose delay ca be tued to match the RNS delay closely has bee proposed i this paper. A CSA tree with edaroud-carry additio for accumulatio of redudat partial products ad a Sklasky parallel-prefix structure has also bee implemeted. Idex Terms Public Key Cryptographic (PKC),Booth algorithm, modulo arithmetic, multiplier, residue umber system (RNS) 1. INTRODUCTION RIVEST, Shamir, ad Adlema (RSA) ad elliptic curve cryptography (ECC) are two of the most well established ad widely used public key cryptographic (PKC) algorithms. The ecryptio ad decryptio of these PKC algorithms are performed by repeated modulo multiplicatios [1] [3]. These multiplicatios differ from those ecoutered i sigal processig ad geeral computig applicatios i their sheer operad size. Key sizes i the rage of 512~1024 bits ad 160~512 bits are typical i RSA ad ECC, respectively [4] [7]. Hece, the log carry propagatio of large iteger multiplicatio is the bottleeck i hardware implemetatio of PKC. The residue umber system (RNS) has emerged as a promisig alterative umber represetatio for the desig of faster ad low power multipliers owig to its merit to distribute a log iteger multiplicatio ito several shorter ad idepedet modulo multiplicatios Modular Multiplicatio i Public Key Cryptosystems Modulo 2 +1, 2, 2-1 additio ad multiplicatio are the crucial operatios i the IDEA algorithm ad also modulo 2 +1 arithmetic operatios are used i Fermat umber trasform computatio. Moduli choices of the forms {2 +1, 2, 2-1} have received sigificat attetio because they offer very efficiet circuits whe cosiderig the area * time 2 product ad efficiet coverters from ad to the biary system. Therefore, desigig efficiet modulo 2-1 multipliers is a iterestig issue. Modulo 2-1 multiplicatio is used extesively i Residue Number System (RNS) based Digital Sigal Processig (DSP) ad cryptography uits. 1

2 begiig at positio x -1 ad cotiuig to the MSB with oe bit overlappig betwee adjacet triplets. If the umber of bits i X (excludig x -1 ) is odd, the sig (MSB) is exteded oe positio to esure that the last triplet cotais 3 bits. I every step we will get a siged digit that will multiply the multiplicad to geerate a partial product eterig the Wallace reductio tree. The meaig of each triplet ca be see i table I: Table I: Radix-4 ecodig Figure 1: Modulo (2-1) multiplier architecture The modulo 2 1 multiplicatio of two umbers -bit each follows 3 steps: productio of 2 partial products modulo 2 1 reductio of this 2 partial products 2 1 ito two umbers of bits additio of these two umbers modulo 2 1 with the precedig adder. 2. LITERAUTRE SURVEY The radix-8 Booth ecodig reduces the umber of partial products to which is more aggressive tha the radix-4 Booth ecodig. However, i the radix-8 Booth ecoded modulo 2-1 multiplicatio, ot all modulo-reduced partial products ca be geerated usig the bitwise circular-leftshift operatio ad bitwise iversio. Particularly, the hard multiple +3X 2-1 is to be geerated by a -bit ed-aroud-carry additio of X ad 2X. Radix-4 ad radix-8 multiplicatio Recodig of biary umbers was first hited at by Booth four decades ago. MacSorley proposed a modificatio of Booth s algorithm a decade after. The modified Booth s algorithm (radix-4 recodig) starts by appedig a zero to the right of x 0 (multiplier LSB). Triplets are take This recodig scheme applied to a parallel multiplier halves the umber of partial products so the multiplicatio time ad the hardware requiremets decrease. This gai is possible at the expese of somewhat more complex operatios i every step. However, that the required multiples of Y {0, Y, 2Y} are available by merely shiftig Y to the left. Although the algorithms ad operatios specified above seem rather arbitrary at the first sight, they are based o meaigful umber systems. If oe focuses o what modificatios are beig doe to X, the oe may arrive at a differet represetatio for the 2s-complemet umber X as show i figure 2: Figure 2: Siged-digit represetatio where digits Di are oe of -2, -1, 0, 1, 2 foud i the table of figure 1, based o the value of triplets i the form (xi+2 xi+1 xi). Here we have a siged digit represetatio of 2

3 X i radix-4. Siged-digit umber represetatio allows redudacy to exist. Thaks to this we ca make a parallel recodificatio that is, all triplets are recoded at the same time, ad the value of each triplet is idepedet from the adjacet triplets. Radix-8 recodig applies the same algorithm as radix-4, but ow we take quartets of bits istead of triplets. Each quartet is codified as a siged-digit usig the table II: TableII:Radix-8 recodig I fact, oly a 21-bit adder is eeded to geerate the bit positios from z1 to z21. Bits z0 ad z22 are directly kow because z0=y0 ad z22=y20 (sig bit of the 2s-complemet umber; 3Y ad Y have the same sig). If i the memory from where we take the umbers just two additioal bits are stored together with each value of the set of umbers, we ca decompose the previous add i three shorter adds that ca be doe i parallel. I this way, the delay is the same of a 7-bit adder: Here we have a odd multiple of the multiplicad, 3Y, which is ot immediately available. To geerate it we eed to perform this previous add: 2Y+Y=3Y. But we are desigig a multiplier for specific purpose ad thereby the multiplicad belogs to a previously kow set of umbers which are stored i a memory chip. We have tried to take advatage of this fact, to ease the bottleeck of the radix-8 architecture, that is, the geeratio of 3Y. I this maer we try to attai a better overall multiplicatio time, or at least comparable to the time we could obtai usig radix-4 architecture (with the additioal advatage of usig a less umber of trasistors). To geerate 3Y with 21-bit words we oly have to add 2Y+Y, that is, to add the umber with the same umber shifted oe positio to the left, gettig i this way a ew 23-bit word, as show i figure 3: Figure 3: 21-bit previous add Bits which are goig to be stored are the two itermediate carry sigals c8 ad c15. Before each word of the set of umbers is stored i the memory, the value of its itermediate carries has to be obtaied ad stored beside it. I this way, they are immediately available whe it is required to perform the previous add to get the multiple 3Y of oe of the umbers that belogs to the set. The radix-4 Booth ecodig techique is most prevalet as all required modulo reduced partial products ca be geerated by circular-left-shift operatio ad bit-wise complemetatio, thereby miimizig the hardware complexity. The reductio i the umber of partial products is determied by the radix of the Booth ecodig techique employed. Reductio of partial products by more tha half is possible with higher radix Booth ecodig. Similar to the radix-4 algorithm, the radix-8 Booth ecodig algorithm ca be cosidered as a digit set coversio of four cosecutive multiplier bits y3i-1,y3i,y3i+1,y3i+2, yi Є {0, 1}from Y, to d i, d i Є [ 4, 4], for i = 0, 1, Ν/3. 3

4 The digit set coversio is give by (1) where y -1, y, y +1 ad y +2 are zero. For the radix-8 Booth ecoded modulo 2-1 multiplier, the required modulo-reduced partial products are show i Table III. From Table 3, the ecessary modulo-reduced partial products except ±3X ca be geerated by circular-left-shift operat-io ad/or bitwise compleme-tatio of the multiplicad, X. The geeratio of±3x requires a large wordlegth adder which icreases the critical path delay of the multiplier sigificatly. TABLE III: MODULO-REDUCED PARTIAL PRODUCTS FOR RADIX-8 BOOTH ENCODING results also cofirm that the proposed method helps pathologists distiguish exact lesio sizes ad regios 3. PROPOSED RADIX-8 BOOTH ENCODED MODULO 2-1 MULTIPLIER DESIGN To esure that the radix-8 Booth ecoded modulo 2-1multiplier does ot costitute the system critical path of a high- DR moduli set based RNS multiplier, the carry propagatio legth i the hard multiple geeratio should ot exceed bits. To this ed, the carry propagatio through the HAs i Fig. 1 ca be elimiated by makig the ed-aroud-carry bit c 7 a partial product bit to be accumulated i the CSA tree. This techique reduces the carry propagatio legth to bits by represetig the hard multiple as a sum ad a redudat ed-aroud-carry bit pair. The resultat [/3] +1 ed-aroud-carry bits i the partial product matrix may lead to a margial icrease i the CSA tree depth ad cosequetly, may aggravate the delay of the CSA tree. I which case, it is ot sufficiet to reduce the carry propagatio legth to merely bits usig the above techique. Sice the absolute differece betwee the ocritical modulo 2-1 multiplier delay ad the system critical path delay depeds o the degree of imbalace i the moduli wordlegth of a RNS, the delays caot be equalized by arbitrarily fixig the carry propagatio legth to bits. Istead, we propose to accomplish the adaptive delay equalizatio by represetig the hard multiple i a partially-redudat form [48]. A. Geeratio of Partially-Redudat Hard Multiple Let X 2-1 ad 2X 2-1 be added by a group of M (=/k) k-bit RCAs such that there is o carry propagatio betwee the adders. Fig. 2 shows this additio for =8 ad k=4,where the sum ad carry-out bits j from the RCA block j are represeted as S i j adc i for i [0,k-1] ad j [0,M- 1],respectively. I Fig. 2, the carry-out of RCA 0,C 0 3, is ot propagated to the carry iput of RCA 1 but preserved as oe of the partial product bits to be accumulated i the CSA tree. The biary weight of the carry-out C 1 3 of RCA 1 has,however, exceeded the maximum rage of the modulus ad has to be modulo reduced before it ca be accumulated by the CSA tree. 1 By Property 2, the biary weight of C 3 ca be reduced from 2 8 to 2 0. Thus, C 1 3 is iserted at the least sigificat bit (lsb)positio i Fig It should be stressed that the carry-out C 3 is a partial carry propagated through oly k most sigificat FAs ad hece, is differet from the ed-aroud-carry bit i the modulo 2-1 additio of X ad 2X, i.e., c 7 of Fig. 5.From Fig. 6, the partially-redudat form of +3X 2-1 is give by the partial-sum ad partial-carry pair(s,c) 4

5 Fig. 5. Geeratio of partially-redudat +3X 2-1 usig k-bit RCAs Fig. 7. Geeratio of partially-redudat simple multiples. Fig.6. Geeratio of partially-redudat B+3X 2-1 where Fig. 8. Modulo-reduced partial products ad CC for X Y Sice modulo 2-1 egatio is equivalet to bitwise complemetatio by Property 1, the egative hard multiple i a partiallyredudat form, -3X 2-1 =(, ), is computed as follows: To avoid havig may log strigs of oes i, a appropriate bias B,, is added to the hard multiple such that both C ad are sparse [48]. The value of B is chose as The addeds for the computatio of the biased hard multiple, B+3X 2-1 i a partially-redudat form are X 2-1, 2X 2-1ad B or equivaletly S,C ad B. Sice is chose to be a biary word that has logic oes at bit positios 2 kj ad logic zeros at other bit positios, B+3X 2-1 ca be geerated by simple XNOR ad OR operatios o the bits of S ad C at bit positios 2 kj. Fig. 6 illustrates how these bits i the sum ad the carry outputs of RCA 0 ad RCA 1 are modified. I geeral B+3X 2-1, is give by the partial-sum ad partial-carry pair (BS,BC)such that where 5

6 ad For j=0, 1 M-1. Let partially-redudat form. Fig. 7 shows the biased simple multiples, B+0 2-1, B+X 2-1, B+2X 2-1, ad B+4X 2-1 represeted i a partially-redudat form for =8. From Fig. 10, it ca be see that the geeratio of these biased multiples ivolves oly shift ad selective complemetatio of the multiplicad bits without additioal hardware overhead. C. Radix-8 Booth Ecoded Modulo 2-1 Multiplicatio with Partially-Redudat Partial Products The i-th partial product of a radix-8 Booth ecoded modulo 2-1 multiplier is give by PP i= 2 3i d i X 2-1 (12) To iclude the bias B ecessary for partiallyredudat represetatio of PP i, (12) is modified to PP i = 2 3i (B+d i X) 2-1 (13) Usig Property 3, the modulo 2-1 multiplicatio by 2 3i i (13) is efficietly implemeted as bitwise circular-left-shift of the biased multiple, (B+d i X). For =8 ad k=4,fig. 8 illustrates the partial product 8 matrix of X Y) 2-1 with Fig. 9. Modulo-reduced partial product geeratio. It ca be easily verified that the sum of (BS, BC) ad() modulo 2-1 is 2B 2-1. Therefore,()represets the partially-redudat form of B-3X 2-1. B. Geeratio of Partially-Redudat Simple Multiples The proposed techique represets the hard multiple i a biased partiallyredudat form. Sice the occurreces of the hard multiple caot be predicted at desig time, all multiples must be uiformly represeted. Similar to the hard multiple, all other Booth ecoded multiples listed i Table I must also be biased ad geerated i a Fig.10. (a) Bit-slice of Booth Ecoder (BE). (b) Bit-slice of Booth Selector (BS). (/3+1) partial products i partiallyredudat represetatio.each PP i cosists of a -bit vector, pp i7--- pp i1 pp i0 ad a vector of /k=2 redudat carry bits, q i1 ad q i0. Sice q i0 ad q i1 are the carry-out bits of the RCAs, they are displaced by k-bit positios for a give PP i. The bits, q ij is displaced circularly to the left of q( i-1) j by 3 bits, i.e., q 20 ad q 21 are displaced circularly to the left of q 10 ad q 11 by 3 bits, respectively ad q 10 ad q 11 are i tur displaced to the left of q 00 ad q 01 by 3 bits, respectively. The last partial product i 6

7 Fig. 8 is the Compesatio Costat (CC) for the bias itroduced i the partially-redudat represetatio. The geeratio of the moduloreduced partial products, PP 0, PP 1 ad PP 2, i a partially-redudat represetatio usig Booth Ecoder (BE) ad Booth Selector (BS) blocks are illustrated i Fig. 8. The BE block produces a siged oe-hot ecoded digit from adjacet overlappig multiplier bits as illustrated i Fig. 10(a). The siged oe-hot ecoded digit is the used to select the correct multiple to geerate PP i. A bit-slice of the radix-8 BS for the partial product bit, PP ij is show i Fig. 10(b). Fig. 12.Multiplier Simulatio Results Fig 13.Radix-4 Sythesis Report(Gate Cout) Fig.14.Radix-8 Sythesis Report (Gate Cout) Fig. 11. Modulo-reduced partial product accumulatio. As the bit positios of q ij do ot overlap, as show i Fig. 8, they ca be merged ito a sigle partial product for accumu-latio.the merged partial products, PP i ad the costat CC are Accumulated usig a CSA tree with ed-aroud-carry additio at each CSA level ad a fial two-operad modulo 2-1 adder as show i Fig RESULTS 5. CONCLUSION A family of low-area ad low-power modulo 2-1 multipliers with variable delay to achieve delay balace amogst idividual modulo chaels i a high-dr RNS multiplier was proposed. The delay of the proposed multiplier is cotrolled by the wordlegth of the small parallel RCAs that are used to compute the requisite hard multiple of the radix-8 Booth ecoded multiplicatio i a partially-redudat form. From sythesis results costraied by the critical chael delay of the RNS, it was show that the proposed multiplier simultaeously reduces the area as well as the power dissipatio of the radix-4 Booth ecoded multiplier for 28, which is the useful dyamic rage of RNS multiplicatio to meet the miimum key-size requiremets of ECC ad RSA algorithms. REFERENCES 7

8 [1] R. Rivest, A. Shamir, ad L.Adle-ma, A method for obtaiig digital sigatures ad public key cryptosy-stems, Commu. ACM, vol. 21, o.2, pp , Feb [2] V. Miller, Use of elliptic curves i cryptography, i Proc. Advacesi Cryptology-CRYPTO 85, Lecture Notes i Computer Sciece, 1986,vol. 218, pp [3] N. Koblitz, Elliptic curve cryptosystems, Mathemat. of Comput., vol.48, o. 177, pp , Ja [4] Natioal Istitute of Stadards ad Techology. Available: csrc.ist.gov/publicatios/pubssps.html [5] A. K. Lestra ad E. R. Verheul, Selectig cryptographic key sizes, J. Cryptol., vol. 14, o. 4, pp , Aug [6] C. McIvor, M. McLooe, ad J. V. McCay, Modified Motgomery modular multiplicatio ad RSA expoetiatio techiques, IEE Proc. Comput. ad Dig. Techiq., vol. 151, o. 6, pp , Nov [7] C. McIvor,M.McLooe, ad J. V. McCay, Hardware elliptic curve cryptographic processors over, IEEE Tras. Circuits Syst. I,Reg. Papers, vol. 53, o. 9, pp , Sep [8] D. M. Schiiaakis, A. P. Fouraris, H. E. Michail, A. P. Kakaroutas,ad T. Stouraitis, A RNS implemetatio of a Elliptic curve poit multiplier, IEEE Tras. Circuits Syst. I, Reg. Papers, vol. 56, o.6, pp , Ju [9] J. C. Bajard ad L. Imbert, A full RNS implemetatio of RSA, IEEE Tras. Comput. Brief Cotributios, vol. 53, o. 6, pp , Ju [10] H. Nozaki, M. Motoyama, A. Shimbo, ad S. Kawamura, Implemetatio of RSA algorithm based o RNS Motgomery multiplicatio, i Proc. Workshop o Cryptographic Hardware ad Embedded Systems,Paris, Frace, May 2001, pp [11] T. Stouraitis ad V. Paliouras, Cosiderig the alteratives i lowpower desig, IEEE Circuits Devices Mag., vol. 17, o. 4, pp ,Jul [12] S. Potarelli, G. C. Cardarilli, M. Re, ad A. Salsao, Totally fault tolerat RNS based FIR filters, i Proc. 14th IEEE It. O-Lie Testig Symp., Rhodes, Greece, Jul. 2008, pp [13] Mr.K.Ramamoha Reddy,is curretly doig post graduatio i Vagdevi istitute of Tech & Sciece,Proddatur,Kadapa(Dt) A.P with the specializatio of VLSI [14] Mr.V.Ramesh,is a Assistat Professor i ECE dept. at Vagdevi istitute of Tech&Sciece,Proddatur.He obtaied his B.Tech degree i ECE from MeRITS,JNTUA,Udayagiri i 2007,M.Tech degree i Electroic Istrumetatio ad Commuicatio Systems from S.V.Uiversity,Tirupati i 2009.He has 3years of teachig experiece ad his area of iterest icludes Electroics istrumetatio ad Ateas.He has published 4 papers i referred iteratioal jourals ad also 2papers at atioal level cofereces. [14] Mr.C.Mahammed Aslam is the HOD,Dept.of ECE at Vagdevi istitute of Tech&Sciece,Proddatur.He obtaied his B.Tech degree i ECE from Dr.Babasaheb Ambedkar Maratwada Uiversity,Auragabad i 1997,M.Tech degree i Digital Electroics ad Computer Sciece from JNTU,Hyderabad i 2007.He ahs 10 years of teachig experiece.he registered his Ph.D from JNTU,Aatapur i digital Image Processig.His area of iterest is Microprocessor ad EDC circuits. He has published 2 papers i iteratioal jourals. 8