A New Implementation for a 2 n 1 Modular Adder Through Carbon Nanotube Field Effect Transistors

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1 April 2015, Volume 2, Number 2 (pp ) Joural of Computig ad Security A New Implemetatio for a 2 1 Modular Adder Through Carbo Naotube Field Effect Trasistors Seyyed Ashka Ebrahimi a, Mohammad Reza ReshadiNezhad a, a Faculty of Computer Egieerig, Uiversity of Isfaha, Isfaha, Ira. A R T I C L E I N F O. Article history: Received: 06 Jauary 2015 Revised: 17 November 2015 Accepted: 22 February 2016 Published Olie: 08 May 2016 Keywords: RNS, Modulo Adder, Naoelectroic, CNFET A B S T R A C T The modulo 2 ± 1 are the most applied modulo set i residue umber system (RNS). The modulo adder 2 1 is very importat due to its variety of applicatios i DSP, like additio/subtractio ad multiplicatio i digital filters, cryptography, fault detectio, fault correctio ad checksum. I this article, by applyig carbo aotube trasistors based o Ed Aroud Carry structure, a modulo adder 2 1 is implemeted. The problems are aalyzed ad i order to fix them ad improve the orbital parameters, a ew desig is proposed. Through this desig, the problem for two represetatios of zero are solved, ad by takig advatage of a structure for fast calculatio of carry, the orbital parameters are upgraded. The circuits are simulated by Hspice simulatio tools ad their performaces are verified. Simulatio results cofirm the superior performace of this proposed desig compared to the EAC (Ed Aroud Carry) structure. c 2015 JComSec. All rights reserved. 1 Itroductio Additio is the most fudametal arithmetic operatio [1] that ca be used to implemet more complex arithmetic circuits such as multiplicatio, divisio ad expoetiatio [2, 3]. I these calculatios, additio ad subtractio circuits are widely used. Operatios of additio due to their extesive applicatio i a logical computig uit, Floatig Poit calculatios uit, ad address calculatio to access the cache ad mai memory are vital compoets of the processors [4]. Sice the first appearace of digital systems ad arithmetic circuits, extesive studies have bee coducted o this issue. By improvig the performace of additio operatios, orbital parameters of the derived circuits ca be upgraded [5]. Hece, the implemetatio of this Correspodig author. addresses: ebrahimi@eg.ui.ac.ir (S. A. Ebrahimi), m.reshadiezhad@eg.ui.ac.ir (M. R. ReshadiNezhad) ISSN: c 2015 JComSec. All rights reserved. arithmetic operatio i a fast ad low-power maer is a ecessity to make a fast ad low-power chip [6]. Thus icreasig performace of the additio operatios is oe of the major challeges i the desig ad implemetatio of the arithmetic circuits. The mai problem i implemetig fast additio circuits is the carry propagatio [1, 6]. The most sigificat bits are depedet o the least sigificat bits whe calculatio of additio takes place, thus causig a sigificat icrease i circuit delay [7]. The solutios that are proposed to solve this problem, are: alterative umeral systems such as Redudat ad Residue umber system [1, 8] ad structures for fast carry propagatio like Carry Look Ahead ad parallel Prefix adders [9]. The Residue Number System (RNS) has a differet mathematical approach to the umeral system. By Covertig arithmetic o large umbers to a collectio of smaller umbers, RNS represetatio is itroduced [1]. The arithmetic operatios o these small umbers are coducted i parallel [10 12]. With respect to delay, it ca be assumed that i each processig oly

2 zigzag 130 A New Implemetatio for a 2 1 Modular Adder Through... S. A. Ebrahimi ad M. R. ReshadiNezhad 2= 0 1= 2 Ch (1,2)= (6,2) o a2 1= 0 Figure 1. No-Radiated Graphite Sheet oe umber is processed. I RNS, with coversio of a large umber (The umber of bits) ito several small umbers, a large computatioal operatio is divided ito several small parallel computatios, where, each of these small computatios are carried out separately ad idepedetly [13, 14]. This feature shriks the carry propagatio chai which is useful i may applicatios to ehace computig speed. MOSFET trasistors ad CMOS techology have take the largest share of digital circuits implemetatio. So far may systems ad tools such as computers, mobile phoes, digital cameras, ad other electroic tools are made by usig them. Major advaces i this techology are due to the smaller trasistor sizig. Scalig trasistors will give the opportuity to icrease the umber of trasistors iside a chip ad thus ehace the fuctioality of the chip, poited out by Moore s low [15]. Despite may advaces made i physics ad chemistry fields, cotiuatio of this tred is faced with great challeges, that is, makig the size of the trasistors smaller, has its ow serious costraits like quatum effects ad chip temperature rise. Assessig the alterative tools ad techologies is ievitable. Oe of these tools is the Carbo Naotube Field-effect Trasistors (CNFETs) a achievemet by aotechology with a great chace to replace the covetioal silico techology [16 18]. I these trasistors, the semicoductor carbo aotubes are used as the trasmissio chael [19]. I the ext two sectios of this article Carbo Naotube Trasistor ad Residue Number System are briefly reviewed. After RNS, the modulo adder 2 1 is examied. I the fourth sectio, the implemetatio of EAC structure is discussed ad after examiig its advatages ad disadvatages, the proposed structure usig carbo aotube trasistors is itroduced. This sectio icludes the detailed descriptio, the simulatio results ad the advatages of the proposed structure. At the ed a summery ad coclusio will be preseted. The circuits are aalyzed by Hspice simulatio tools ad the Staford library model [20] for CNFETs. 2 Carbo Naotube Trasistors Carbo aotube (CNT) is istalled as a trasmissio chael i CNFETs. This chael is placed betwee Source ad Drai, ear the Gate [15]. Carbo aotubes ca be cosidered as a sheet of graphite (Graphite is a allotrope of carbo) wrapped aroud itself formig a hollow cylider. The umber of carbo atom layers that form a hollow cylider, ca be more tha oe. Torsio directio of carbo atoms i the legth of the atom is displayed with a vector amed Chirality (ch). For checkig this vector, two uit vectors of a 1 ad a 2 are used ad the factor of each vector is idicated by 1 ad 2. 1 ad 2 are two positive itegers as show i Figure 1 [21]. Accordig to the values of 1 ad 2, three differet cofiguratios for aotube ca be shaped. If oe of these two vectors is zero, the aotube will be Zigzag, If 1 = 2, the aotube is Armchair, otherwise, the aotubes will be Chiral. I term of electrical coductivity, if 1 = 2 or if 1 2 = 3i (i is a iteger), the aotube is coductive (metallic), otherwise, it is semicoductor. Electrical resistace of aotube is very low; the

3 April 2015, Volume 2, Number 2 (pp ) 131 Figure 2. a) Frot View ad b) Top View the of a CNFET electros are facig with little resistace, ad ca move alog the aotube easily. This amout of resistace is much lower tha that of the prevalet coductors [21]. If the aotube is composed of a sigle layer of carbo atom, it is amed SWCNT ad if it is composed of multi layers, it is amed MWCNT [22]. Sigle-walled semicoductor carbo aotubes (SWCNT) are used i makig CNFET trasistors. Like MOSFET, CN- FETs have the types of P ad. The advatage of CNFET is that the size ad mobility of P ad are idetical [23]. Sice the chaels of CNFET are of a lower resistace tha that of the MOSFETs, the chip temperature ad the power cosumptio ca be reduced. The size of the ch vector is equal to the circumferece of the base of carbo aotubes obtaied by Equatio (1) [24]. The diameter of the aotube which is a importat parameter i circuit desig is obtaied by dividig ch by π. The threshold voltage of CNFET has iverse relatio with its aotube diameter. To calculate the threshold voltage of each CNT trasistor with a diameter of D Equatio (2) [24] is applied; so by chagig the diameter of the aotube, trasistors with differet threshold voltages ca be produced, see CNFET, i Figure 2. V th E bg 2e = 3 3 av π ed CNT D CNT (m) (1) D CNT = a π (2) I Equatios (1) ad (2), e is the electroic charge, E bg is the Badgap, a is the space of carbo atoms at approximately 0.249, D CNT is the diameter of the aotube, ad V π is approximately Residue Number System To covert the commo umbers to Residue Number System they are broke ito several smaller umbers based o a set amed Moduli set. The moduli set is the basis of RNS. Each Moduli Set cosists of a series of compoets amed moduli. The umber of the modules ad the way they are chose have essetial roles i system efficiecy [8]. Selectig Moduli Set will have a direct effect o the orbital parameters ad is determiat of the overall system efficiecy [14]. The members of a moduli set are prime umbers with respect to each other. I geeral, the Moduli Set of M with m i compoets (moduli) is preseted as follows: M = {m 1, m 2,, m } (3) The Dyamic Rage (DR) is the set of umbers covered by RNS. I other words, DR determies which domai from the covetioal umber system is selected by the moduli set as residue. This value is obtaied by multiplyig the modules together [13]. DR = m 1 m 2 m (4) Each umber, i [0, DR) rage, has a uique represetatio i RNS. To calculate the correspodig residue umber x i modulo M, the proper umber is divided by M ad the remaider of the divisio will be the represetatio of x for modulo M. This sequece is preseted by the followig two equatios: X RNS (x 1, x 2,..., x ) (5) x i = X mod m i = X mi = 0 x i m i (6) I a RNS system, the task of covertig the covetioal umber ito a residue umber is through a uit amed Forward Coverter, which coverts the biary umber to a residue umber [8]. The modulo represetatio of umber x i modulo M is expressed by Equatio (7): x if 0 x m 1 x m = x + km if x < 0 (7) x km if x m where, k is a positive iteger, M is the desired modulo ad x is ay arbitrary umber. Required arith-

4 132 A New Implemetatio for a 2 1 Modular Adder Through... S. A. Ebrahimi ad M. R. ReshadiNezhad Modulo m1 B A Operads Forward Coversio Modulo m2 Reverse Coversio Results Carry -bit CPA Ci Modulo Chaels Modulo m S Figure 3. RNS System Figure 4. Modulo 2 1 Adder With EAC Method metic operatios are performed o each oe of the residues o idividual basis. The circuits resposible for this calculatio are amed the Modular Chaels. Oe of the most importat modular chaels is the Modular Adders. These adders are oe of the most fudametal ad primary elemets used i the residue umber system [8]. The extesios of these elemets are applied i all differet parts of the RNS: forward coverter, arithmetic uits, ad reverse coverter. Implemetig the RNS circuits without modulo adders is practically impossible. The arithmetic operatios for each of the umbers (residues) are ru i parallel with other residues ad by circuits desiged to perform i a particular modulo. After coductig calculatios through Modulo Chaels, the results of each modulo will be trasmitted to a Reverse Coverter [14] where they are coverted ito a weighted umber (covetioal umber) [8]. If Y = {y 1, y 2,, y } ad X = {x 1, x 2,, x } the the additio/subtractio of the residues x ad y with respect to Moduli Set M = {m 1, m 2,, m }, is equal to: {x 1 ± y 1, x 2 ± y 2,, x ± y } (8) X±Y = x 1 ± y 1 m1, x 2 ± y 2 m2,, x ± y m (9) The overall structure of a RNS system is illustrated i Figure The Modular Adder for Modulo 2 1 The modulo adder 2 1 which is equivalet to Oe s complemet adder, i additio to beig used i RNS, has additioal applicatios, like additio/subtractio ad modulo multiplicatio i digital filters [25], Cryptography [26], error detectio ad correctio [27], ad i calculatio of checksum i fast etworks [28]. Various structures are preseted for the modulo adder 2 1, [29 34] each with specific characteristics. With referece to Equatio (7), additio i this modulo ca be implemeted based o Equatio (10). A + B 2 1 = { A + B (2 1) if A + B 2 1 A + B if A + B < 2 1 (10) Sice A + B (2 1) = (A + B + 1) 2, the Equatio (10) ca be writte as: { A + B 2 1 = A + B if A + B 2 1 A + B if A + B < 2 1 (11) Sice A ad B are i modulo 2 1 ad their largest value is ( }{{} ) 1, the the coditio A+B 2 1 will hold true, whe A ad B are the complemets of each other ad/or carry-out is 1, Equatio (11) ca be rewritte as: { A + B 2 1 = A + B if A + B 2 A + B otherwise = A + B + Carry 2 (12) Equatio (12) is a geeral method kow as Ed Aroud Carry (EAC). I this method, the carry-out must be added to the sum of two umbers. Therefore the fial aswer is foud i two steps: 1) the carry-out is calculated through a CPA, where, the value of carryi to CPA is cosidered zero ad 2) the carry-out obtaied i the previous step is applied to the CPA as the carry-i ad the addig operatio is repeated (Figure 4). It should be oted that the adder is -bit, hece the calculated sum will be -bit (the secod carry of additio is igored). The delay ad hardware cost of circuit i Figure 4 is: { Delay = 2(D F A ) (13) Area = (A F A ) I Equatio (13), the D F A is the full-adder delay ad the A F A is the full-adder hardware cost.

5 April 2015, Volume 2, Number 2 (pp ) 133 Carry A B FA S A2 B2 FA S2 A1 B1 FA S1 A0 B0 Ci Figure 5. Schematic Diagram of the RCA Figure 6. The Covetioal Structure of FA 4 The Proposed 2 1 Adder 4.1 Implemetatio of EAC Structure EAC structure for implemetig VLSI requires a - bit CPA; therefore, a Ripple Carry Adder (RCA) is applied. A schematic diagram of the RCA is show i Figure 5. RCAs are the easiest ad the least costly form of the CPAs. The dotted lie i Figure 5 shows the critical path of the delay. RCA is made of cascade coectio of several FAs. For this purpose, the covetioal structure of FA (Figure 6) which is implemeted by carbo aotube trasistors, has bee used. The most importat advatage of EAC is its simplicity i desig ad implemetatio. Furthermore, it is possible that ay kid of CPA be applied i a EAC s structure ad the expasio of be easily doe due to its simple structure as well. 4.2 Proposed Desig EAC scheme has three drawbacks: 1) too much delay, because the ultimate aswer is prepared i two separate cycles of carry-out calculatio ad calculatio of the sum with the carry-i from the previous step 2) bidig of the carry-out to carry-i cause a coditioal loop ad 3) this type of desig leads to two FA S0 represetatio of zero. As a example, cosider = 4 ad A = (1000) 2 = (8) 10 ad B = (0111) 2 = (7) 10 with moduli set 15 (2 4 1 = 15). Sice the carryout of these two umbers (assumig that the carry-i is 0 ) is zero, the sum output of EAC, will be S = (1111) 2 = (15) 10. Sice the sum is equal to moduli, the it is expected, accordig to Equatio (7), that the value of the moduli be subtracted from S ad therefore, the fial result would be (0000) 2. This example idicates that i EAC structure there are two represetatios of zero: the egative zero (111 1) 2 ad the positive zero (000 0) 2. This ca be trivial i some applicatios, like reverse coverter desig i a residue umber system. As log as these circuits are used i RNS, their correctio ito sigle represetatio of zero is ot required [34]. But i most applicatios of this arithmetic circuit, the two zero represetatio ca be problematic. I geeral, adders that have oly oe represetatio of zero, have additioal hardware overhead. By assumig that the two sigle bit umbers a ad b are obtaied as follows: p = a b, g = ab (14) where, P =propagate, that is, the carry propagatio ad g=geerate, that is, the carry geeratio ad represets the XOR. The carry-out of these two siglebit umbers ca be obtaied through the followig equatio: Carry = g + pc i (15) For two four-bit umbers Equatio (15) ca be writte as follows: Carry = g 3 +p 3 g 2 +p 3 p 2 g 1 +p 3 p 2 p 1 g 0 +p 3 p 2 p 1 p 0 C i (16) I modulo adder desiged through EAC method, the carry-i is always cosidered as beig 0 ; thus Equatio (16) ca be compacted as follows: Carry = g 3 + p 3 g 2 + p 3 p 2 g 1 + p 3 p 2 p 1 g 0 (17) By implemetig the modulo adder 2 1 through EAC method, the issue of two represetatios of zero is existet whe both of the iputs are complemetary of each other. I Equatio (18), if x = 1 the issue of two represetatios of zero is obvious ad (000 0) is displayed as (111 1). x = (a 1 b 1 ) (a 2 b 2 )... (a b ) (18) I this proposed method, Equatio (17) is applied to calculate the carry-out ad Equatio (18) is applied to determie the coditio(s) that causes two represetatios of zero. For hardware implemetatio these two equatios are merged. Schematic diagram of this proposed scheme is show i Figure 7. This proposed desig cosists of two separate uits: a) the carry computatio (Carry Geerator: CG) ad b) the -bit Carry Propagatio Adder (CPA). The CG cotais

6 Carry 134 A New Implemetatio for a 2 1 Modular Adder Through... S. A. Ebrahimi ad M. R. ReshadiNezhad A B A B Carry Geerator Mode -bit CPA S Figure 7. Schematic Diagram of the Proposed Adder Figure 8. Trasistor Level Structure of Carry Geerator Uit the detectig circuit of two represetatios of zero coditio(s) ad the calculatio of carry-out. These two circuits are combied with each other. The dotted lie i Figure 7 shows the critical path of delay whe this proposed method is implemeted. I additio to CPA a separate circuit is applied to calculate the carry, thus the problem of loop i EAC structure is removed. As observed i Figure 7, the carry is calculated through the CG uit subject to double represetatio of zero coditio(s). This circuit is desiged to calculate the carry i a rapid maer. The output of the CG uit eters the -bit CPA uit i such a maer that it is cosidered as the CPA carry-i. As metioed earlier, i order to costruct the CG uit, both of the Equatio (17) ad (18) have bee implemeted. The field effect trasistor structure of this uit is show i Figure 8. Here, all the trasistors are iitialized simultaeously accordig to the give iputs, where the ON ad OFF status of each trasistor is determied. This proposed method ca perform i both the sigle ad double zero formats through usig a sigal amed Mode. This sigal is applied to covert modulo adder from sigle represetatio of zero to double represetatios of zero ad vice versa. Sice oe of the trasistors i this structure aticipate carry, therefore carry-out is calculated fast. The hardware overhead imposed o the circuit for removig the problem of two represetatios of zero cosists of two trasistors. If the value of Mode is 1, the adder will operate as two represetatios of zero ad if the iitial value of the Mode is 0, the additio operatio is performed i such a way that there would be oly oe represetatio of zero. The imposed overhead for cotrollig the sigle or two represetatios of zero is illustrated i Figure 8. For sectio B of the circuit (-bit CPA), the itroduced RCA is applied [35]. A advatage of this proposal is the existece of sigals p i, p i which are applied i cotrollig the multiplexers; cosequetly, for producig (a i b i ) ad (a i b i )i CG uit, there is o eed for extra trasistors sice the geerated sigals i CPA uit ca be used. Aother advatage of this proposed method i [35], is applyig the bridge desig style i implemetig miority-ot gate. This style ehaces the efficiecy of the circuit where the delay ad power cosumptio are reduced [36]. The multiplexers of the adder circuit i [35] are desiged through the Pass gate techology; therefore, the outputs are Full-swig. The last FA i CPA structure

7 April 2015, Volume 2, Number 2 (pp ) 135 Figure 9. Trasistor Level Structure of CPA Uit Out 4-bit CG 4-bit CG 4-bit CG 4-bit CG Mode Figure 10. Schematic Diagram of CG Uit for > 4 (uit B) is without carry calculatio sectio. Sice the sum of the two -bit umbers i modulo 2 1 are of bits. The trasistor level structure of CPA uit for =4 is show i Figure 9. As observed i Figure 8, the CG circuit is implemeted by applyig Pass-gate techology. Thus, by a icrease i the umber of bits (), the Fa-out of the circuit icreases, leadig to a icrease i delay. To remove this problem the CG uit is divided ito blocks of four bits, i a sese that the output of the (k 1) th block is coected to the iput Mode of the k th block after passig through a iverter Figure 10. The circuits preseted i this article are implemeted through carbo aotube field effect trasistors. Hspice simulatio tool ad the Model i [20] are used for circuits simulatio. This model is fully described i the two articles [37, 38]. The umber of aotube per trasistor is3, the value of pitch = 30e 9m ad gate legth = 32e 9m. To calculate the delay i the circuit, all chages i iput ad output are evaluated ad the maximum delay is reported as the circuit delay. Parameter PDP is obtaied by multiplyig the average power cosumptio i the worst-case delay. I order to obtai the values of delay ad power cosumptio, ad aalyze the iput ad output pulses ad also verify the circuit performace, the Comsmos Scope software is used. The diameters of the aotube used i this proposed method with the correspodig Chirality ad threshold voltage are tabulated i Table 1. The simulatio results at 27 C, voltage of 1.2 V ad o capacitive load for = {16, 8, 4} are tabulated Table 1. Diameter, Chirality ad Threshold Voltage of CN- FETs used i this article Type Diameter Chirality Threshold P-Type (19,0) N-Type (19,0) Table 2. Simulatio Results of the Proposed Adder Desig Delay (ps) Power (uw ) PDP (e 17) Tr. Cout 4 EAC Based-o [39] Based-o [40] Proposed EAC Based-o [39] Based-o [40] Proposed EAC Based-o [39] Based-o [40] Proposed i Table 2. The iput patters applied to the circuits for = 4 are show i Figure 11. The improvemet of the orbital parameters like delay, power cosumptio, PDP ad the umber of trasistors, with respect to are illustrated i Fig-

8 136 A New Implemetatio for a 2 1 Modular Adder Through... S. A. Ebrahimi ad M. R. ReshadiNezhad Figure 11. Iputs Patter for = 4 ure 12, (a), (b), (c) ad (d) respectively. The results cofirm the improved performace of this proposed architecture compared to that of the EAC structure ad desigs based o articles [39, 40]. through the bridge desig style ad the Pass-gate. Simulatio results cofirm the improved performace of this proposed method whe compared to that of the EAC structure. 5 Coclusio As far as the authors of this article kow the modulo adder 2 1 is beig implemeted through Carbo aotube trasistors for the first time. At first, a adder based o EAC structure is implemeted ad evaluated, ad the a desig to remove the problems of EAC structure ad ehace its efficiecy is preseted. I this itroduced method, the CG structure with the ability to compute the carry-out i a fast maer is applied, which i tur upgrades the delay parameter i a proper maer. Here the problem of two represetatios of zero is solved, i such a way that the itroduced circuit is able to calculate oe or two represetatios of zero. The structure is desiged i a maer that it does ot impose a big hardware overhead. Power cosumptio is sigificatly reduced Refereces [1] Parhami Behrooz. Computer arithmetic: Algorithms ad hardware desigs. Oxford Uiversity Press, 19: , [2] Neil HE Weste ad Kamra Eshraghia. Priciples of CMOS VLSI desig, volume 188. Addiso- Wesley New York, [3] Reto Zimmerma ad Wolfgag Fichter. Lowpower logic styles: Cmos versus pass-trasistor logic. Solid-State Circuits, IEEE Joural of, 32 (7): , [4] Yigtao Jiag, Abdulkarim Al-Sheraidah, Yuke Wag, Edwi Sha, ad Ji-Gyu Chug. A ovel multiplexer-based low-power full adder. Circuits ad Systems II: Express Briefs, IEEE Trasactios o, 51(7): , 2004.

9 April 2015, Volume 2, Number 2 (pp ) 137 Figure 12. The Improvemet of the Orbital Parameters Agaist Variatio i [5] Keiva Navi, Horialsadat Hossei Sajedi, Reza Faghih Mirzaee, Mohammad Hossei Moaiyeri, Ali Jalali, ad Omid Kavehei. High-speed full adder based o miority fuctio ad bridge style for aoscale. Itegratio, the VLSI joural, 44(3): , [6] Israel Kore. Computer arithmetic algorithms. Uiversities Press, [7] Mi Lu. Arithmetic ad logic i computer systems, volume 169. Joh Wiley & Sos, [8] Amos Omodi ad Bejami Premkumar. Residue umber systems. World Scietific, [9] Reto Zimmerma. Computer Arithmetic: Priciples, Architectures, ad VLSI Desig. Lecture otes, Itegrated Systems Laboratory, ETH Zürich, URL ch/~zimmi/publicatios/comp_arith_otes. ps.gz. [10] MR Reshadiezhad ad FK Samai. A ovel low complexity combiatioal rs multiplier usig parallel prefix adder. Iteratioal Joural of Computer Sciece Issues (IJCSI), 10(2), [11] MA Bayoumi ad P Sriivasa. Parallel arithmetic: from algebra to architecture. I Circuits ad Systems, 1990., IEEE Iteratioal Symposium o, pages IEEE, [12] T Stouraitis ad V Paliouras. Cosiderig the alteratives i low-power desig. Circuits ad Devices Magazie, IEEE, 17(4):22 29, [13] Keiva Navi, Amir Sabbagh Molahosseii, ad Mohammad Esmaeildoust. How to teach residue umber system to computer scietists ad egieers. Educatio, IEEE Trasactios o, 54(1): , [14] Amir Sabbagh Molahosseii, Keiva Navi, Chitra Dadkhah, Omid Kavehei, ad Somayeh Timarchi. Efficiet reverse coverter desigs for the ew 4- moduli sets ad based o ew crts. Circuits ad Systems I: Regular Papers, IEEE Trasactios o, 57(4): , [15] Mary Eshaghia-Wiler. Bio-ispired ad aoscale itegrated computig, volume 1. Joh Wiley & Sos, [16] Mohammad Reza Reshadiezhad, Mohammad Hossei Moaiyeri, ad NAVI Kaiva. A eergy-efficiet full adder cell usig cfet techology. IEICE trasactios o electroics, 95(4): , [17] Arijit Raychowdhury ad Kaushik Roy. Carboaotube-based voltage-mode multiple-valued logic desig. Naotechology, IEEE Trasactios o, 4(2): , [18] Sheg Li, Yog-Bi Kim, ad Fabrizio Lombardi. Ctfet-based desig of terary logic gates ad arithmetic circuits. Naotechology, IEEE Trasactios o, 10(2): , 2011.

10 138 A New Implemetatio for a 2 1 Modular Adder Through... S. A. Ebrahimi ad M. R. ReshadiNezhad [19] Sader J Tas, Alwi RM Verschuere, ad Cees Dekker. Room-temperature trasistor based o a sigle carbo aotube. Nature, 393(6680): 49 52, [20] Uiversity Staford. Staford CNFET Model, URL staford-cfet-model. [21] Jie Deg. Device modelig ad circuit performace evaluatio for aoscale devices: silico techology beyod 45 m ode ad carbo aotube field effect trasistors. PhD thesis, Staford Uiversity, [22] Peima Keshavarzia ad Keiva Navi. Uiversal terary logic circuit desig through carbo aotube techology. Iteratioal Joural of Naotechology, 6(10-11): , [23] Geuho Cho, Yog-Bi Kim, Floriaa Lombardi, ad MiSu Choi. Performace evaluatio of cfet-based logic gates. I Istrumetatio ad Measuremet Techology Coferece, I2MTC 09. IEEE, pages IEEE, [24] Mohammad Hossei Moaiyeri, Keiva Navi, ad Omid Hashemipour. Desig ad evaluatio of cfet-based quaterary circuits. Circuits, Systems, ad Sigal Processig, 31(5): , [25] W Keeth Jekis ad Bejami J Leo. The use of residue umber systems i the desig of fiite impulse respose digital filters. Circuits ad Systems, IEEE Trasactios o, 24(4): , [26] Xuejia Lai ad James L. Massey. Advaces i Cryptology EUROCRYPT 90: Workshop o the Theory ad Applicatio of Cryptographic Techiques Aarhus, Demark, May 21 24, 1990 Proceedigs, chapter A Proposal for a New Block Ecryptio Stadard, pages Spriger Berli Heidelberg, Berli, Heidelberg, ISBN doi: / URL / _35. [27] Stephe Sik-Sag Yau ad Yu-Cheg Liu. Error correctio i redudat residue umber systems. Computers, IEEE Trasactios o, 100(1):5 11, [28] Fred Halsall ad Data Liks. Computer etworks ad ope systems. Addiso-Wesley Publishers, pages , [29] Ju Che ad James E Stie. Parallel prefix lig structures for modulo 2ˆ -1 additio. I Applicatio-specific Systems, Architectures ad Processors, ASAP th IEEE Iteratioal Coferece o, pages IEEE, [30] Lampros Kalampoukas, Dimitris Nikolos, Costas Efstathiou, Haridimos T. Vergos, ad Joh Kalamatiaos. High-Speed Parallel-Prefix Modulo 2-1 Adders. IEEE Tras. Computers, 49(7): , doi: / URL http: //dx.doi.org/ / [31] R. A. Patel, M. Beaissa, ad S. Boussakta. Efficiet ew approach for modulo 2/sup /-1 additio i rs. IEE Proceedigs - Computers ad Digital Techiques, 153(6): , Nov ISSN doi: /ip-cdt: [32] Somayeh Timarchi, Mahmood Fazlali, ad Sori D Cotofaa. A uified additio structure for moduli set {2-1, 2, 2 + 1} based o a ovel rs represetatio. I Computer Desig (ICCD), 2010 IEEE Iteratioal Coferece o, pages IEEE, [33] Shaoqiag Bi, Warre J Gross, Wei Wag, Asim Al-Khalili, ad MNS Swamy. A area-reduced scheme for modulo 2-1 additio/subtractio. I System-o-Chip for Real-Time Applicatios, Proceedigs. Fifth Iteratioal Workshop o, pages IEEE, [34] Rakesh A Patel, Mohammed Beaissa, ad Said Boussakta. Fast parallel-prefix architectures for modulo 2-1 additio with a sigle represetatio of zero. Computers, IEEE Trasactios o, 56 (11): , [35] Seyyed Ashka Ebrahimi ad Peima Keshavarzia. Fast low-power full-adders based o bridge style miority fuctio ad multiplexer for aoscale. Iteratioal Joural of Electroics, 100(6): , [36] Keiva Navi, Mohammad Hossei Moaiyeri, Reza Faghih Mirzaee, Omid Hashemipour, ad Babak Mazloom Nezhad. Two ew low-power full adders based o majority-ot gates. Microelectroics Joural, 40(1): , [37] J. Deg ad H. S. P. Wog. A compact spice model for carbo-aotube field-effect trasistors icludig oidealities ad its applicatio #x2014;part i: Model of the itrisic chael regio. IEEE Trasactios o Electro Devices, 54 (12): , Dec ISSN doi: /TED [38] J. Deg ad H. S. P. Wog. A compact spice model for carbo-aotube field-effect trasistors icludig oidealities ad its applicatio #x2014;part ii: Full device model ad circuit performace bechmarkig. IEEE Trasactios o Electro Devices, 54(12): , Dec ISSN doi: /TED [39] Aliakbar Rezaei, Mehdi Masoudi, Fazel Sharifi, ad Keiva Navi. A ovel high speed full adder cell based o carbo aotube fet (cfet). Iteratioal Joural of Emergig Scieces, 4(2): 64 75, [40] Shima Mehrabi, Reza Faghih Mirzaee, Mohammad Hossei Moaiyeri, Keiva Navi, ad Omid

11 April 2015, Volume 2, Number 2 (pp ) 139 Hashemipour. Cfet-based desig of eergyefficiet symmetric three-iput xor ad full adder circuits. Arabia Joural for Sciece ad Egieerig, 38(12): , Seyyed Ashka Ebrahimi is Ph.D. studet i computer architecture i the School of computer egieerig, Uiversity of Isfaha, Isfaha, Ira. His research iterests maily focus o Naoelectroics with emphasis o CNFET ad QCA, VLSI implemetatio of MVL circuits, Mixed-mode circuits ad Nao- FPGA. Mohammad Reza Reshadiezhad was bor i Isfaha, Ira, i He received his B.S. ad M.S. degree from the Electrical Egieerig Departmet of Uiversity of Wiscosi, Milwaukee, USA i 1982 ad 1985, respectively. He has bee i positio of lecturer as faculty of computer egieerig i Uiversity of Isfaha sice He also received the Ph.D. degree i computer architecture from Shahid Beheshti Uiversity, Tehra, Ira, i He is curretly Assistat Professor i Faculty of Computer Egieerig of Uiversity of Isfaha. His research iterests are Digital Arithmetic, Naotechology cocerig CNFET ad QCA, VLSI Implemetatio of circuits, Logic Circuits Desig, ad Cryptography.