Modulo 2 n +1 Arithmetic Units with Embedded Diminished-to-Normal Conversion

Transcription

1 th Euromicro Coferece o Digital System Desig Modulo 2 +1 Arithmetic Uits with Embedded Dimiished-to-Normal Coversio Evagelos Vassalos, Dimitris Bakalis Electroics Laboratory, Dept. of Physics Uiversity of Patras Patras, Greece vassalos@upatras.gr, bakalis@physics.upatras.gr Haridimos T. Vergos Dept. of Computer Egieerig & Iformatics Uiversity of Patras Patras, Greece vergos@ceid.upatras.gr Abstract The dimiished-oe represetatio has bee proposed for RNS-based systems with moduli of the 2 +1 forms as a ecodig that is more efficiet tha the ormal represetatio i the arithmetic processig uits. However, its use ecessitates a two-step reverse coversio, i which a dimiished-to-ormal coversio is first performed before the fial residue-to-biary coversio resultig i performace loss. I this paper we itroduce efficiet modulo 2 +1 adders, subtractors ad multipliers that accept dimiished-oe operads at their iputs ad derive ormal operads at their outputs, that is, we embed the dimiished-to-ormal coversio withi the arithmetic processig. Experimetal results show that the proposed oe-step approach is more efficiet i terms of delay. Keywords-residue umber system; modulo arithmetic; modulo 2 +1 arithmetic uits; dimiished-oe represetatio; ormal represetatio I. INTRODUCTION The Residue Number System (RNS) [1] [2] is a alterative umber represetatio commoly adopted for speedig up computatios i digital sigal processig [3-6], cryptography [7-9] ad telecommuicatio applicatios [10-12]. A o-positioal RNS is defied by a set of L moduli, suppose {m 1,, m L } that are pair-wise relatively prime. A iteger A has a uique represetatio i the RNS, give by the set {a 1,, a L } of residues, where a i A is m i the modulo m i residue of A. A operatio over a RNS is defied as (z 1,, z L ) (a 1,, a L ) (b 1,, b L ), where z a b. The computatio of z i oly depeds o a i, b i, i i i m i ad m i implyig that all z i s ca be computed i parallel, each i a separate arithmetic uit ofte called a chael. Sice all chaels operate i parallel ad each deals with arrow residues istead of wide umbers, sigificat speedup over the usual biary represetatio may be achieved. A RNS-based system cosists of three mai blocks. At first, all biary iputs are coverted to their correspodig sets of residues with biary-to-residue (forward) coverters, accordig to the specified moduli set. The, the arithmetic processig is performed i parallel i each modulo chael. The arithmetic computatios that are usually performed cosist of several additios, subtractios ad multiplicatios, which ca be efficietly realized i modulo arithmetic. Fially, the RNS represetatio of the results is coverted back to biary with residue-to-biary (reverse) coverters. RNS chaels with moduli of the 2, 2-1 or 2 +1 forms have received sigificat attetio. This is because the arithmetic circuits that have bee proposed for the 2 ±1 moduli are almost as efficiet as the biary oes for the same operad widths [13-27]. Furthermore, efficiet coverters exist betwee the residue ad the biary represetatio for various moduli sets [26] [28-38]. I such moduli sets, the 2 +1 chael has to deal with operads oe bit wider tha the correspodig 2-1 or 2 chaels, leadig to a performace bottleeck. To avoid this, ad give that i the case of a zero operad the result ca be derived straightforwardly, [39] itroduced the dimiished-oe represetatio. I the dimiished-oe represetatio each operad is represeted decreased by oe compared to its ormal represetatio ad hece oly bits are required for its represetatio. A separate bit is utilized to idicate a zero operad or result. The dimiished-oe represetatio has the advatage that it allows to better equalize the delay of the modulo 2 +1 chael with the delay of the remaiig chaels of the moduli set. Durig the last years, efficiet architectures for dimiished-oe modulo 2 +1 additio, subtractio ad multiplicatio have bee preseted i the ope literature, that are more efficiet tha those for the ormal represetatio [14] [15] [19] [21] [22] [24] [26] [27]. To this ed, the dimiished-oe represetatio is preferred for modulo chaels of the 2 +1 forms i RNS-based systems. Biary-to-residue coversio for the dimiished-oe represetatio is equally efficiet as the coversio for the ormal represetatio [26] [40]. However, almost all residue-to-biary coverters that have bee reported util ow assume a ormal represetatio for the residues of the 2 +1 forms. The oly exceptio is the reverse coverter that is reported i [26] for the {2-1, 2 +k, 2 +1} moduli set. Hece, if the dimiished-oe represetatio is adopted i order to speed up the arithmetic processig, the a two-step approach is required i the reverse coversio; a dimiishedto-ormal coverter has to be used before the fial residueto-biary coversio. The dimiished-to-ormal coverter ca be based o a biary icremeter [15] but its logarithmic delay [41] ca cacel all the speedup achieved i the arithmetic processig. I this paper we explore the embeddig of the dimiished-to-ormal coversio withi the arithmetic /11 $ IEEE DOI /DSD

2 processig uits. To this ed, we preset ovel architectures for desigig modulo 2 +1 arithmetic uits (adders, subtractors ad multipliers), that assume the dimiished-oe represetatio at the iputs ad the ormal represetatio at the outputs. The proposed architectures are based o those of the correspodig dimiished-oe arithmetic uits. They ca be efficietly utilized i RNS-based systems with moduli of the 2 +1 forms where the arithmetic processig is based o the dimiished-oe represetatio while the reverse coversio assumes the ormal represetatio. The remaiig of the paper is orgaized as follows. The ext two sectios preset ovel modulo 2 +1 adders ad subtractors while sectio IV presets ovel modulo 2 +1 multipliers. Sectio V presets experimetal results ad comparisos. The last sectio cocludes the paper. II. MODULO 2 +1 ADDITION Suppose that A ad B deote two modulo 2 +1 operads, that is, 0 A, B < 2. Let (a z, A ) ad (b z, B ) deote the dimiished-oe represetatios of A ad B, respectively, where a z ad b z are the zero idicatio bits of the two operads that are equal to 1 oly whe A or B is equal to 0 ad A a -1 a 0 ad B b -1 b 0 are -bit wide vectors which are defied accordig to the followig equatios [15]: A 1, A 0 A, B 1, B 0 B 0, A 0 0, B 0 Give the dimiished-oe represetatios of A ad B, the sum of the two operads take modulo 2 +1 i ormal represetatio, accordig to the values of A ad B, is summarized i Table I. Let us cosider the followig cases: A 0 ad B 0 (equivaletly a z 0 ad b z 0) It holds that A B A + B + 2 A + B It is well kow that a dimiished-oe adder produces at the output the least sigificat bits of the sum of its iput operads take modulo 2 +1 icreased by oe [21]. The most sigificat bit of the abovemetioed arithmetic operatio ca be derived by checkig whether the two iput operads are bitwise complemetary [40]. Moreover, a - bit Carry Save Adder (CSA) with Iverted Ed-Aroud Carry (IEAC), composed of Full Adders (FAs) ad a TABLE I. MODULO 2 +1 ADDITION a z b z A + B A + B A + B A + B A B + 2 iverter, produces at its output, i carry ad sum format, the sum of its iput operads take modulo 2 +1 icreased by oe. Hece, the first icremet i the modulo additio operatio ( A + B +1 ) ca be realized by a CSA with 2 IEAC with iputs A, B ad 0, while the secod ca be realized by a ehaced dimiished-oe adder [40], as show i Fig. 1 (r r 0 deote the +1 bits of the result). Obviously, the FAs of the CSA are simplified to Half Adders (HAs). A 0 ad B 0 or A 0 ad B 0 I this case, oly a sigle icremet is required. We ca still use the architecture of Fig. 1 as log as we ihibit the icremet performed at the IEAC CSA. Whe A or B or both are equal to 0, the carry output of the most sigificat HA of the CSA is equal to 0 ad thus its iverted value that is equal to 1 is drive to the least sigificat bit positio (Y 0 i Fig. 1) i the ehaced dimiished-oe adder. We ca chage this bit value to 0 by a 2-iput NOR gate drive by the carry out of the HA ad by a z b z ( deotes a logic OR). The output of the NOR gate is drive to the least sigificat bit iput of the ehaced dimiished-oe adder. A 0 ad B 0 (equivaletly a z 1 ad b z 1) I this case, both icremets must be ihibited. The modificatio described for the previous case ihibits the icremet performed by the IEAC CSA i this case too, while the secod ihibitio ca be performed by ivertig the half-sum sigal (h 0 ) at the least sigificat bit positio withi the ehaced dimiished-oe adder, whe a z b z 1. The complete architecture for the proposed modulo 2 +1 adder is show i Fig. 2. Note that oe of the modificatios made to the architecture of Fig. 1, i order to cover the last two cases, reside o the critical path of the circuit. b 1 a 1 b 2 a 2 HA HA HA HA X 1 Y 1 X 2 Y 2 Y 2 X 1 Y 1 X 0 Y 0 b 1 a 1 Ehaced Dimiished oe Adder r r 1 r 2 r 2 r 1 r 0 Figure 1. Modulo 2 +1 additio. b 0 a 0 469

3 b z a z b 1 a 1 b 2 a 2 HA HA HA HA s b z a z X 1Y 1 X 2Y 2 Y 2 X 1 Y 1 X 0 Y 0 b 1 a 1 b 0 a 0 b z a z X 0Y 0 TABLE II. MODULO 2 +1 SUBTRACTION A z B z A B A + B A B +1 2 A + B A 2 + B 2 Modified Ehaced Dimiished oe Adder b z b 1 b 2 b 1 b 0 h 0 r r 1 r 2 r 2 r 1 r 0 a 1 a 2 a 1 a 0 Figure 2. Proposed modulo 2 +1 adder architecture. a z III. MODULO 2 +1 SUBTRACTION Let us ow cosider the modulo 2 +1 subtractio. Give the dimiished-oe represetatios of two modulo 2 +1 operads A ad B, (a z, A ) ad (b z, B ), the differece of A ad B take modulo 2 +1 i ormal represetatio, A B, ca be derived as follows. We distiguish the 2 +1 followig four cases: c b z a z HA HA HA HA s s X 1 Y 1 X 2 Y 2 Y 2 X 1 Y 1 X 0 Y 0 Modified Ehaced Dimiished oe Adder b z a z X 0 Y 0 A 0 ad B 0 It holds that A B where 2 ( A ) ( B A + (2 ) 1) B A B 2 A + B B deotes the bitwise complemet of B. A 0 ad B 0 Sice B 0, B +B ad therefore it holds that A B ( A ) B ) A + B A 0 ad B 0 It holds that A B 2 A ( B A + (2 ) 2 1) B A B A + B A 0 ad B 0 Sice B 0, B +B ad therefore it holds that A B A B A B r r 1 r 2 r 2 r 1 r 0 Figure 3. Proposed modulo 2 +1 subtractor architecture. All four above cases are summarized i Table II. It is obvious that the modulo 2 +1 subtractio ca be realized by the modulo 2 +1 adder preseted i the previous sectio, provided that we complemet the bits of B whe B 0 ad leave the bits of B ualtered whe B 0. The proposed architecture for modulo 2 +1 subtractio is show i Fig. 3. IV. MODULO 2 +1 MULTIPLICATION Almost all architectures that have bee preseted, durig the last few years, for modulo 2 +1 multiplicatio [24-27], cosist of three stages. At first, all partial products (PPs) ad correctio terms (CTs) are formed. These are actually -bit wide vectors. The, a multi-operad adder (usually a adder tree) composed of CSAs with IEAC is used to compress all PPs ad CTs to two -bit wide vectors that are fially added with a fast two-operad modulo 2 +1 adder i order to produce the result of the multiplicatio. Cosider two modulo 2 +1 operads A ad B ad their correspodig dimiished-oe represetatios (a z, A ) ad (b z, B ). Assume at first that both A ad B are ot equal to 0. A dimiished-oe modulo 2 +1 multiplier will produce at its h 0 470

4 output the dimiished-oe represetatio of the product of A ad B, that is, A B 1 ( A ) ( B ) A B + A + B 2 I order to get the product i ormal represetatio we have to compute A B 2 ( A ) ( B A B ) + A 2 + B 2 Hece, we ca utilize ay dimiished-oe architecture for modulo 2 +1 multiplicatio ad we ca get the ormal represetatio of the result by: (a) icreasig by oe the CT of the dimiished-oe multiplier (which i several cases is costat), ad (b) replacig the fast dimiished-oe twooperad adder that produces the -bit wide result with a ehaced dimiished-oe two-operad adder as the oe preseted i [40] that produces all +1 bits of the result. The proposed architecture is show i Fig. 4. We also have to take ito accout the cases where A or B (or both) are equal to 0. I these cases, A 0 0 or B 0 0 (or both), but the architecture of Fig. 4 will produce a result which is ot equal to 0 sice it assumes that a dimiished-oe value of 0 at its iputs represets the ormal value of 1. I order to get the correct result, we ca simply force the +1 outputs i these cases to logic 0 by a series of 2-iput AND gates drive by the logic NOR of the a z ad b z zero idicatio bits. The complete architecture is the give i Fig. 5. The proposed architecture ca be based o ay architecture for dimiished-oe modulo 2 +1 multiplicatio. I the followig we preset architectures that ca be derived based o the dimiished-oe modulo multipliers preseted i [27] ad [24], which are cosidered the most efficiet orecoded ad Booth-recoded architectures i the ope literature, respectively. The architecture of [27] derives a partial product matrix with -bit wide partial products ad a additioal -bit correctio term (CT) equal to 0 0( a 1b )( 1 a 1b ). The 1 partial products ad the correctio term are the added with a adder tree composed of CSAs with IEAC ad fially a fast dimiished-oe two-operad adder is used to derive the -bits of the result. We have to ote that zero hadlig is ot take ito cosideratio i the multipliers of [27]. Accordig to Fig. 5, we ca use the architecture of [27] for derivig the result of the multiplicatio i ormal represetatio as log as we: (a) replace the fast dimiished-oe adder with the ehaced oe [40] i order to get +1 bits at the output, (b) add the 2-iput AND gates ad the 2-iput NOR gate at the output for hadlig the zero operads ad (c) icrease the correctio term by oe. This is easily achieved by replacig the CT vector of [27] with the correctio term 0 01( a 1b ). 1 Cosider ow the architecture of [24] which derives Booth-recoded dimiished-oe multipliers ad assume that is eve. The architecture derives /2+2 partial products, each -bits wide. /2 of them are attributed to the Booth-recodig, oe is a correctio term that is iput depedet ad the fial partial product is a costat correctio term with a value equal to 1. Similarly to the previous case, we ca use the architecture of [24] for derivig the proposed modulo multiplier. What we have to do is to use the ehaced dimiished-oe adder ad the AND gates at the output while also icreasig the CT by oe. Figure 4. Modulo 2 +1 multiplicatio. Figure 5. Proposed modulo 2 +1 multiplier architecture. 471

5 TABLE III. UNIT-GATE DELAY AND AREA ESTIMATIONS Dimiished-oe with zero hadlig Dimiished-oe + Coverter Proposed Adders 2log + 6 3log + 9 2log + 5 Subtractors 2log + 7 3log 0 2log + 6 Multipliers 4D(/2+2) + 2log + 9 4D(/2+2) + 3log 2 4D(/2+2) + 2log +10 Adders 3log (7/2)log /2log +7/2 +9 Subtractors 3log (7/2)log /2log +9/2 +9 Multipliers (9/2)log + (29/2) log + (39/2) /2log +(37/2) Proposed Dimiished 1+coverter Dimiished 1 Proposed Dimiished 1+coverter Dimiished (a) Proposed Dimiished 1+coverter Dimiished 1 Proposed Dimiished 1+coverter Dimiished (b) Proposed Dimiished 1+coverter Dimiished 1 Proposed Dimiished 1+coverter Dimiished (c) Figure 6. Uit-gate delay ad area compariso of (a) adders, (b) subtractors, ad (c) multipliers. V. EVALUATION AND COMPARISONS I this sectio we evaluate the proposed arithmetic uits ad compare them agaist the correspodig uits that use a dimiished-oe arithmetic uit with zero hadlig alog with a dimiished-to-ormal coverter at the output. For the dimiished-oe arithmetic uits we assume the architectures proposed i [15] [19] ad [24], which are cosidered to be the curret state of the art. For the dimiished-to-ormal coverter we assume a cotrolled biary icremeter with a Sklasky parallel-prefix structure [15]. A area-delay compariso of the various coverters ca be based o the uit gate model [42]. The uit gate model assumes that each mootoic gate couts as oe gate equivalet for both area ad delay, while two-iput XOR ad XNOR gates cout for two gate equivalets for both area ad delay. 472

6 TABLE IV. CMOS VLSI DELAY AND AREA RESULTS Dimiished-oe + Coverter Proposed (s) (μm 2 ) (s) (μm 2 ) Adders Subtractors Multipliers Table III presets area ad delay estimatios of the proposed arithmetic uits. The proposed adders ad multipliers are based o the ehaced dimiished-oe adders preseted i [40] while the proposed multipliers are based o the Booth-recoded multipliers preseted i [24]. The D(k) fuctio i the multipliers case deotes the umber of levels that are required i a Dadda adder tree for reducig k partial products to two. Table III also presets the area ad delay estimates of the correspodig dimiished-oe arithmetic uits, accordig to [15] [19] ad [24], as well as the estimates of the above metioed dimiished-oe arithmetic uits alog with the dimiished-to-ormal coverter. For the dimiished-to-ormal coverter, a delay equal to log+3 equivalet gates ad a area equal to (1/2)log+2+2 equivalet gates are assumed. Fig. 6 graphically compares the uit-gate area ad delay of the various arithmetic uits for values of up to 64. We observe that the delay of the proposed circuits is sigificatly smaller tha that of the dimiished-oe circuits with the coverter while it is very close to the delay of the dimiished-oe arithmetic uits. Regardig the area, the proposed adders ad subtractors are slightly larger tha the other two circuits uder compariso while all multipliers have approximately the same area. The uit-gate model estimatios for area ad delay ca oly be cosidered as idicative. To attai realistic results, arithmetic uits for 4 values of were described i HDL. After simulatig the resultig descriptios, the circuits were sythesized ad mapped to a 90 m CMOS implemetatio techology [43]. The Syopsys Desig Compiler tool [44] i the topographical mode was used for the sythesis ad mappig of the circuits. I this mode, for achievig faster timig closure, the tool performs floorplaig i parallel with sythesis ad mappig ad the desig is aotated with wirig legths ad fa-out ad parasitic capacitaces comig directly from the floorpla of the desig ad ot from a wire load model. We assumed that each circuit s iput ad output is drive by the output of a D flip flop ad drives the iput of a D flip flop of the same implemetatio library, respectively. A typical corer (1.2V, 25 o C) was cosidered. Each circuit was recursively optimized for speed usig a bottom-up approach. A fial area recovery step was the applied. Table IV presets the attaied area ad delay results. The results validate that the proposed circuits are sigificatly faster tha those where the dimiished-tobiary coversio is performed separately at the output of the dimiished-oe arithmetic uit. VI. CONCLUSIONS Novel modulo 2 +1 adders, subtractors ad multipliers have bee preseted i this paper. The proposed circuits, apart from their arithmetic operatio they also perform represetatio coversio, sice they accept dimiished-oe operads at their iputs ad produce their results i the ormal represetatio, avoidig that way the eed for a twostep reverse coversio process. The proposed arithmetic uits ca be efficietly utilized i RNS-based systems with moduli of the 2 +1 forms where the arithmetic processig is based o the dimiished-oe represetatio while the residue-to-biary coversio assumes the ormal represetatio. ACKNOWLEDGEMENT This work was supported by the Caratheodory Programme of the Uiversity of Patras (D.178). 473

7 REFERENCES [1] P. V. Aada Moha, Residue Number Systems: Algorithms ad Architectures, Netherlads: Kluwer Academic Publishers, [2] A. Omodi ad B. Premkumar, Residue Number Systems: Theory ad Implemetatio, Lodo: Imperial College Press, [3] R. Chaves ad L. Sousa, RDSP: A RISC DSP based o Residue Number System, I Proceedigs of 6 th Euromicro Symposium o Digital System Desig, 2003, pp , doi: /dsd [4] P. G. Feradez ad A. Lloris, RNS-based implemetatio of 8x8 poit 2D-DCT over field-programmable devices, Electroics Letters, vol. 39, o. 1, Ja. 2003, pp , doi: /el: [5] Y. Liu ad E. Lai, Moduli set selectio ad cost estimatio for RNSbased FIR filter ad filter bak desig, Desig Automatio for Embedded Systems, vol. 9, o. 2, 2004, pp , doi: /s [6] G. Cardarilli, A. Naarelli ad M. Re, Residue umber system for low-power DSP applicatios, I Proceedigs of Asilomar Coferece o Sigals, Systems ad Computers, Apr. 2007, pp , doi: /ACSSC [7] J. -C. Bajard ad L. Imbert, A full RNS implemetatio of RSA, IEEE Trasactios o Computers, vol. 53, o. 6, Ju. 2004, pp , doi: /TC [8] J. -C. Bajard, S. Duquese, M. Ercegovac, ad N. Meloi, Residue systems efficiecy for modular products summatio: Applicatio to Elliptic Curves Cryptography, I Proceedigs of of SPIE, Aug. 2006, doi: / [9] D. Schiiaakis, A. Fouraris, H. Michail, A. Kakaroutas, ad T. Stouraitis, A RNS implemetatio of a F p Elliptic Curve Poit Multiplier, IEEE Trasactios o Circuits ad Systems I, vol. 56, o. 6, Oct. 2009, pp , doi: /TCSI [10] U. Meyer-Baese, A. Garcia ad F. Taylor, Implemetatio of a commuicatios chaelizer usig FPGAs ad RNS arithmetic, VLSI Sigal Processig, vol. 28, o. 1 2, May 2001, pp , doi: /A: [11] M. Paella, ad G. Martielli, A RNS architecture for quasi-chaotic oscillators, Joural of VLSI Sigal Processig, vol. 33, o. 1 2, Ja. 2003, pp , doi: /A: [12] A. S. Madhukumar ad F. Chi, Ehaced architecture for Residue Number System-based CDMA for high-rate data trasmissio, IEEE Trasactios o Wireless Commuicatios, vol. 3, o. 5, Sep. 2004, pp , doi: /TWC [13] L. Kalampoukas, D. Nikolos, C. Efstathiou, H. T. Vergos, ad J. Kalamatiaos, High-Speed Parallel-Prefix Modulo 2-1 Adders, IEEE Trasactios o Computers, vol. 49, o. 7, Jul. 2000, pp , doi: / [14] H. T. Vergos, C. Efstathiou, ad D. Nikolos, Dimiished-Oe Modulo 2 +1 Adder Desig, IEEE Trasactios o Computers, vol. 51, o. 12, Dec. 2002, pp , doi: /TC [15] C. Efstathiou, H. T. Vergos, ad D. Nikolos, Hadlig Zero i Dimiished-oe Modulo 2 +1 Adders, Iteratioal Joural of Electroics, vol. 90, o. 2, 2003, pp , doi: / [16] C. Efstathiou, H. T. Vergos, ad D. Nikolos, Fast Parallel-Prefix Modulo 2 +1 Adders, IEEE Trasactios o Computers, vol. 53, o. 9, Sep. 2004, pp , doi: /TC [17] R. Patel, M. Beaissa, ad S. Boussakta, Fast Parallel-Prefix Architectures for Modulo 2-1 Additio with a Sigle Represetatio of Zero, IEEE Trasactios o Computers, vol. 56, o. 11, Nov. 2007, pp , doi: /TC [18] H. T. Vergos, ad C. Efstathiou, A Uifyig Approach for Weighted ad Dimiished-1 Modulo 2 +1 Additio, IEEE Trasactios o Circuits ad Systems II, vol. 55, o. 10, Oct. 2008, pp , doi: /TCSII [19] E. Vassalos, D. Bakalis, ad H. T. Vergos, Novel Modulo 2 +1 Subtractors, I Proceedigs of Coferece o Digital Sigal Processig, Jul. 2009, doi: /ICDSP z. [20] C. Efstathiou, Efficiet Modulo 2 +1 Subtractors for Weighted Operads, I Proceedigs of Iteratioal Coferece o Electroic Circuits ad Systems, Dec. 2010, doi: /ICECS [21] Z. Wag, G. A. Jullie, ad W. C. Miller, A Efficiet Tree Architecture for Modulo 2 +1 Multiplicatio, Joural of VLSI Sigal Processig, vol. 14, o. 3, 1996, pp , doi: /BF [22] Y. Ma, A simplified architecture for modulo (2 +1) multiplicatio, IEEE Trasactios o Computers, vol. 47, o. 3, Mar. 1998, pp , doi: / [23] C. Efstathiou, H. T. Vergos, ad D. Nikolos, Modified Booth Modulo 2-1 Multipliers, IEEE Trasactios o Computers, vol. 53, o. 3, Mar. 2004, pp , doi: /TC [24] L. Sousa, ad R. Chaves, A Uiversal Architecture for Desigig Efficiet Modulo 2 +1 Multipliers, IEEE Trasactios o Circuits ad Systems I, vol. 52, o. 6, Ju. 2005, pp , doi: /TCSI [25] H. T. Vergos, ad C. Efstathiou, Desig of Efficiet Modulo 2 +1 Multipliers, IET Computers ad Digital Techiques, vol. 1, o. 1, Ja. 2007, pp , doi: /iet-cdt: [26] R. Chaves, ad L. Sousa, Improvig Residue Number System Multiplicatio with more Balaced Moduli Sets ad Ehaced Modular Arithmetic Structures, IET Computers ad Digital Techiques, vol. 1, o. 5, Sep. 2007, pp , doi: /ietcdt: [27] C. Efstathiou, I. Voyiatzis, ad N. Sklavos, O the Modulo 2 +1 Multiplicatio for Dimiished-1 Operads, I Proceedigs of Coferece Sigals, Circuits ad Systems, Nov. 2008, doi: /ICSCS [28] Y. Wag, Residue-to-biary coverters based o ew Chiese Remaider Theorems, IEEE Trasactios o Circuits ad Systems II, vol. 47, o. 3, Mar. 2000, pp , doi: / [29] Z. Wag, G. A. Jullie, ad W. C. Miller, A improved residue-tobiary coverter, IEEE Trasactios o Circuits ad Systems I, vol. 47, o. 9, 2000, pp , doi: / [30] N. Burgess, Efficiet RNS-to-biary coversio usig high-radix SRT divisio, IEE Proceedigs Computers ad Digital Techiques, vol. 148, o. 1, 2001, pp , doi: /ipcdt: [31] Y. Wag, X. Sog, M. Aboulhamid, ad H. She, Adder based residue to biary umber coverters for (2-1, 2, 2 +1), IEEE Trasactios o Sigal Processig, vol. 50, o. 7, Jul. 2002, pp , doi: /TSP [32] B. Cao, C. H. Chag, ad T. Srikatha, A efficiet reverse coverter for the 4-moduli set {2-1, 2, 2 +1, } based o the ew Chiese Remaider Theorem, IEEE Trasactios o Circuits ad Systems I, vol. 50, o. 10, Oct. 2003, pp , doi: /tcsi [33] A. Omodi, Fast residue-to-biary coversio usig base extesio ad the Chiese Remaider Theorem, Joural of Circuits, Systems ad Computers, vol. 16, o. 3, Ju. 2007, pp , doi: /S X. [34] B. Cao, C. H. Chag, ad T. Srikatha, A residue-to-biary coverter for a ew five-moduli set, IEEE Trasactios o Circuits ad Systems I, vol. 54, o. 5, May 2007, pp , doi: /TCSI [35] P. V. Aada Moha, ad A. Premkumar, RNS-to-biary coverters for two four-moduli sets {2-1, 2, 2 +1, } ad {2-1, 2, 2 +1, }, IEEE Trasactios o Circuits ad Systems I, vol. 54, o. 6, Ju. 2007, pp , doi: /TCSI [36] Y. Kuo, S. Li, M. Sheu, J. Wu, ad P. Wag, Efficiet VLSI desig of a reverse RNS coverter for ew flexible 4-moduli set (2 p+k, 2 p +1, 2 p -1, 2 2p +1), I Proceedigs of Iteratioal Symposium o Circuits 474

8 ad Systems, May 2009, pp , doi: /ISCAS [37] A. Molahosseii, K. Navi, C. Dadkhah, O. Kavehei, ad S. Timarchi, Efficiet reverse coverter desigs for the ew 4-moduli sets {2-1, 2, 2 +1, } ad {2-1, 2 +1, 2 2, } based o New CRTs, IEEE Trasactios o Circuits ad Systems I, vol. 57, o. 4, Apr. 2010, pp , doi: /tcsi [38] K. Gbolagade, R. Chaves, L. Sousa, ad S. Cotofaa, A improved RNS reverse coverter for the { , 2, 2-1} moduli set, I Proceedigs of Iteratioal Symposium o Circuits ad Systems, May 2010, pp , doi: /iscas [39] L. Leibowitz, A simplified biary arithmetic for the fermat umber trasform, IEEE Trasactios o Acoustics, Speech, ad Sigal Processig, vol. 24, o. 5, Oct. 1976, pp , doi: /TASSP [40] H. T. Vergos, ad D. Bakalis, O Implemetig Efficiet Modulo 2 +1 Arithmetic Compoets, Joural of Circuits, Systems ad Computers, vol. 19, o. 5, Aug. 2010, pp , doi: /s [41] H. Paradeh-Afshar, A. Afzali-Kusha, ad A. Khakifirouz, A Very Fast ad Low Power Pseudo-Icremeter for Address Bus Ecoder/Decoder, I Proceedigs of Iteratioal Coferece o Microelectroics, Dec. 2006, pp [42] A. Tyagi, A reduced-area scheme for carry-select adders, IEEE Trasactios o Computers, vol. 42, o. 10, Oct. 1993, pp , doi: /ICCD [43] Syopsys Ic, SAED 90m EDK, 2011, [44] Syopsys Ic, Syopsys Desig Compiler User Guide, Versio E ,