A New 3-Bit Integrating Time to Digital Converter Using Time to Voltage Conversion Technique

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1 Bulleti of Eviromet, Pharmacology ad Life Scieces Bull. Ev. Pharmacol. Life Sci., ol 3 [11] October 2014: Academy for Eviromet ad Life Scieces, dia Olie SSN Joural s URL: CODEN: BEPLAD Global mpact Factor Uiversal mpact Factor ORGNAL ARTCLE A New 3-Bit tegratig Time to Digital Coverter Usig Time to oltage Coversio Techique Mahdi Rezvayvardom *, Tayebeh Ghaavati Nejad **, Ebrahim Farshidi *** * Departmet of Electrical Egieerig, Shahid Chamra Uiversity of Ahvaz, Ahvaz, ra ** Departmet of Electrical Egieerig, Shahid Chamra Uiversity of Ahvaz, Ahvaz, ra *** Departmet of Electrical Egieerig, Shahid Chamra Uiversity of Ahvaz, Ahvaz, ra farshidi@scu.ac.ir ABSTRACT this paper a ew dual slope time to digital coverter that employs the time to voltage coversio ad egratig techiques for digitizig the time erval iput sigals is preseted. The proposed coverter features high accuracy, very small average error ad high liear rage. Also this coverter has some advatages such as low circuit complexity, low power cosumptio ad low sesitive to the temperature, power supply ad process chages (PT) compared with the time to digital coverters that used precedig coversio techiques. order to evaluate the proposed idea, a egratig time to digital coverter is desiged i 0.18μm CMOS techology ad was simulated by Hspice. Compariso of the theoretical ad simulatio results cofirms the proposed TDC operatio; theore, the proposed coverter is very coveiet for applicatios which have average speed ad low variatios i the sigal amplitude such as biomedical sigals. Keywords: Time to digital coverter (TDC), time to voltage coverter (TC), idirect coversio TDCs, dual slope aalog to digital coverter Received Revised Accepted NTRODUCTON recet years, time to digital coverter has bee wide applicatios i idustries such as o-chip time sigal measuremet, biochemical sesor readout ad frequecy sythesis circuits [1-3], All Digital Phase Locked Loops (ADPLL) [4,5], laser rage fiders [3], digital storage oscilloscopes ad capacitive sesor readouts [6]. Curretly, may differet structures of time to digital coverters is proposed by researchers, each useful for a particular applicatio. geeral, the time to digital coverters ca be divided by researchers o two parts, direct ad idirect time to digital coversio schemes [7]. The time to digital coverters with direct coversio use the delay lies to measure the time erval betwee iput sigals (i.e. Start ad Stop). The mai disadvatages of these coverters are complex circuit structures ad hece high power cosumptio, high sesitivity to variatios i the process parameters, supply voltage ad temperature (PT) [8]. Whe a mismatch occurs betwee these coverters elemets, oliear factors appear i their operatio ad equatios. geeral, the dyamic rage of these coverters is limited by the umber of delay stages which leads to slow coversio rate [9]. Usually, time to digital coverters with idirect coversio have a two steps process to coversio that cotai time to aalog coversio stage ad a aalog to digital coversio stage. These coverters ca be divided o two parts: the ramp time to digital coverters [10] ad dual slope pulse stretchig time to digital coverters [11,12]. The advatages of these coverters are high precisio ad less sesitivity to PT variatios. Aother advatage of the idirect coversio schemes are simple circuit desig, the small umber of elemets, small occupied area of the C cheap ad theore low power cosumptio compared with the direct coversio techiques. Also, the idirect coversio techiques beefit the proper dyamic rage ad liearity. this paper, a ew TDC is preseted. The proposed coverter employs the time to voltage coversio ad egratig techiques to digitizig a time erval betwee iput sigals. The proposed coverter uses a idirect time to digital coversio method. Theore, our coverter has the appropriate liearity without extra elemets. The proposed coverter is useful for high accuracy ad the average speed BEPLS ol 3 [11] P a g e 2014 AELS, NDA

2 Rezvayvardom et al applicatios such as biomedical sigals. Sice i these sigals, the differece betwee two successive samples is much smaller tha the full-scale voltage. Also, the amplitude voltage i the biomedical sigals chages very slowly. the proposed coverter, erpolatio is performed based o the dual slope coversio. The offset voltage ad parasitic capacitors errors are elimiated i the proposed coverter. These errors are occurred i the TDC that have the capacitors i parallel with the comparators iputs ad affect o the coverter s accuracy ad resolutio. These problems exist i [8] ad [11] which use the erpolatio techique for time to digital coversio. The proposed coverter topology is simple ad its liear rage is high. The proposed coverter is a idirect TDC. Thus, the chip area ad subsequetly power cosumptio are reduced relatively. This paper orgaized as the followig: The secod sectio presets the backgroud of the egratig dual slope aalog to digital coverter. the third sectio, the block diagram ad the operatio modes of the proposed coverter is described theoretically. The fourth sectio shows the results of simulatio by Hspice i the TSMC 0.18μm CMOS Techology. Fifth, the results of the two previous sectios are compared with each other. Basic pricipals geeral, the aalog to digital coverters is divided to two mai parts, sigle-slope ad dual-slope coversio. itially, the egratig dual-slope aalog to digital coverter is described briefly. Because, the proposed time to digital coverter operate based o the dual-slope structure. Dual-slope aalog to digital coverter The block diagram ad the theoretical waveforms of the dual-slope aalog to digital coverter are show i the Fig. 1 ad Fig. 2 respectively [13]. this coverter, the iput voltage, i, is compared with the erece voltage,. The accuracy of the coverter is depedet to oly the egrator time costat, R 1C 1. The dual-slope ADC is performed i two phases. phase 1, the egrator capacitor, C 1, starts chargig. Also, the iput switch, S 1, is coected to the iput voltage, - i. Sice, the iput voltage, - i is a variable voltage thus, the egrator output is variable ad with the positive slope. The period of phase 1 is costat (i.e. T 1), ad equal to the period that couter cout from 00 0 to 11 1 oce i thermal code. Phase 2 is the dischargig phase. This phase starts whe the S 1 is coected to erece voltage,. This phase eds whe C 1 is discharged ad theore the comparator output becomes high. So, the period of the phase 2 is variable ad the slope of the egrator output is costat. Proposed egratig time to digital coverter This sectio ivestigates the performace of the proposed coverter i differet modes of operatio. The block diagram ad the theoretical waveforms of the proposed coverter are show i the Figure 3 ad Figure 4 respectively. The proposed coverter cotais a time to voltage coversio circuit, a egrator, a comparator, two couters ad a digital adder. This coverter has three differece operatio modes. Mode 1 the proposed coverter, mode 1 is the reset mode. this mode, both iput sigals (i.e. Start ad Stop) are low. S 1 is tured o. Theore, the egratig capacitor, C, is discharged ad the egrator output, out1, is zero. Also, the comparator output, out2, becomes oe ad both couters are reset. Durig this mode, other switches are off. the ed of this mode, the coverter is prepared to the operatio phase. Mode 2 Mode 2 starts whe the iput sigal, Start, becomes high while other iput sigal, Stop, is low. Thus, the period of mode 2 is the time erval betwee the risig edges of the iput sigals (i.e. Start ad Stop). this mode, S 2 is tured o ad S 3 is coected to while S 1 is off. Theore, the couter 1 is eabled ad starts coutig with the erece frequecy, f clk. this mode, the coverter operatio is divided to two parts that performed simultaeously: time to voltage coversio part ad egratig part. Time to voltage coversio part Time to voltage coversio part cotais a charge pump circuit ad a chargig ad dischargig capacitor. the charge pump circuit, the iput capacitor, C, is charged by the trasistor M 2 ad costat curret source (i.e. ), whe S 2 is tured o ad S 3 is coected to the erece voltage,. Theore, i the ed of this mode, C is charged to. The BEPLS ol 3 [11] P a g e 2014 AELS, NDA

3 Rezvayvardom et al Fig. 1. The block diagram of dual-slope aalog to digital coverter [13]. Fig. 2. The theoretical waveforms of dual-slope aalog to digital coverter [13]. Fig. 3. The block diagram of proposed time to digital coverter. BEPLS ol 3 [11] P a g e 2014 AELS, NDA

4 Rezvayvardom et al Fig. 4. The theoretical waveforms of proposed time to digital coverter. T (1) C polarity of is show i the Fig. 3. is proportioal to the time erval betwee iput sigals (i.e. T ) lieally. So, the is obtaied as: tegratig part the egratig part, the erece voltage,, is coected to the egrator iput by S 3. The egrator output, out1, is a ramp voltage with a egative slope. Because, is a positive voltage. Also, out1 is proportioal to T ad. Thus: out1 where is the egrator time costat ad equal to R C. T 1 T dt R C (2) 0 BEPLS ol 3 [11] P a g e 2014 AELS, NDA

5 the mode 2, the comparator output, out2 is low. For proper operatio, time to voltage coversio part ad egrator part should perform simultaeously. Mode3 Mode 3 starts whe the Stop sigal becomes high while Start sigal is high still. Theore, the couter 2 is eabled ad cout with the erece frequecy, f clk. this mode S 3 is coected to the iput capacitor, C, ad is coected to the egrator iput. Thus, the egrator output is a ramp voltage with positive slope. Because; the polarity of is egative. The equatios of this mode are: T T 1 T T2 0 T T C T 2 C dt 0 0 (3) 2 (4) where T 2 is the period of time whe the egrator capacitor, C, is discharged ad its voltage becomes zero. Accordig to the (3) ad (4), T 2 is idepedet of the time erval betwee the iput sigals, T, ad is proportioal to, ad C liearly. Mode 3 eds whe the out1 becomes zero. Theore, the comparator output is high ad couter 1 ad 2 are reset ad coutig are stopped. As a result, the couter 1 couts the time erval T T T2 ad the couter 2 couts the time erval T 2, both with the erece frequecy, f clk. The time to digital coverter should measure the time erval betwee the iput sigals, T. Thus i the couter 1 output, the produced digital code has a offset. This offset is equal to the couted digital code i durig T 2. The offset is elimiated whe produced digital codes of couter 1 ad 2 are etered to a digital adder. Theore, the fial output, D out, is the digital code for T. Accordig to the (1) to (4), the followig equatios are obtaied: T C C T i i T T2 (5) T 2 T2 T T 2 B out (6) i Bout b1 2 b b 1 2 b 2 where B out is the ratio betwee iput voltage ad erece voltage. b 1, b 2,, b are the biary factors. Simulatio Results Rezvayvardom et al This sectio ivestigates the simulatio results of the proposed time to digital coverter that simulated by Hspice i TSMC 0.18 m techology. The simulated coverter is a 3-bits time to digital coverter. For the proposed simulated coverter, is 100 A. With a 50-MHz erece clock, C ad C are 3pF ad 10pF respectively. Also, R is 100KΩ ad DD is 1.8. Fig. 5 ad Fig.6 are show the iput sigals (i.e. Start ad Stop) respectively. The time erval betwee the iput sigals, T, is selected 400S. Fig.7 ad Fig. 8 are show the ad out1 respectively. the Fig. 8, the ramp voltage with egative slope is related to the egratig from ad the ramp voltage with the positive slope is related to the egratig from. The simulated results of the proposed time to digital coverter cofirm the (1) to (5) equatios ad the theoretical waveforms i the Fig. 4. Fig. 9 ad Fig. 10 are show the couter 1 ad couter 2 outputs, D out1 ad D out2, respectively that are 3 bits. Accordig to the selected elemet ad T for the simulated proposed coverter, the (5) to (7) equatios cofirm the D out1 ad D out2. (7) BEPLS ol 3 [11] P a g e 2014 AELS, NDA

6 Rezvayvardom et al Fig. 5. The iput sigal, Start, waveform of the simulated proposed coverter Fig. 6. The iput sigal, Stop, waveform of the simulated proposed coverter Fig. 7. The iput capacitor voltage,, of the simulated proposed coverter Fig. 8. The egrator output voltage, out1, of the simulated proposed coverter BEPLS ol 3 [11] P a g e 2014 AELS, NDA

7 Rezvayvardom et al Fig. 9. The couter 1 output waveform, D out1, of the simulated proposed coverter Fig. 10. The couter 2 output waveform, D out2, of the simulated proposed coverter CONCLUSON this paper a ew egratig time to digital coverter is preseted. The proposed time to digital coverter employs the time to voltage coversio ad egratig techiques. The advatages of the proposed coverter are the appropriate liear rag without extra elemets, high accuracy, elimiatig the offset voltage ad parasitic capacitors error i the comparators output, low sesitive to the temperature, power supply ad process chages (PT), simple circuit desig ad theore low power cosumptio. The proposed egrated time to digital coverter is simulated by Hspice i TSMC 0.18 m techology. Compariso of the theoretical ad simulatio results cofirms the proposed TDC operatio. Refereces 1. Nois, R., Grollitsch, W., Sata, T., Cheriak, D., Da Dalt, N.(2013). digpll-lite: A Low-Complexity, Low-Jitter Fractioal-N Digital PLL Architecture. Solid-State Circuits, EEE Joural, vol.48, o.12, pp ercesi, L., Faori, L., De Berardiis, F., Liscidii, A., Castello, R.(2012). A Dither-Less All Digital PLL for Cellular Trasmitters. Solid-State Circuits, EEE Joural, vol.47, o.8, pp Roberts, G.-W ad Ali-Bakhshia, M.(2010). A brief roductio to time-to- digital ad digital-to-time coverters. EEE Tras. Circuits Syst., Exp. Briefs, Exp. Briefs, vol.57, o.3, pp BEPLS ol 3 [11] P a g e 2014 AELS, NDA

8 Rezvayvardom et al 4. Jeog, C.-H., Kwo, C.-K., Kim, H., Hwag,.-C., Kim, S.-W.(2013). Low-power, wide-rage time-to-digital coverter for all digital phase-locked loops. Electroics Lett, vol.49, o.2, pp Ha, Y., Li, D., Geg, S.; Xu, N.; Rhee, W.; Oh, T.-Y.; Wag, Z.(2013). All-digital PLL with ΔΣ DLL embedded TDC. Electroics Lett, vol.49, o.2, pp Che, P., Che, C.-C., Tsai, C.-C., ad Lu, W.-F.(2005). A time-to-digital-based CMOS smart temperature sesor. EEE Joural. Solid-State Circuits, vol.40, o.8, pp Xig, N., Woo, J-K., Shi, W-Y., Lee, H., Kim, S.(2010). A 14.6 ps Resolutio, 50 s put-rage Cyclic Time-to- Digital Coverter Usig Fractioal Differece Coversio Method. Circuits ad Systems : Regular Papers, EEE Trasactios o, vol.57, o.12, pp Kim, M., Lee, H., Woo, J-K., Xig, N., Kim, M-O., Kim, S.(2011). A Low-Cost ad Low-Power Time-to-Digital Coverter Usig Triple-Slope Time Stretchig. Circuits ad Systems : Express Briefs, EEE Tras, vol.58, o.3, pp Xig, N., Shi, W.-Y., Jeog, D.-K., Kim, S.(2010). High-resolutio time-to-digital coverter utilizig fractioal differece coversio scheme. Electro Lett, vol.46, o.6, pp Hsiao, M-J., Huag, J-R., Chag, T.-Y.(2004). A built-i parametric timig measuremet uit. EEE Des. Test Comput., vol.21, o.4, pp Che, P., Che, C-C., She, Y-S.(2006). A low-cost low power CMOS time-to-digital coverter based o pulse stretchig. EEE Tras. Nucl. Sci, vol.53, o.4, pp Saihua Xu., Yog Chig Lim., Jia Haur Wog., Quoc Huy Lam.(2013). Massively parallel time-stretched aalog-todigital coverter. Sigal Processig (CWSP 2013), Costatiides teratioal Workshop, 2013, vol.1, o.4, pp David. A. Johs, Ke Marti.(1997). Desig of Aalog CMOS tegrated Circuits. Joh Wiley & Sos. CTATON OF THS ARTCLE Mahdi R, Tayebeh G N, Ebrahim F. A New 3-Bit tegratig Time to Digital Coverter Usig Time to oltage Coversio Techique. Bull. Ev. Pharmacol. Life Sci., ol 3 [11] October 2014: BEPLS ol 3 [11] P a g e 2014 AELS, NDA