Continuous-Time Delta-Sigma. Shifting Dynamic Element Matching

Transcription

1 A83-dB SFDR 10-MHz Badwidth Cotiuous-Time Delta-Sigma Modulator Employig a Oe-Elemet- Shiftig Dyamic Elemet Matchig Hog Phuc Nih, Masaya Miyahara, ad Akira Tokyo Istitute of Techology, Japa

2 Outlie 1 Backgroud Proposed oe-elemet-shiftig OES) DEM method Implemetatio ad measuremet results Coclusio

3 Outlie 2 Backgroud Proposed oe-elemet-shiftig OES) DEM method Implemetatio ad measuremet results Coclusio

4 Receiver architecture 3 TV tuer 2G/3G cellular WLAN *10 MHz badwidth our target desig) *High Dyamic Rage DR) *High Spurious-Free Dyamic Rage SFDR) ΣΔ ADC is a hopeful solutio to achieve high DR & SFDR

5 ΣΔ ADC architecture 4 SNR Cotiuous-time ΣΔ ADC with multi-bit quatizer & DAC Limita atio of F s L=4 N=1,2,3,4 L=3 N: Quatizer resolutio OSR: oversamplig ratio =Fs/2/BW) L: filter order Our desig L=2 DAC liearity L=1 50 is a issue Low resolutio OSR

6 Liearity issues of feedback DAC Iput stage of ΣΔ ADC R V i ip N C i + - V im - + P R i V om V op Uity cell 5 Static error Mismatch C i I<7> Ip<7> I<1> Ip<1> I<0> Ip<0> E: Mismatch deviatio Trasitor size For simplicity, a 3bit DAC is cosidered

7 Liearity issues of feedback DAC Iput stage of ΣΔ ADC C i 6 R V i ip N + - V im - + P R i V om V op Dyamic error Glitch C i I<7> Ip<7> I<1> Ip<1> I<0> Ip<0> Normalized Parasitic capacitace glitch eergy No-ideal switchig For high h speed operatio, dyamic error becomes more critical

8 What is glitch eergy? 7 Switchig asymmetry I ua) T s) Glitch eergy Glitch area) Glitch eergy: average of 8192poits

9 Requiremets of DAC liearity 8 Static error Mismatch Dyamic error Glitch % 1.6% Requiremet for SNR>70dB BW=10MHz, Fs=500MHz)

10 Outlie 9 Motivatio Proposed oe-elemet-shiftig OES) DEM method Implemetatio ad measuremet results Coclusio

11 DEM topology summary 10 Prop. OES DWA-group ADWA, Bi-DWA) TC-group RTC, RSTC) Glitch Good Bad Ecellet Mismatch Good Ecellet Bad DEM: to improve DAC liearity) *Data Weighted Averagig DWA) [1] *Advaced Radom DWA ADWA) [2] *Bi-directioal DWA Bi-DWA) [3] *Thermometer Codig TC, w/o DEM) *Radomized Thermometer Codig RTC) [4] *Restricted Swappig Thermometer Codig RSTC) [5] [1] R. T. Baird et al., IEEE Tras. Circuits Syst. II,, Dec [2] I. Fujimori et al., IEEE J. Solid-State Circuits, Dec [3] D. H. Lee et al., IEEE Tras. Circuits Syst. II, Oct [4] D. H. Lee et al., IEEE Tras. Circuits Syst. II, Feb /11/30 [5] M. H. She et al., IEEE Tras. H.P. Circuits Nih, Syst. Tokyo II, Tech. May

12 11 OES: Elimiatig Effect of Glitch By reducig the umber of switched elemets g) w/ same other glitch coditios) g) Glitch eergy > = N N N g 1) ) 1), ) 2 1) ) 1), ) ) < + = 1) ) 1), ) 1) ) 1), ) 2 ) g 1) ) ) = g

13 Glitch Eergy 12 g) Glitch eergy Sim coditio *tfb-tf=trb-tr=20ps trb tr *Cp=10fF *3bit DAC w/o mismatch) Requiremet for SNR>70dB BW=10MHz, Fs=500MHz)

14 13 OES: Preserve Reductio of Mismatch Effect DA AC mismatch sp pectrum [db] By reducig the mismatch error spectrum i the iterestig badwidth w/ same mismatch deviatio) OES Good) ADWA Ecellet) RSTC Bad) Frequecy [MHz] DA AC mismatch sp pectrum [db] DA AC mismatch sp pectrum [db] %mismatch, iput: 1MHz@-30dBFS) Frequecy [MHz]

15 Mismatch requiremet 14 Mismatch DAC area Mismatch Relaatio Sim coditio *tfb-tf=trb-tr=0ps trb tr *Cp=10fF *3bit DAC w/o glitch) Requiremet for SNR>70dB BW=10MHz, Fs=500MHz)

16 With Both of Glitch ad Mismatch 15 w/glitch w/o DEM w/glitch OES 70 RSTC RTC 60 Bi-DWA ADWA mismatch OES achieves better SNDR & SFDR performace over the published DEM methods Sim coditio *tfb-tf=trb-tr=20ps *Cp=10fF *3bit DAC w/ mismatch)

17 Outlie 16 Backgroud Proposed oe-elemet-shiftig OES) DEM method Implemetatio ad measuremet results Coclusio

18 System architecture 17 Modulator Spec FF+FB, 3 rd order 4bit AD/DA BW: 10MHz Fs: 500MHz SNDR req : 70dB 90m CMOS process

19 OES DEM architecture 18 Eample for 4 elemets DAC OES DEM *Simplicity o etra poiter, o register) *Rela timig requiremet for feedback DAC

20 Modulator layout 19 OES DEM Core area: 9% Power cosumptio: 6%

21 Measuremet Results 20 w/o DEM OES-DEM Remove by digital filter BW W/o DEM OES DEM SNDR SFDR

22 Measuremet Results 21 SNDR-w/o DEM SFDR-w/o DEM SNDR-OES DEM SFDR-OES DEM Average of 10dB SFDR improvemet are achieved

23 Performace Compariso 22 Uit This work [6] [7] [8] Type/ DEM CT/OES CT/DWA DT/DEM CT/DWA Badwidth MHz Samp. freq. MHz SFDR db * * SNDR db DR db Power mw CMOS proc. m FoM fj/cov *Better SFDR compared with cov. DEM method) *Less power w/ same SFDR) [6]J. G. Jo et al., ASSCC Dig. Tech. Papers, Nov [7]O. Rajaee et al., IEEE J. Solid-State Circuits, Apr /11/30 [8]K. Matsukawa et al., IEEE Symp. o VLSI H.P. Circuits, Nih, Ju. Tokyo Tech.

24 Outlie 23 Backgroud Proposed oe-elemet-shiftig OES) DEM method Implemetatio ad measuremet results Coclusio

25 Coclusio 24 Proposed OES DEM method substatially suppresses the both effects of mismatch ad glitch. ΣΔ modulator usig OES DEM achieves 83dB SFDR ad 10dB improvemet compared to o DEM. Simplicity ad effectiveess of the OES techique makes it very attractive ad prefer for cost ad power cosideratios.

26 Ackowledgmets 25 This work was supported by CREST, JST, VLSI Desig ad Educatio Ceter VDEC), the Uiversity of Tokyo i collaboratio with Cadece Desig Systems. The authors also ackowledge Berkeley Desig Automatio for the use of the Aalog FastSPICE AFS) Platform.

27 Referece 26 [1] R. T. Baird ad T. S. Fiez, Liearity ehacemet of multibit Σ A/D ad D/A coverters usig data weighted averagig, IEEE Tras. Circuits Syst. II, Aalog Digit. Sigal Process., vol. 42, o. 12, pp , Dec [2] I. Fujimori, L. Logo, A. Hairapetia, K. Seiyama, S. Kosic, J. Cao, ad S. L. Cha, A 90-dB SNR 2.5-MHz output-rate ADC usig cascaded multibit delta-sigma modulatio at 8X oversamplig ratio, IEEE J. Solid-State Circuits, vol. 35, o. 12, pp , Dec [3] D. H. Lee, ad T. H. Kuo, Advacig data weighted averagig techique for multi-bit sigma delta modulators, IEEE Tras. Circuits Syst. II, Ep. Briefs, vol. 54, o. 10, pp , Oct [4] D. H. Lee, T. H. Kuo, ad K. L. We, Low-cost 14-bit curret-steerig DAC with a radomized thermometer-codig method, IEEE Tras. Circuits Syst. II, Ep. Briefs, vol. 56, o. 2, pp , Feb [5] M. H. She, J. H. Tsai, ad P. C. Huag, Radom swappig dyamic elemet matchig techique for glitch eergy miimizatio i curret-steerig DAC, IEEE Tras. Circuits Syst. II, Ep. Briefs, vol. 57, o. 5, pp , May [6] J. G. Jo, J. Noh, ad C. Yoo, A 20MHz badwidth cotiuous-time Σ modulator with jitter immuity improved full-clock period SCR FSCR) DAC ad high speed DWA, ASSCC Dig. Tech. Papers, pp. 1-4, Nov [7] O. Rajaee, T. Musah, N. Maghari, S. Takeuchi, M. Aiya, K. Hamashita, ad U. K. Moo, Desig of a 79 db 80 MHz 8X-OSR Hybrid Delta-Sigma Pipelied ADC, IEEE J. Solid-State Circuits, Vol. 45, No. 4, pp , Apr [8] K. Matsukawa, Y. Mitai, M. Takayama, K. Obata, S. Dosho ad A., A 5th-Order Delta-Sigma Modulator with Sigle-Opamp Resoator, IEEE Symp. o VLSI Circuits, pp , Ju

28 27 Thak you!!!