Design of FPGA- Based SPWM Single Phase Full-Bridge Inverter

Transcription

1 Desig of FPGA- Based SPWM Sigle Phase Full-Bridge Iverter Afarulrazi Abu Bakar 1, *,Md Zarafi Ahmad 1 ad Farrah Salwai Abdullah 1 1 Faculty of Electrical ad Electroic Egieerig, UTHM * afarul@uthm.edu.my Abstract Nowadays power iverters serve as a importat emergecy power supply system i evets of mai power supply failure. The AC output voltage of a power electroic iverter is usually o-siusoidal ad hece has a high harmoic cotet. Siusoidal Pulse Width Modulatio (SPWM) scheme is ormally used to covert the DC power supply ito AC power supply by comparig the referece voltage waveform with the triagular waveform kow as carrier. SPWM provides a way to reduce the total harmoic distortio of load curret. The objective of this paper is to demostrate a SPWM switchig scheme by usig Altera DE2-70 board. I this SPWM techique, a siusoidal referece voltage waveform is compared with the triagular carrier voltage to geerate the o ad off switchig states. This switchig scheme will trigger the gate of the power switch. I this paper, the SPWM switchig strategies implemeted usig Altera DE2-70 (Cycloe II EP2C35F672C6) with 16 bit serial cofiguratio devices. The switchig betwee referece ad carrier waveforms of SPWM is obtaied by usig Matlab software. Simulatio o the desig waveform is coducted usig Quartus II software tools provided by Altera. The output frequecy of SPWM is 50 Hz ad the desig is limited to two values of modulatio idices which are 0.5 ad Keywords: SPWM-Siusoidal Pulse Width Modulatio, FPGA-Field Programmable Logic Array, VHDL- Very High Descriptio Laguage.

2 1. INTRODUCTION Pulse width modulatio (PWM) is the most popular switchig techique used i several types of coverters with a appropriate switchig scheme to produce a desired switchig patter. PWM is oe of the switchig techiques used for a AC-to-DC coverter to produce a AC output sigal fed from DC iput [1]. The o ad off scheme is based o the itersectio of the triagular carrier sigal ad a costat DC referece sigal. The PWM techique still cotais a harmoics ad aother approach is to use Siusoidal Pulse Width Modulatio (SPWM) switchig techique [2]. This paper presets the work carried out to produce the bipolar SPWM cotrol sigal. I SPWM a fixed triagular waveform is compared with a siusoidal waveform ad the amplitude of output waveform ca be varied from rage 0 to 1 [1]. The o ad off switchig states will be geerated whe the istataeous value of the referece sigal is larger tha the triagular carrier. I order to implemet SPWM switchig usig Altera DE2-70 board, the switchig iterval betwee each crossig is calculated usig Matlab software. The crossover poit of the sigal is the trasferred ito a table. For the hardware, Altera DE2-70 Cycloe II DE-2 70 is used. It provides a wide rage of desity, memory, embedded multiplier ad packagig optios i a customer-defied FPGA feature set optimized for low-cost applicatios. I additio, Cycloe II FPGA also supports a wide rage of commo exteral memory iterfaces ad I/O protocols commo i lowcost applicatios. It is expected the use of FPGA easier to geerate the cotrol sigal for sigle phase full bridge iverter. Furthermore, the desig of the switchig pulse ca be altered without ay chages i hardware. This is the mai advatage of this approach that applied the FPGA techology where there is a flexibility of ay chage o the switchig parameter ad directly elimiates the complexity of the hardware. Matlab M-File. The program is capable to produce the SPWM waveform characteristic over several rages of frequecies, modulatio ad umber of pulses. The iput data is processed through a mathematical programmig ad the itersectio betwee referece sigal ad carrier sigal geerates PWM pulses for a period of α to ß i each pulse as show i Fig. 2. I Fig. 2, is the umber of pulse for half cycle of referece sigal. The program is implemeted usig Matlab/M-file programmig ad is achieved through six steps as demostrated i Fig. 3. Fig 2 Geeratio of SPWM switchig scheme Fig. 3 Block diagram of Matlab Programmig I this paper, the selected frequecy of the output iverter is 50Hz with two modulatio idices that is 0.75 ad 0.5. The SPWM output sigal is recorded based o time scale ad degree scale. These data are used to produce the SPWM switchig states whereas the time will be digitized. Fig. 1 Sigle phase Full-Bridge Iverter 2. MATLAB PROGRAMMING A program is developed from the fudametal cocept of the SPWM switchig techique by usig 3. SWITCHING STRATEGIES The coverter is used a Isulated Gate Bipolar Trasistor (IGBT) as the switchig device. The IGBTs have simpler drivig circuits tha other power switchig devices which lead to high-power applicatio. The iverter is sigle phase full-bridge topology with IGBT used as switchig devices. The 50Hz referece frequecy data ad the chose modulatio iduces are obtai from Matlab software the depicted i Table 1 (a) ad (b) respectively. The recorded data are take over oe complete cycle of

3 referece sigal. Iitially, the data recorded are i degree scale; this are coverted to time scale. I this form, the data is easier to use to geerate digital SPWM sigal. From the table, it ca be observed that the width of each pulse at the begiig ad at the ed of every half cycle i the same scale. For istat, the positive half cycle of referece sigal, the width of the pulse t 1 is equal to the pulse of t 20. The period of the referece iput frequecy is 1 T = f ref For the half cycle, T 2 (1) The values of α, β ad the width of the pulses expressed i term of time ca be determied from equatios (3), (4), ad (5) respectively. T / 2 α ( t) = α ( ) 180 T / 2 β ( t) = β ( ) 180 (2) (3) Width = β α (4) All the calculated itersectio values for α ad β are show i Table 1 (a) ad (b). The last itersectio poit betwee the referece sigal ad carrier sigal occurs at β 40 which is equal to 19.76ms ad this happes at the last pulse over oe cycle of 20ms. Table 1: (a) ad (b): Data obtaied from Matlab for modulatio idices 0.5 ad 0.75 (b) 4. VHDL PROGRAMMING USING QUARTUS II By usig Quartus II 8.0 sp1 software provided by Altera, the data obtaied from Table 1 digitized for implemetatio i Quartus II software. Fig. 4 illustrates the block diagram of the complete SPWM geerator for modulatio idices 0.5 ad The block diagram cosists of altpll which is able to geerate a 25 MHz clock output from the 50 MHz iteral clock of Altera DE2-70 board. The altpll megafuctio ca be used to geerate other clock. It ca be set to operate at multiples frequecy. The clock divider is applied to divide iteral clock of Altera DE2-70 board ito several frequecy rages. For example, the iteral clock frequecy ca be divided ito 25 MHz, 1 MHz, 100 khz, 1 khz ad etc. The, the 1 MHz of the output frequecy of clock divider is coected to the lpm_couter which cout from 0 to over oe complete cycle. This meas, oe cycle of this frequecy represets the period of 1 µs. The lpm_couter megafuctio is a biary couter that either ca be set for coutig up, dow or simultaeously. The o ad off sigal is created by VHDL programmig ad geerator coverted ito block diagram. The VHDL program for 0.75 ad 0.5 modulatio idices are created by employig four switches which are operated i pairs at a time (S1-S2 ad S3-S4). (a)

4 Files (.sof). The cofiguratio data for devices are dowloadad to programm the hardware. The voltage level of the iput ad output o the expasio header ca be adjusted to 3.3V, 2.5V or 1.8V. Fig. 4 Block diagram of SPWM geerator Before uploadig the program ito DE2-70 board, the SPWM sigal is first simulated by usig Waveform Editor. Fig. 5 shows the output SPWM geerated. At this poit, the measured value is compared with the differet betwee the observed. The shapes of the SPWM waveform at high speeds for short iterval ca be observed by usig compress optio to compress the waveform. The output of the SPWM geerator is the assiged to the expasio header of the DE2 board through Pi Plaer. The expasio headers coect directly to 36 pis of the Cycloe II FPGA chip. Table 2 show the output cotrol sigal available at expasio header pis. 5. RESULTS Tektroix four chael digital oscilloscope TDS3054B is used to measure the output voltage from the DE2-70 board. The experimet was coducted for both modulatios which are 0.5 ad Fig. 6 ad Fig. 7 demostrate the width differece implemetatio modulatio 0.5 ad 0.75 respectively. I actual situatio, the upper traces sigals of Fig. 6 ad Fig. 7 are used to cotrol the turig o/off of the power switches S1S2 while the lower traces is to cotrol power switches S3S4 of the iverter. The width of both pulses from t 1 to t 40 is aalyzed ad compared with the simulated sigal usig Quartus II software. The timig differeces betwee the waveform at the scree are compared for verificatio check for accuracy. Thus it ca be said that the accuracy of the iteral clock of the DE2 board is very precise. Fig. 5 Cotrol sigal for 0.5 ad 0.75 Fig. 6 Output sigal for modulatio idex 0.5 Table 2: Output of SPWM coected to expasio header DE2 board Modulatio Idices (ma) Switch S1 S2 S3 S4 S1 S2 S3 S4 Expasio Header PIN N_24 PIN N_29 PIN M_22 PIN M_21 PIN N_21 PIN N_22 PIN L_21 PIN L_22 The Assembler which is the compiler module that completes project processig will geerate a device programmig image. For the FPGAs, this programmig image is i the form of oe or more Programmer Object Files (.pof) ad SRAM Object Fig. 7 Output sigal for modulatio idex 0.75

5 Fig. 8 Dead time for 0.5 modulatio idex Fig. 11 Output sigal for S1S2 ad S3S4 with modulatio idex= 0.75 Fig. 9 Dead time for 0.75 modulatio idex Fig. 8 ad Fig. 9 show the dead time betwee switches S1S2 ad S3S4 for the modulatio idices of 0.5 ad 0.75 respectively. From these figures, it ca be observed that the dead time for modulatio idices 0.5 ad 0.75 are 420µs ad 460µs respectively. The occurrece of dead time betwee the S1S2 ad S3S4 shows that the sigal is possible to be implemeted. It is based o the characteristics of the tur o ad tur off of the IGBT which up to ao secod. The SPWM sigals with the modulatio idices of 0.5 ad 0.75 have the amplitudes of 3.3 V ad 3.24 V respectively ad show i Fig. 10 ad Fig CONCLUSIONS This paper has outlied ad illustrated a method to obtai the switchig pulses i geeratig a SPWM sigal for a sigle-phase iverter. The SPWM sigal has bee desig ad tested usig Quartus II software ad implemeted o Altera DE2-70 Board. The modulatio idex, umber of pulses over a period ad the output frequecy ca be easily chaged usig the program. The SPWM sigal is uploaded o a sigle chip of Altera Board ad it capable to provide flexibility, reliability ad ease to program i order to cotrol a sigle-phase iverter. ACKNOWLEDGMENT The author/authors would like to thak Uiversiti Tu Hussei O Malaysia (UTHM) for supportig this research uder the Short Term Research Grat. REFERENCES [1] Muhammad, H. Rashid. Power Electroics Circuits, Devices ad Applicatio. Upper Saddle River, NJ: Pretice Hall, [2] M. N. Md Isa, M.I. Ahmad, Sohiful A.Z. Murad ad M. K. Md Arshad, FPGA Based SPWM Bridge Iverter, America Joural of Applied Scieces 4 (8), 2007, pp Fig. 10 Output sigal for S1S2 ad S3S4 with modulatio idex= 0.5