Cascaded Feedforward Sigma-delta Modulator for Wide Bandwidth Applications

Transcription

1 Tamkag Joural of Sciece ad Egieerig, Vol. 4, No., pp () 55 Cascaded Feedforward Sigma-delta Modulator for Wide Badwidth Applicatios Je-Shiu Chiag, Teg-Hug Chag ad Pou-Chu Chou Departmet of Electrical Egieerig Tamkag Uiversity Tamsui, Taipei, Taiwa 5, R.O.C. Abstract A ew sigma-delta modulator architecture for wide badwidth applicatio called cascaded feedforward sigma-delta modulator is proposed i this paper. This sigma-delta modulator is similar to the covetioal feedforward summatio sigma-delta modulator. The covetioal feedforward summatio sigma-delta modulator uses multi-bit feedback ad therefore a multi-bit digital-to-aalog coverter (DAC) is eeded. Due to the oliearity of the multi-bit DAC, it is difficult to be implemeted. O the other had the proposed approach uses.5-bit feedback, ad thus the implemetatio of the aalog part is much easier tha the covetioal oe. Sice the.5-bit feedback will cause coarse quatizatio errors, error cacellatio must be doe i the digital part. Here a adaptive filter with least mea square algorithm is used to reduce the oliear effect. The simulatio results show that the sigal to oise plus distortio ratio (SNDR) of this architecture is very close to that of the ideal feedforward summatio sigma-delta modulator with multi-bit DAC ad ca be used for the wide badwidth applicatio. Key Words: Wide-badwidth, Cascaded Sigma-delta Modulator, Feedforward, xdsl, Dual-quatizer. Itroductio The sigma-delta modulatio (SDM) techique has become popular i the desig of high-performace aalog-to-digital coverters []. Due to the oversamplig approach, SDM is difficult to be implemeted i the wide badwidth applicatios, such as image processig, widebad CDMA,, etc. There are may varieties of architectures to desig a sigma-delta modulatio such as MASH, sigle-loop, cascaded, feedforward summatio, distributed feedback,, etc [8]. The feedforward summatio with local resoator feedback sigma-delta modulator (FFSDM) [8] is realized by usig aalog filter desig approach ad is suitable for wide-badwidth applicatios. I FFSDM, it is implemeted by aalog filter desig approach, ad thus the cut-off frequecy (db frequecy) ca be easily decided to determie the desired badwidth ad oise floor. Kuo et al. proposed a high order FFSDM sythesis tool (HOST) to decide the filter coefficiets ad make the realizatio of FFSDM very easily [7]. I order to be applied to the wide-badwidth systems i FFSDM, multi-bit quatizatio is used for achievig the desired sigal-to-oise ratio (SNR). For a fixed order SDM, we ca icrease the bit umbers of the iteral quatizer or the oversamplig ratio (OSR) to improve the SNR. Due to the oversamplig ature, i wide badwidth applicatios the OSR of a SDM caot be very high otherwise the badwidth will be very limited. Therefore, i the wide badwidth SDM desig we have to icrease the bit umbers of the iteral quatizer istead of OSR to gaieough SNR. For that reaso, a multi-bit digital-to-aalog coverter

2 56 Je-Shiu Chiag et al. (DAC) i the feedback of the SDM is required. As we kow, i the VLSI circuit desig the DAC has the iheret oliearity, ad may cause desig complicatio sigificatly. I order to make the SDM implemetatio easier, we propose a ew SDM architecture that is similar to the architecture of FFSDM but without multi-bit DAC; we call this SDM as cascaded feedforward sigma-delta modulator (CFFSDM). I this architecture, a.5-bit quatizer substitutes the multi-bit DAC, ad the error cacellatio techique is adopted to elimiate the coarse quatizatio error i the digital part. Geerally, digital circuits have better liearity tha aalog circuits (DAC). Sice the techology of digital circuits is very matured curretly, ad the implemetatio of the aalog circuits of CFFSDM is ot difficult, all these characteristics show that this ew SDM ca be easily implemeted to a wide badwidth applicatio. This paper is orgaized as follows: Sectio is the itroductio. Sectio describes the covetioal wide-badwidth SDM architecture. Sectio illustrates the architecture of CFFSDM. We aalyze the o-ideal effects of CFFSDM i Sectio 4; the comparisos ad simulatio results are show i Sectio 5. Fially we give the coclusio i Sectio 6.. Architectures of the Covetioal Wide Badwidth Sigma-Delta ADC The sigma-delta aalog to digital coversio has bee popular over the past 5 years. It exploits the advacig of the moder fie-lie CMOS process to obtai high-resolutio ADC without sufferig from its iaccuracy. However, due to its oversamplig ature, the coversio badwidth of the sigma-delta ADC is severely limited. This limitatio ca be partly alleviated by usig some special architecture such as cascaded multistage architecture or MASH []. MASH combies several low order modulators to achieve a high-order oise shapig fuctio, ad ca improve the performace by icreasig stages or orders. However, the mismatch betwee stages may degrade the performace. I order to maitai a good performace for a cascaded SDM with oe bit quatizer, it has to icrease the OSR or order. Aother approach to improve SNR is to use multi-bit quatizer [5]. For example, the SNR of a secod order cascaded SDM ca be obtaied by the followig equatio [8]: SNR max = 6.N log( OSR) () where N is the bit umber of the quatizatio. From equatio (), we ca fid that doublig the OSR improves the SNR by 5 db ad icreasig bit of the quatizatio ca improve the SNR by 6 db. The oise trasfer fuctio (NTF) of the L sigle-loop or cascaded SDM is NTF = ( z ). Whe the order L is high, the quatizatio oise is more effectively suppressed at low frequecies, ad we have more gai at high frequecies. That implies that this fuctio may ot be suitable i lower OSR applicatios. The problem ecoutered i the oise shapig fuctio is the large high frequecy oise shapig gai for large L. The idlig waveform at the comparator iput becomes very large due to low comparator gai ad makes the system to become ustable. We ca modify the pure differetiatig respose by itroducig poles ito the NTF, ad the NTF ca be expressed as ( z ) NTF =. The purpose of addig is to flatte the frequecy portio of the NTF as show i Figure. Accordig to Figure, we fid that as the badwidth is higher, the oise floor of ( z ) NTF = is effectively suppressed by L NTF = ( z ). Sice the NTF is simply a th-order high pass fuctio, we ca desig the badwidth ca be desiged by determiig the db frequecy of the filter, ad the SNR ca be determied by the filter order or the quatizatio bit umbers. I [,8,] a Butterworth or a iverse-chebyshev high pass fuctio is used for the desig of the NTF deomiator, ad the proper zeroes ca be added to its umerator to icrease the i-bad oise suppressio. NTF gai i db Frequecy (-Z) (-Z) Z) Figure. Modifyig the NTF to reduce high frequecy gai I this paper, the NTF is desiged by iverse-chebyshev filter. Figure shows the frequecy respose of a iverse-chebyshev high-pass fuctio. First, let us describe the N=5

3 Cascaded Feedforward Sigma-Delta Modulator for Wide Badwidth Applicatios 57 architecture ad some disadvatage of the sigma-delta modulator with feedforward summatio ad local resoator feedbacks (FFSDM). The block diagram of FFSDM is show i Figure. Magitude(dB) Magitude of a iverse-chebyshev high pass fuctio Frequecy(HZ) Figure. The frequecy respose of a iverse-chebyshevhigh pass fuctio X z z 4 a z b a e V a Y z b z a 4 5 Figure. Liear model of a feedforward sigma-delta modulator I FFSDM, it is possible to move the ope-loop poles (which become the NTF zeros whe the loop is closed) away from dc alog the uit circle by addig a small egative-feedback term (r i ) aroud pairs of itegrators i the loop filter. This causes the frequecies of ifiite loop gai (ad hece ifiite oise atteuatio) to be shifted away from dc to fiite positive frequecies. The equatio for a pair of itegrators with feedback is z R ( = () z ( r) z The poles have a radius of ad a frequecy ω, r ω = a cos( ) r for r << () Equatios () ad () are derived by assumig that oe of the itegrators has a simple delay while the other does ot. This ca be accomplished i switched-capacitor circuits by correctly phasig a 5 the switches from the egative feedback etwork. A slightly less effective resoator ca be built by usig feedback aroud pairs of itegrators, while allowig both itegrators to have a z - delay term i the umerator. I this case, the poles move o a vertical lie from the (, j) poit away from the real axis ad therefore do ot exhibit ifiite gai at the resoace frequecy. The switched-capacitor implemetatio for the dual-delay itegrator pair is simple ad does ot require double op-amp settlig. To solve the coefficiets, we ca use Kuo s high-order SDM sythesis tool, HOST [7]. Accordig to Maso gai theorem, the NTF of a eve-order (N=m) ca be expressed as N( NTF FF = where = m N Z) [( z ) r i ] i= = m m m Z) [( ri ] ([a i (z ) a i ] [( rj ]) i= i= j= i ( (4) (5) By equatig the NTF FF ( ad the sythesized NTF(, the SDM coefficiet ca easily be obtaied. The desig flow is expressed as follows: First, the coefficiet r's are used to fit the zeros i the sythesized NTF(. Whe r's are obtaied, a's ca also be obtaied by equatig their deomiators. The coefficiet g's are set to ; this approach may limit the swig of the itegrator but the coefficiet ca be adjusted to avoid overload. The stability of this architecture is decided by the oise power gai (NPG) that ca be expressed as follows: π jω NPG = ( NTF( e ) ) dω (6) π A large NPG may icrease the high-frequecy oise that may result i destabilizatio of the modulator [], ad cause the modulator to become ustable. Although the FFSDM is a good architecture for wide badwidth applicatio, the multi-bit quatizatio may cause difficulties i the hardware implemetatio. By usig the multi-bit quatizer i the FFSDM, a multi-bit DAC is required ad the DAC may cause the performace degradig. Figure 4 shows the geeral model with DAC errors. The output of the SDM fuctio with DAC errors ca be derived as: Y( = G(X(H(E Q (-G(E D ( (7)

4 58 Je-Shiu Chiag et al. L( where G( = is the sigal trasfer L ( fuctio (STF) ad ca be desiged as a low pass filter; H ( = L ( is the oise trasfer fuctio (NTF) ad ca be desiged as a high pass filter. Accordig to equatio (7), the DAC error caot be shaped by H( ad will appear i the base-bad to icrease total oise floor. Due to the oliear effects, the SNR will decrease sigificatly whe the DAC error is large. May architectures such as data weighted averagig algorithm (DWA) [9] ad dyamic elemet matchig (DEM) [] ca be used to solve this problem. Although DWA ad DEM are iveted to solve the oliearity problems of DAC i SDM, the solutios are still too complicated. A ew SDM architecture without multi-bit DAC but has good performace is proposed i this paper, ad the details are described i ext sectio. X Σ L( α E Q Σ E D Σ Figure 4. The liear block diagram of a geeral SDM with DAC error. A New Architecture of Wide Badwidth Sigma-Delta Modulator I the ew SDM architecture, we use a.5-bit quatizer i the feedback path ad thus elimiate the multi-bit DAC; we also use error cacellatio scheme i the digital part to cacel the coarse quatizatio errors. We call this SDM as cascaded feedforward sigma-delta modulator (CFFSDM). The schematic diagram of this architecture is show i Figure 5. X z z a z b a e V Y a V e Y g z z b g z z a - H(Z) V Figure 5. The architecture of cascaded feedforward sigma-delta modulator V W a For the topology show i Figure 5, the loop filters are essetially idetical: a a a a L ( =... z ( z ) ( z ) ( z ) (8) Oce the loop filter is set for optimum oise shapig, ad thus the STF is fixed. Specifically, L G( = H ( = (9) L where H ( = () L ad v = v e. () The digital outputs v ad v ca be expressed as v = Gu He () v = [( v e ) v ] e () If the digital filter H is chose to be H = H = NTF, (4) the the output w becomes w = v H v = Gu He (5) I (5), the coarse quatizatio oise e is cacelled i the ideal case. Therefore the output fuctio of CFFSDM ad the ideal output fuctio of FFSDM with multi-bit DAC are idetical. The CFFSDM does ot oly solve the oliearity of the multi-bit DAC problems but also has very good error resistace to the pole errors, gai errors, ad coefficiet variatios. Although, we eed a digital filter to maitai the same system performace with covetioal FFSDM but as we kow, the digital circuits are simpler ad have lower area ad oise tha aalog circuits. Therefore, our proposed architecture ca reduce the aalog circuit (o DAC requiremet) ad oly eed to add a digital filter. The simulatio results are show i Sectio V. The oideality effects ad error cacellatio schemes are described i ext sectio. 4. Noliearity Effects ad Error Cacellatio Schemes The major aalog imperfectios of the CFFSDM are pole errors, gai errors, ad coefficiet variatios, ad they are described i the followig subsectios. 4. Pole Errors The pole error is a importat oideality that ca degrade the performace of the CFFSDM. This error is due to the fiite itegrator gai at dc (A dc ),

5 Cascaded Feedforward Sigma-Delta Modulator for Wide Badwidth Applicatios 59 ad ca further shape the quatizatio oise. The trasfer fuctio of a delay ad leaky itegrator is: H ( = (6) z ( ) A dc Therefore, the trasfer fuctio of L( i CFFSDM will become: L ( z ) = a z ( a [ z ( A dc A dc ) )] a [ z (... A dc )] a [ z ( A (7) This effect may chage the NTF ad degrade the SNR. 4. Gai Errors Mismatches betwee the samplig ad itegratig capacitors resultig i a gai error i the trasfer fuctio of a switched-capacitor itegrator ca be expressed as: λ H ( = z (8) where λ = C = C C ) ( C ) (9) ( C ad C is the relative capacitor errors of the itegrators. Thereafter L( becomes: a ( λ ) a ( λ ) a ( λ ) L ( z ) = z ( z ) ( z )... a ( λ ) ( z ) dc )] ( ) This effect may chage the pole locatio of the NTF, ad may degrade the performace or make the modulator to become ustable. 4. Coefficiet Variatios The coefficiet variatios may deviate L(, ad thus chage the desired NTF to a ukow status. The effect of coefficiet variatios may cause a coarse quatizatio oise e through the leakage path. The output voltage i z-domai becomes: V ( = V H ( E( () real ideal leakage Let us Assume small relative errors, ad the the trasfer fuctio, H leakage (, of the leakage oise ca be approximated by a fiite Taylor series expasio: H leakage Vreal( ( = E ( X ( = E ( = M ( z ) ( z ) ( z ) = A A A... AM () where coefficiets A, A,, A M- are fuctios of both the dc op-amp gai A dc ad the relative capacitor errors C of the itegrators. The filterig i ( z ) effects of factor are depedet o the OSR. I order to elimiate the leakage e i the output, we use a adaptive filter with least mea square (LMS) algorithm ad a dither ijectio scheme to correct the imperfectio of the aalog circuit [6,]. The schematic diagram of the CFFSDM with error correctio schemes is show i Figure 6. X z z a z b a e d V Y a V e d g z z b V g z z a - L(Z) correlatio H(Z) V L Figure 6. CFFSDM with error correctio scheme The mai compoets of V i Figure 6 are the egative.5-bit quatizatio oise (-e ) ad dither (-d); the z-trasform is give by: V = E ( d( E ( E ( d( () Ad hece, the digital correctio sigal V L i Figure. 6 is give by: V L ( = V (L c ( (E d)(w w z w z w m z (m) ) (4) where m coefficiets w i s form the vector T w = [ w, w,... w m ]. Thus V L is a egative estimatio of the oise leakage. Sice the exact values of the aalog imperfectio are a priori ukow, the parameters of the digital correctio filter L C ( must be adaptively cotrolled. The addig of a dither i frot of the.5-bit quatizer behaves similarly to the quatizatio oise. Sice the dither sigal d s follows the same parasitic leakage path toward the output as the quatizatio oise e, removig the dither sigal from the output a W

6 6 Je-Shiu Chiag et al. requires the same operatio as removig the quatizatio oise e from the output. I other words, the miimizatio of the dither sigal i the output is equivalet to the miimizatio of the oise leakage. Therefore addig a dither sigal also ca reduce the toe i the base bad [8]. Although, we eed a adaptive filter to maitai the system performace but as we kow, the digital circuit have lower circuit oise ad area tha aalog circuit. Therefore, it is worth to add a digital filter to maitai the whole system performace. 5. Simulatio Results Cosider the circuit specificatios of high-speed SDMs for xdsl system as expressed i Table : Table. The desired circuit specificatios of the SDM Specificatios Values Peak SNDR 8dB Dyamic Rage (DR) 8dB Modulator Order 4 Quatizer Bit 5 Oversamplig Ratio Sigal Badwidth Maximum Stable Iput.5MHz -6dB Usig the automatic high-order SDM sythesis tool (HOST) [7] that proposed by Kuo et al. to desig this SDM ca obtai the specificatios show i Table. Table. Specificatios of the sythesized FFSDM Specificatios Peak SNDR Dyamic Rage (DR) Values 86dB 88dB Modulator Order 4 Quatizer Bit 4 Oversamplig Ratio Sigal Badwidth Samplig Frequecy Maximum Stable Iput Modulator structure.5mhz 6MHz -6dB FFSDM The structure ad the correspodig modulator coefficiets are show i Figure 7 ad the output spectra are show i Figure 8. Coefficiet Value Coefficiet Value Coefficiet Value g.775 a.669 b.4 g.857 a.58 b.4958 g.7 a.669 b g4.677 a4.46 b4.667 Figure 7. The structure ad its coefficiets of a fourth-order four-bit FFSDM where Y[k] db H z ( = z The FFT of Y[] solid: ideal case@sndr=86db dot: % DAC mismatch@sndr=7db Freq Figure 8. The output spectra of FFSDM with ideal case ad DAC mismatch Accordig to Figure 8, we fid that the DAC mismatch is the most serious problem i FFSDM. Therefore, the data-weighted averagig (DWA) [8] ca be used to reduce the DAC mismatch. However, DWA may icrease the aalog circuit complexity. By usig the CFFSDM architecture, the DAC mismatch problem ca be elimiated ad oly eed to desig a digital cacellatio. The same circuit specificatios of FFSDM ca be applied to CFFSDM ad the specificatios of the sythesized CFFSDM ca be obtaied ad are show i Table,

7 Cascaded Feedforward Sigma-Delta Modulator for Wide Badwidth Applicatios 6 ad its coefficiets are show i Table 4. Table. Specificatios of the sythesized CFFSDM Specificatios Values Peak SNDR 8dB Dyamic Rage (DR) 84dB Modulator Order 4 Quatizer Bit.5 bit for feedback path 5 bit for output path Oversamplig Ratio Sigal Badwidth.5MHz Samplig Frequecy 6MHz Maximum Stable Iput -6dB Modulator structure CFFSDM Table 4. Coefficiets of the four-order five-bit CFFSDM Coefficiet Value Coefficiet Value Coefficiet Value g.9 a.9 b.8 g.6 a.6 b.8 g.5 a.5 b.8 g4. a4. b4.5 The output spectra are show i Figure 9 with coefficiet variatios ad fiite opamp gai. Accordig to Figure 9, the CFFSDM ca reduce the aalog circuit complexity effectively ad the coefficiet variatios ca be reduced by careful layout techiques. Y[k] db Y[k] db The FFT of Y[] solid: is ideal case@sndr=8db Freq (a) The FFT of Y[] % coefficiet variatio@sndr=76db Y[k] db The FFT of Y[] 6dB opamp gai@sndr=8db Freq (c) Figure 9. The output spectra of CFFSDM (a) ideal case, (b) with coefficiet variatios, ad (c) with fiite opamp gai SNDR (db) iput level (db) Figure. The SNDR plot of the CFFSDM ( : for ideal case, *: with 5% coefficiet variatios, : A dc = 6dB, x:.5-bit quatizer output) As usig the CFFSDM architecture with.5-bit quatizer i the feedback loop, the output spectra are show i Figure 9, ad Figure is the SNDR of CFFSDM with various coditios. From Figure we fid that the DAC error is elimiated, but the gai error becomes more serious due to the.5-bit quatizatio oise leakage of the output. By employig the adaptive filter ad dither sigal the simulatio result is show i Figure. The result exhibits that the SNDR icreases by several adaptive cycle times, ad fially the adaptive error-correctio process coverges to a optimum value. From Figure, we fid the SNDR of the CFFSDM with error correctio scheme is almost the same as that of the ideal case, ad Figure is the time-domai outputs of all itegrators i CFFSDM. The comparisos of the various differet architectures are showed i Table Freq (b)

8 6 Je-Shiu Chiag et al. Table 5. The comparisos of the various differet architectures Specificatios Architectures MASH - FFSDM CFFSDM Order Quatizer bit @5 OSR 6 Samplig ratio (MH SNDR with ideal case (db) SNDR with A dc =6dB (db) SNDR with % DAC mismatch (db) SNDR with % coefficiet variatio (db) SNDR (db) iput level (db) Figure. The SNDR plot of the CFFSDM ( : for ideal case, *: with 5% coefficiet variatios ad A dc = 6dB, : adaptive filter output).5 Output of st itegrator.5 Magitute time x -.5 Output of st itegrator.5 Magitute time x -

9 Cascaded Feedforward Sigma-Delta Modulator for Wide Badwidth Applicatios 6.5 Output of st itegrator.5 Magitute time x -.5 Output of 4st itegrator.5 Magitute time x - Figure. Time-domai outputs of all itegrators i CFFSDM 6. Coclusio I the covetioal wide badwidth SDM desig, people use multi-bit quatizer with multi-bit DAC to implemet the SDM. The oliearity of the multi-bit DAC causes the difficulty ad complexity of the desig ad implemetatio of the wide badwidth SDM. I the proposed CFFSDM, we use.5-bit quatizer to overcome the problems caused by the multi-bit DAC. The coarse quatizatio error caused by the.5-bit quatizer ca be cacelled by the adaptive filter with least mea square algorithm ad a dither ijectio scheme i the digital part. The simulatio shows this ew architecture is almost as good as the ideal case. The proposed architecture provides a alterative choice of easier implemetatio of the wide badwidth sigma-delta modulator. Refereces [] Cady, J. C. ad Temes, G. C., Oversamplig Delta-Sigma Data Coverters: Theory, Desig, ad Simulatio, IEEE Press, New York (99). [] Chao, K. C., Nadee, S., Lee, W. L., ad Sodii, C. G., A higher order topology for iterpolative modulators for oversamplig A/D coverter, IEEE Tras. Circuits ad Syst., Vol. 7, pp. 9-8 (99). [] Cii, D., Samori, C. ad Lacaita, A. L., Double-idex averagig: a ovel techique for dyamic elemet matchig i Sigma- Delta A/D coverters, IEEE Tras. Circuits ad Syst. II, Vol. 46, pp (999). [4] Ferguso, P. F., Gaesa, Jr. A. ad Adams, R. W., Oe bit higher order sigma-delta A/D coverters, IEEE Proc. of ISCAS, Vol., pp.

10 64 Je-Shiu Chiag et al (99). [5] Keey, J. G. ad Carley, L. R., Desig of multi-bit oise-shapig data coverters, Aalog It. Circuits Sigal Proc. Joural (Kluwer), Vol., pp (99). [6] Kiss, P., Silva, J., Wiesbauer, A., Su, T., Moo, U. -K., Stoick, J. T. ad Temes, G. C., Adaptive digital correctio of aalog errors i MASH ADCs. II. Correctio usig test-sigal ijectio, IEEE Tras. Circuits ad Syst. II, Vol. 47, pp (). [7] Kuo, T. H., Che, K. D. ad Che, J. R., Automatic coefficiets desig for high-order sigma-delta modulator, IEEE Tras. Circuit ad Syst. II, Vol. 46, pp. 6-5 (999). [8] Norsworthy, S. R., Schreier, R. ad Temes, G. C., Delta-Sigma Data Coverters: Theory Desig, ad Simulatio, IEEE Press, New York (997). [9] Nys, O. ad Hederso, R. K., A 9-bit low-power multibit sigma-delta ADC based o data weighted averagig, IEEE Joural of Solid-State Circuits, Vol., pp (997). [] Rabii, S. ad Wooley, B. A., The Desig of Low-Voltage, Low-Power Sigma-delta Modulators, Kluwer Academic Publishers, Bosto/Dordrecht/Lodo (999). [] Risbo, L., Stability predictio for high-order Σ- modulators based o quasi liear modelig, IEEE Proc. of ISCAS, pp (994). [] Schreier, R., A empirical study of high-order sigle-bit delta-sigma modulators, IEEE Tras. Circuits ad Syst. II, Vol. 4, pp (99). [] Wiesbauer, A. ad Temes, G. C., O-lie digital compesatio of aalog circuit imperfectios for cascaded Σ modulator, IEEE-CAS Regio 8 Workshop o Aalog ad Mixed IC Desig, pp (996). Mauscript Received: Ju., ad Accepted: Jul. 7,