A GHz Constant KVCO Low Phase Noise LC-VCO and an Optimized Automatic Frequency Calibrator Applied in PLL Frequency Synthesizer

Transcription

1 A GHz Costat KVCO Low Phase Noise LC-VCO ad a Optimized Automatic Frequecy Calibrator Applied i PLL Frequecy Sythesizer Hogguag Zhag, Pa Xue, Zhiliag Hog State Key Laboratory of ASIC & System Fuda Uiversity Shaghai, Chia hgzhag4@fuda.edu.c Abstract A GHz costat KVCO LC-VCO applied i PLL frequecy sythesizer is preseted i this paper. With costat KVCO LC-VCO, the frequecy sythesizer is able to obtai costat badwidth. Furthermore, the VCO has a low KVCO which will result low phase oise. A Optimized automatic frequecy calibrator (AFC) is proposed, the AFC ca select the sub-bad which is earest to middle cotrol voltage. The proposed frequecy sythesizer has bee desiged i TSMC 65 m CMOS P9M process, post-simulatio results show that the proposed LC-VCO has the characteristics of costat 60 MHz/V ad costat 6 MHz sub-bad spacig ad the post-simulatio results also valid the algorithm of the proposed AFC. Keywords-Phase Lock Loop(PLL); Frequecy Sythesizer; Voltage Cotrolled Oscillator (VCO); Automatic Frequecy Cotrol (AFC) I. INTRODUCTION Mobile commuicatio techology plays a icreasigly importat role i moder people's livig, it chages people s way of life. Ad wireless local area etwork (WLAN), wireless metropolita area etwork (WMAN) ad wireless wide area etwork (WWAN have bee istalled aroud the world. I short, we are i the era of wireless commuicatios. Trasceiver is a importat compoet of wireless commuicatio, it ca receive ad trasmit wireless sigal, ad frequecy sythesizer is the key block which provides the local oscillator sigal for sigal up-mixed ad dowmixed coversio i wireless trasceiver. It is a bridge betwee basebad sigal ad RF sigal. I order to prevet uwated sigal ifiltrate ito the meaigful sigal, a clea clock is idispesable [], [2]. With the developmet of commuicatio, the multi-mode multi-bad commuicatio protocols becomig more ad more popular, ad these protocols eed wide frequecy rage VCO which will result a high K VCO, ad as is kow to all, K VCO is proportioal to PLL frequecy sythesizer phase oise, thus multi sub-bad i VCO is a effective method to solve this problem. The sigle frequecy-voltage curve is replaced by multi frequecy-voltage curves, this techique will decrease the K VCO. However, everythig has two sides, multi sub-bad will cause a series of problems, such as how to keep the sub-bad spacig homogeeous, how to keep the K VCO costat, ad how to selects a fit sub-bad [3], [4], [5]. PLL loop badwidth impacts the loop stability ad phase oise, ad the PLL badwidth is determied by voltage cotrol gai (K VCO ), frequecy dividig ratio ad charger pump curret. Costat K VCO ad programmable charger pump are employed to esure a costat loop badwidth. AFC is a key blocks which will work i digital coarse tuig at first, the PLL frequecy sythesizer will ever work i the desired frequecy if the AFC does ot work, so a optimized AFC is proposed to select the sub-bad. A GHz costat K VCO low phase oise LC-VCO ad a optimized automatic frequecy calibrator applied i PLL frequecy sythesizer is preseted, ad this paper is orgaized as follows. Sectio 2 describes the proposed system architecture, sectio 3 aalyzes ad implemets the circuits, ad sectio 4 illustrates the layout ad postsimulatio results. Fially, a brief coclusio is discussed i sectio 5. II. SYSTEM ARCHITECTURE The PLL frequecy sythesizer system architecture is show i Figure., the frequecy sythesizer cotais two modules, coarse tuig ad fie tuig, the coarse tuig is able to select the fit sub-bad, ad this tuig is cotrolled by mixed loop which is composed by VCO ad AFC. While the fie tuig will lock a defiitely frequecy, ad this tuig is cotrolled by aalog loop which is composed by FPD, charger pump, loop filter, VCO, divider ad DSM [], [4]. The S switches o ad S 2 switches off iitially, the coarse tuig selects the fit VCO sub-bad, the S switcher off ad S 2 switches o to start the fie tuig. Figure. System architecture of PLL frequecy sythesizer

2 The output frequecy of PLL frequecy sythesizer is ot costat, ad the relatioship betwee the output frequecy ad referece crystal frequecy is show i Eq. (). While N.S is the dividig ratio. they work regio is colored by red. The VCCA is cotrolled by V ctrl which is a cotiuously variable, the voltage rages from 0.7 V to. V, ad they work regio is colored by blue. Freoutput = N. S Freref () The N.S usually has a large variable percet, ad the percet is especial large i ultra-wide bad (UWB) trasceiver. Ad VCO is the key compoet which has the characteristic that the output frequecy is cotrolled by voltage. As metioed above, the PLL frequecy sythesizer phase oise is proportioal to K VCO, so multi sub-bad is employed to lower the K VCO. Figure.2 illustrates this pheomeo [4], [6]. (a) (b) Figure.2 Frequecy-Voltage Curve. (a) sigle bad (b) multi sub-bad III. ANALYSIS AND IMPLEMENTATION OF CIRCUITS A. Voltage Cotrolled Oscillator VCO is the key compoet i PLL frequecy sythesizer, for the out-of-bad phase oise, frequecy rage ad power dissipatio all have a closely relatioship to the performace of VCO, a cross couple wide bad low phase oise VCO is preseted, the VCO has PMOS cross couple pairs ad NMOS cross couple pairs, the curret reuse method is employed i this desig, so the VCO is easy to oscillate with low curret dissipatio. However the double MOS pairs will deteriorate the voltage headroom of output sigal, thus we cut the commo curret tails [3], [6]. The VCO frequecy rages from 4.6 GHz to 5.6 GHz, i order to decrease the K VCO, the bad is divided ito 64 sub bads. The VCO frequecy is determied by iductor ad capacitor, as is show i Eq. (2). f = (2) 2π LC For iductor value is hard to modify, so tuig VCO frequecy by chagig capacitor is a commo method, the proposed VCO capacitor is composed by fixed capacitor, digital cotrolled capacitor array (DCCA) ad voltage cotrolled capacitor array. The fixed capacitors are MIM capacitor, ad the DCCA ad VCCA are PMOS trasistors which work i iversio regio. These MOS trasistors CV curve is illustrated i Figure.3. The capacitor is icreasig with the icreasig of cotrolled voltage, ad the DCCA is cotrolled by digital sigal, the voltage is 0 V either or.2v, Figure.3 PMOS capacitor versus cotrolled voltage The proposed VCO, the VCCA uit ad the DCCA uit are illustrated i Figure.4. I VCCA uit, whe NB<0> is low, the PMOS trasistor gate voltage is almost equal to V ctrl, whe NB<0> is high, the PMOS trasistor gate voltage is 0, which will result a low value capacitor. I order to obtai a costat K VCO ad costat sub-bad spacig, the DCCA ad VCCA are utilized thermometer codig. Although there are oly oe V ctrl ad 6-bit DCCA cotrol word, the VCCA ad DCCA are divided i 64 uits. Furthermore, the PMOS trasistors size are ever same, they are optimized by proposed algorithm. Figure.4 VCO architecture ad VCCA, DCCA uit

3 The DCCA has 64 uits, ad they are valued C D, a C D, a 2 C D, a 3 C D, a 62 C D, a 63 C D. Ad the VCCA also has 64 uits, they are valued C V, b C V, b 2 C V, b 3 C V, b 62 C V, b 63 C V. So the capacitor of the sub bads are show i Eq. (3). whe the V ctrl is i the middle of cotrolled voltage [7], [8]. C + C + ( b + b + b + + b ) C + C = fixed D V V, middle 2 3 5,mi Cfixed + ( + a+ a2 + + a 2 + a ) CD + ( b + b b63 ) CV = + ( ) V, middle,mi C b b b C =2,3,4 63 C + ( + a+ a2 + + a63) C + ( + b+ + b63 ) CV =64 fixed D, middle (3) The C fix is the fixed capacitor, ad C D is the DCCA capacitor, C V,mi is the miimum capacitor of VCCA whe the cotrol voltage is equal to 0, ad C v,middle is the VCCA capacitor whe the cotrol voltage is equal to V ctrl. The K VCO is the frequecy gai of the uit voltage, it is show i Eq. (4). C V 3, middle f 4 ctrl VCO, π LC V VCO, = = + b + b2 + b3 + b CV 3, middle 4π LC V ctrl K = =2,3,4 64 The a ad b are determied by PMOS trasistor size, they are obtaied by the followig method. ) Set the maximum frequecy f H miimum frequecy f L, sub-bad umber ad iductace. The ceter frequecy of every bad is preseted i Eq. (5). fh = fh fl fceter, = fl + =2,3,4 63 (5) fl =64 2) Get the K VCO, i order to avoid the sub-bad discotiuous, the overlap ratio is set to 50%, ad the K VCO is show i Eq. (6). Ad the capacitors of every subbad, the are preseted i Eq. (7). K VCO f f f f = = 2 ( 50%) H L H L Ctot = (7) 2 4π Lf The Eq. (4) ca be solved by Eq. (5), Eq. (6) ad Eq. (7). Thus the parameter b, b 2, ad b are obtaied. 3) Get C V,mi ad C V, middle by simulatio, ad solve the Eq. (3). The the parameter a, a 2, ad a are obtaied. I this way, a costat K VCO, costat sub-bad spacig VCO is esured. PLL loop badwidth selectio is very importat, because small loop badwidth will cause slow respose, ad large loop badwidth will dissipate too much power ad cause the udesired oise. Ad the badwidth of PLL frequecy sythesizer with typical 3 rd loop filter is show i Eq. (8). IcpKVCO RC BW = (8) 2π N C+ C2 + C3 As metioed above, the PLL has a wide rage of frequecy usually, so the N will be chaged with the variatio of frequecy, ad the resistor ad capacitors of loop filter are fixed, furthermore, K VCO is costat by the proposed method. I order to esure the loop badwidth fixed, charger pump curret should be proportioal to (4) (6) frequecy divider ratio N. so programmable multi-curret charger pump is employed. B. Automatic Frequecy Calibrator The AFC priciple is explaied as followig, the VCO is coutig durig the time of p cycle of referece clock, ad VCO couter is compared with the umber that which is p times of the referece frequecy. The referece clock F ref is divide by p, this time is a cout uit time T ctr, the relatio betwee T ctr ad the T ref is show i Eq. (9). T ctr = p T (9) ref O the oe had, p is a iteger umber, T ref is the period of the referece clock, the VCO output sigal positive edge is couted durig the time of T ctr, ad the N ctrl is the couter result. O the other had, the target frequecy is determied by the frequecy divisio ratio N.F ad referece frequecy, ad the flow diagram is illustrated i Figure.5. A compariso is made betwee N ctrl ad N dec, ad δ is the differece. The the sub-bad of the VCO is moved up or dow based o this differece [8], [9]. Figure.5 Architecture of AFC The core idea of this priciple is that whe the PLL frequecy is locked, the output frequecy f vco is equal to the referece frequecy f ref multiply the frequecy ratio N.F, the i the p T ref time, the target frequecy cout should be close to p N.F. It should be oted that the decoded value N dec should be a iteger, so p is multiplied by the value of.f should be a iteger greater tha. Ad.F is i biary, thus the value of p is a iteger power of 2. Figure.6 shows the AFC compariso digit. Figure.6 AFC compariso digit Theoretically, i order to guard the least sigificat bit (LSB) ca be detected, ad there will be o residual error. The p should be greater tha 2 24, this will result a extremely log coutig time. So a compromise is made i this desig, oly the 4 highest Sigificat Bit (MSB) is utilized, ad p is desired to be the iteger 6. The rest of the fractioal part of

4 the compositio of the residual error, thus the maximum residual error of 2-4 f ref, the residual error is reduced to oesixth compared with the traditioal structure. AFC work flow chart is show i Figure.7, biary search algorithm is utilized to reduce the umber of compariso. I the first compariso, the VCO output clock f vco is couted durig time T ctr, the couter value N ctr is compared with the decoded value N dec, ad the sub-bad of the voltagecotrolled oscillator is moved accordig to the positive ad egative polarity of δ, ad the absolute differece δ is stored, the differece betwee the secod cout value ad the decoded value δ2 is compared with δ, ad the smaller value of the two umber is stored as δ mi. The AFC will compare the curret differece δ with the previous differece δ mi i every cycle, ad the smaller of the two umber is stored as δ mi [7], [9]. Figure.9 descripts the timig diagram of AFC, the AFC has 8-step, ad every step cotai rst, cout, hold, read, compare ad shift bad sigal, these operatio will cosume 800 s, ad thus the AFC cosume 6.4us ly. Figure.9 Diagram of AFC compariso timig The digital frequecy divider is biary divider, ad ripple carry couter is applied. There are two DFF type i the proposed couter, TSPC logic DFF is employed to process the high frequecy sigal, ad the master-slave latch DFF replaces the TSPC to avoid leakage i slow clock, as show i Figure.0. Figure. 7 Diagram of AFC algorithm The curret differece δ is always compared with the miimum of all previous comparisos. I fact δ is a umber that determies the differece betwee the ceter frequecy of the curret sub-bad ad the target frequecy. The smaller of δ, the closer the ceter frequecy of the curret sub-bad is to the target frequecy. At the same time, if the curret δ value is less tha or equal to, the compariso process is termiated ad the AFC operatio is eded. This is because the asychroous cout will brig the frequecy cout error, δ value less tha or equal to has exceeded the coutig accuracy. I the worst case, the AFC setup time TAFC is equal to (K-) T ctr accordig to the traditioal biary search algorithm, as show i Figure.8. Figure.0 Diagram of AFC high speed couter The AFC diagram is illustrated i Figure., the AFC couter is desig by full custom, ad the digital algorithm is accomplished by half custom. Figure. Diagram of AFC IV LAYOUT AND POST-SIMULATION RESULTS The proposed low oise costat K VCO ad costat subbad spacig LC-VCO has bee desiged i TSMC 65 m CMOS P9M process. The chip layout is show i figure.2, ad the chip area is 456umx268um without test pads, Figure. 8 Diagram of AFC operatio Figure.2 Layout of VCO

5 Table makes a compariso betwee the post-simulatio results ad the recetly reported VCO, it is obviously that the proposed VCO phase oise is very low. Figure.3 Layout of VCO Figure.3 shows the LC-VCO frequecy-voltage curve, as illustrated i the figure, the sub-bad K VCO is costat ad the spacig of sub-bad is costat, these cofirms the effect of the proposed LC-VCO. The K VCO is 60 MHz/V, ad the subbad spacig is 6 MHz. TABLE I. PERFORMANCE COMPARISON (MHZ OFFSET) [] [4] [5] This work Process (m) m f c (GHz) Tuig rage (GHz) Phase oise (dbc/hz) Power (mw) V CONCLUSIONS A GHz costat K VCO low phase oise LC-VCO ad a optimized automatic frequecy calibrator applied i PLL frequecy sythesizer is preseted i this paper. With the proposed thermometer DCCA ad VCCA methods, the VCO achieves the feature of costat K VCO ad costat subbad spacig. The proposed optimize AFC ca select the bad whose ceter frequecy is earest to the desired frequecy. The LC-VCO ad AFC has bee desig i TSMC 65 m CMOS P9M process, the post-simulatio results cofirm the effect of the proposed VCO ad AFC. REFERENCES Figure.4 Phase oise of the LC-VCO Figure.4 descripts the LC-VCO phase oise curve, the VCO output sigal frequecy is 4.8 GHz, ad the phase oise is -26.8dBc/Hz at MHz offset, ad -05dBc/Hz at 00 khz offset. This VCO phase oise is very low for the low K VCO techique is proposed. Figure.5 Operatio of AFC Figure.32 shows the digital simulatio of AFC, the AFC utilize biary successive approximately method to obtai the best cotrol word, the post-simulatio result cofirms that the propose AFC ca work. [] Li Jia, Yeug Bu Choi ad Woo Ga Yeoh, "A 5.8-GHz VCO with Precisio Gai Cotrol," IEEE RFIC, pp , 3-5 (2007) [2] Ozawa S, Yamamoto S. PLL frequecy sythesizer: U.S. Patet 8,53,990[P] [3] Shi J, Shi H. A GHz fractioal-n PLL frequecy sythesizer with fast auto calibratio of loop badwidth ad VCO frequecy[j]. Solid-State Circuits, IEEE Joural of, 202, 47(3): [4] Li Ji; Zhiqu Li, Zhigog Wag ad Wei Li, "A fully itegrated low phase oise VCO for IEEE 802.a WLAN trasceivers i 0.8μm CMOS," ICSICT, pp , (2008) [5] D. Shi, J. East ad M.P. Fly, "A Compact 5GHz Stadig-Wave Resoator-based VCO i 0.3μm CMOS," IEEE RFIC, pp , 3-5 (2007 [6] Luo J, Zhag L, et al. A 24GHz low power ad low phase oise PLL frequecy sythesizer with costat KVCO for 60GHz wireless applicatios[c] Circuits ad Systems, Iteratioal Symposium o. IEEE, 205: [7] Rhee W. Phase-locked frequecy sythesis ad modulatio for moder wireless trasceivers[c] Custom Itegrated Circuits Coferece (CICC), 205 IEEE. IEEE, 205: -75. [8] Pa Y, Che H, Shao K, et al. A 6-GHz low-phase-oise voltagecotrolled oscillator[c] IEEE Iteratioal Coferece o Solid-State ad Itegrated Circuit Techology. IEEE, 200: [9] Lu L, Gog Z, et al. A 975-to-960MHz fast-lockig fractioal-n sythesizer with adaptive badwidth cotrol ad 4/4.5 prescaler for digital TV tuers[c] IEEE Iteratioal Solid-State Circuits Coferece. IEEE, 2009: ,397a.