A 1.2V High Band-Width Analog Multiplier in 0.18µm CMOS Technology

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1 Iteratioal Review of Electrical Egieerig (I.R.E.E.), Vol. 5, N. March-pril 00.V High Bad-Width alog Multiplier i 0.8µm CMOS Techology mir Ebrahimi, Hossei Miar Naimi bstract alog multiplier is a importat buildig block for may aalog computatioal applicatios. I this paper, a ew compact, low power structure ad low voltage CMOS aalog multiplier is proposed. The proposed structure icorporates a cross-coupled squarer circuit. The most importat features of this topology are low power cosumptio ad high bad-width that makes it suitable for use i high fruecy applicatios. ll of these are implemeted usig a compact circuit. The circuit is desiged ad aalyzed i 0.8µm CMOS process model ad the key features like badwidth ad THD are extracted. Simulatio results for the circuit with a.v sigle supply show a very low power cosumptio ad better bad-width with respect to comparable structures. Copyright 00 raise Worthy rize S.r.l. - ll rights reserved. eywords: CMOS alog Multiplier, Four Quadrat, Cross-Coupled Squarer Circuit B C OX C DB C GD C GS C SB C DBp C GSp Nomeclature Iput DC bias voltage. MOS gate oxide capacitace per uit area. Drai-to-bulk capacitor i NMOS trasistors. Gate-to-drai capacitor i NMOS trasistors. Gate-to-source capacitor i NMOS trasistors. Source-to-bulk capacitor i NMOS trasistors. Drai-to-bulk capacitor i MOS trasistors. Gate-to-source capacitor i MOS trasistors. Tras-coductace parameter of MOS trasistor. NMOS tras-coductace parameter. MOS tras-coductace parameter. L Chael legth of MOS trasistor. R sx() NMOS velocity saturatio resistor. R sx(p) MOS velocity saturatio resistor. V DD Supply voltage. V GS MOS gate-to-source voltage. V SB MOS source-to-bulk voltage. V t MOS threshold voltage. V T0 MOS threshold voltage i zero bias coditio. V T NMOS threshold voltage. V T MOS threshold voltage. W MOS chael width. MOS body effect coefficiet., Mismatch terms for threshold voltage of trasistors. MOS velocity saturatio parameter. (0-7 /tox)v - I. Itroductio Todays by the advaces i commuicatio ad sigal processig systems, power cosumptio, power supply ad badwidth become critical problems i circuit desig. alog multipliers are importat buildig blocks for aalog sigal processig applicatios such as modulatio, oscillators, phase fruecy detectio, fuzzy itegrated systems[]-[9].the multiplier performs a liear product of cotiuous sigals x ad y yieldig a output z xy i which is a costat with suitable dimesio[]. Differet structures for optimizig differet features have bee proposed for aalog multipliers. Some of these features are: operatig speed, power cosumptio, supply voltage, badwidth ad etc. s we kow, there are may tradeoffs betwee differet performace features; ehacig oe degrades some others. The previous topologies for multipliers have differet approaches i implemetatio. Oe of these approaches is usig trasistors i triode regio [], [8]. The circuit of [] suffers from oliearity. The mai drawback of [8] is the large umber of trasistors i the implemeted circuit. The domiat approach is usig trasistors i saturatio especially for widebad applicatios [3]. s aother classificatio, multipliers may be implemeted i curret mode or voltage mode. I [4] a curret mode multiplier is proposed for high speed applicatios i which for each multiplicad, say x, the circuit eeds a additioal iput of x. Buildig precise x is ot always possible, so this makes the circuit more complicated ad iserts additioal error. I [3] ad [5] two voltage mode multipliers are proposed ad as a drawback both eed two differet power supply. Usig flipped voltage followers, some proposed circuits miimized the power supply [3], [7]. Mauscript received ad revised March 00, accepted pril 00 Copyright 00 raise Worthy rize S.r.l. - ll rights reserved 803

2 Figs.. Sub-circuit. roposed multiplier circuit. Oe of the good features of our proposed topology is its simplicity ad compact structure. Furthermore, it is desiged with sigle low voltage supply. We will aalyze this topology i ext sectios. The rest of this paper is orgaized as follows. Sectio II explais the desig tred ad structure of the multiplier. Sectio III is about characteristics ad performace aalysis of the multiplier. Sectio IV explais secod order effects o the circuit performace. Simulatio results ad comparisos are preseted i sectio V ad fially sectio VI gives the coclusios. II. Desig Tred I our proposed circuit, all of the trasistors operate i saturatio regio. s we kow, the behavior of MOS trasistor i this regio ca be described as (): D GS t I V V () II.. Sub-Circuit Cosider the circuit i Fig..a. I this stacked structure, I O ca be calculated from the followig uatios: IO ID I Dp () VGS B Y (3) VGSp X (4) Cosuetly, I D ad I Dp ca be writte as: I B Y V (5) D T I X V (6) Dp T From (5), (6) ad () we have: X VT B Y V T (7) Equatio (7) ca be reduced to (8) ad (9): X VT B Y V T (8) B Y V X V T T (9) Substitutig (9) i (5) or (6), I O ca be writte as the followig closed form uatio: I Y X B V V O T T II.. Multiplyig (0) The fuctio of the proposed circuit is based o the followig mathematical relatios: Z Y X D Y X D () Z Y X D Y X D () Where, D is a offset costat. Subtractig Z by Z leads to uatio (3). Z Z Z XY (3) d 8 ssumig as (4), we ca express the braches currets of Fig. as follows: (4) I Y X B V V (5) W T T I Y X B V V (6) W T T Copyright 00 raise Worthy rize S.r.l. - ll rights reserved Iteratioal Review of Electrical Egieerig, Vol. 5, N. 804

3 I Y X B V V (7) W 3 T T I Y X B V V (8) W 4 T T CL uatios at odes V O ad V O are as follows: B- V i(max) >V T + V Tp (9) Cosiderig B=V DD the maximum ual magitude of X ad Y is as (30): V V V V i(max) < DD T Tp (30) IO IW I W (9) III. alysis ad Evaluatios IO IW3 I W4 (0) V O ad V O ca be expressed by the uatios bellow: VO VDD RI O () VO V DD RI O () Cosuetly, the differetial output V od is ual to: Vod VO VO R IO I O (3) Substitutig (9),(0) ad (5)-(8) i (3) ad regardig to uatios ()-(4) results i (4): V 8RXY (4) Od Equatio (4) shows the multiplyig ature of the circuit obviously. ssumig small values for X ad Y from Fig., the bias coditio for the proposed circuit is as (5): B V V (5) T Equatio (6) shows the coditio that keeps the trasistors i saturatio regio: DD Tp T T Tp V R B V V B V (6) ssumig B=V DD cacels the eed for additioal referece voltage B. ssumig this, (6) ca be reduced to (7): R VDD VTp VT V T (7) other coditio that may restrict the iput rage occurs whe X has its maximum value ad Y has its miimum value. Cosiderig this, the values of X ad Y for which the trasistors are ON must satisfy the iuality of (8): B X Y V V (8) For ual amplitude of X ad Y, the above coditio is summarized to (9). T T III.. ower Dissipatio Oe of the most importat factors for circuit desig is power dissipatio show i (3): VI (3) Where, V is the supply voltage ad I is the total curret. From (3), we ca decrease the power cosumptio by decreasig the power supply voltage or the total curret. To perform this ad cosiderig (6), we selected B(=V DD ) close to V T V Tp. Choosig such a low value of V DD restricts the allowable values for R (Trasistors should be all i saturatio). See coditios (6) ad (7) i previous sectio.the total curret of the circuit is: ITOT IW IW IW3 I W4 (3) Now, static power cosumptio of the circuit ca be foud from the followig uatio (X=Y=0): V B V V (33) 4 Static DD T Tp s uatio (33) shows, choosig B=V DD alog with small eough V DD ( VDD VT V T ), the power dissipatio will be decreased. Decreasig power dissipatio this way, restricts allowable amplitude of X ad Y, (30) shows this tradeoff clearly. III.. Bad-Width Oe of the most importat performace measures of multiplier circuit is the badwidth. High badwidth is the mai advatage of the proposed circuit over the competitive structures. Because of two iputs of the circuit, two differet trasfer fuctios may be defied that leave two values for the badwidth. s depicted i Figs. the trasfer fuctio for X iput is differet from Y iput. For X iput a source follower ad a commo gate stage are i series but for Y iput we have a commo source stage with source resistor. To aalyze the fruecy respose related to each of the two iputs, computig the fruecy respose for oe of the V O or V O is sufficiet. Now for X iput cosider the circuit i Fig.. I this circuit: CO CDB CGD C C C C GS SB DBp (34) Copyright 00 raise Worthy rize S.r.l. - ll rights reserved Iteratioal Review of Electrical Egieerig, Vol. 5, N. 805

4 Figs.. C uivalet circuit for X iput. C uivalet circuit for Y iput I (34) C is the total capacitace at ode ( ), ot cosiderig the C GSp, ad C O is the total capacitace at outputs. s metioed before, the trasistors have small currets so, the chael legth modulatio ca be simply igored. Igorig chael legth modulatio effect V O ad are isolated odes ad we ca estimate related pole of ode V O as: O (35) RC O I order to compute the pole at ode we ca write: V C S g GS m Y C C g g GS m mp Therefore, for the Y iput we have: p R CO CGD R CDB CGD (4) (4) To compute the pole at od we ca write: V C GSpS gmp X C C S g g GSp m mp s a result, by a good precisio we have: p RC R C C p O GD DB g g g g m mp m mp C C C C C C GSp GS SB GSp DBp (36) (37) (38) p g g g g m mp m mp C C C C C C GS GS SB GSp DBp (43) From (37), (38), (4) ad (43) at first review, it seems that badwidth for X ad Y iputs are the same, but we did ot cosider the effect of zeros i our calculatios. Cosiderig this effect the result may be differet. To calculate the zero fruecy i Fig. we assumed that V O is grouded by I O =0 (show by dashed lie) assumig this, we have: g V g V 0 (44) m GS m Based o (37) ad (38), depedig o the size of trasistors ad value of the resistor, each of the p or p may be domiat. But for widebad desig the trasistors are biased i larger g m so usually p is domiat. I order to aalyze the fruecy respose with respect to the Y iput, cosider the circuit i Fig.. I this case we have: CO CDB (39) C C C C GSp DBp SB Igorig chael legth modulatio ad applyig Miller estimatio [0] for C GD we get: O R C O C GD (40) From (44) it will be foud that V =0. Writig CL at ode we get: V C S g GSp mp C C S g g GSp m mp Z X g C mp GSp (45) (46) To compute the zero fruecy i Fig., at the same maer of X, we assume that V O is grouded with I O =0, it yields: CGDSY gm Y V (47) Writig CL at ode we get: Copyright 00 raise Worthy rize S.r.l. - ll rights reserved Iteratioal Review of Electrical Egieerig, Vol. 5, N. 806

5 CGSS gm V Y (48) C C S g g GS m mp Substitutig (48) i (47) we get: body-effect caot be caceled i this way. I Fig. circuit, body-effect will be appeared i N-N4. To aalyze this effect let s assume that: VTN V TN, VTN 3 V TN 4 (53) g m gmp CGD CGD C CGS S S g C g m g mp 0 I (49) we have: m gm gmp CGD gmc C C C Z Y Z Y GD GS (49) (50) Where ad are mismatch terms for the threshold voltage of trasistors. Substitutig (53) i (5) ad (6) ad igorig terms cotaiig, we get: So: ' Out Out I I X Y ' Out Out I I X Y (54) V R X Y (55) error ssumig Z Y Z(Y) << Z(Y) we get: C C C GD GS g g C g C m m GD m (5) Where Z(Y) is the domiat zero. From (46) ad (5) oe will foud that the domiat zero of the Y iput is smaller tha domiat zero of the X iput. If this zero locates ear the domiat pole this causes to appearace of overshot i fruecy respose ad damage flat parts of trasfer fuctio that somehow ca be cosidered as decreasig i badwidth. This effect is show i our simulatios. IV. Secod-Order Effects Equatio () describes the MOS trasistor operatio i saturatio regio i its ideal behavior but i practice there are some secod-order effects that make it differet from square-law uatio. These effects are: body effect, mobility reductio, chael legth modulatio ad trasistor mismatches. These effects lead to appearace of higher harmoics or amplitude ad offset errors i the output. We will aalyze these secod-order effects i this sectio respectively. s it ca be see, this mismatch leads to appearace of X ad Y harmoics i the output. IV.. Error Due to Tras-Coductace Mismatch I Fig. we assumed that NMOS trasistors (N-N4) ad also MOS trasistors (-4) are completely idetical. I this ideal coditio, the output will be described as (4). But i practice there are some fabricatio errors that cause to tras-coductace mismatch. ssumig that the maximum fabricatio error is. x where is a costat coefficiet ad x ca be or p. I the worst case we ca write: d: N,N, N3,N4 (56),, 3,4 (57) I this coditio, I W ca be writte as: I W d I W3 ca be writte as: T Y X B V V T (58) IV.. Body Effect I MOS trasistors by icreasig source-bulk voltage V SB, threshold voltage of the trasistor will be icreased by the followig uatio [0]: I W3 T Y X B V V T (59) VT VT0 f V SB f (5) Most of itegrated circuits are fabricated o - substrate ad MOS trasistors are situated i -wells. Therefore, by coectig bulk to the source, this effect ca be caceled i MOS trasistors. But, i NMOS trasistors, because of the same bulk for all NMOSs, we caot coect bulk to the source ad V SB 0. Therefore, I W ad I W4 ca be writte at the same maer. ssumig ( D B VT V Tp ) ad eglectig the term we ca write: Vod R Y X D 4RXY (60) Copyright 00 raise Worthy rize S.r.l. - ll rights reserved Iteratioal Review of Electrical Egieerig, Vol. 5, N. 807

6 First term i (60) shows the udesirable harmoics ad the secod term shows the error i output magitude. Usig MCLORIN series ad eglectig the terms cotaiig (=, 3, ),(60) ca be rewritte as: Therefore, velocity saturatio leads to the appearace of higher order harmoics i the output ad also it affects the output amplitude. TBLE I RMETERS FOR CIRCUIT IN FIG. V od R 8RXY Y X D (6) From (6) we ca see that the amplitude error is egligible ad error due to udesirable harmoics is very small because Y, X, D ad have very small values ( X,Y,D, ). IV.3. Error Due to Velocity Saturatio other importat o-ideal effect is the velocity saturatio that exists i sub-micro devices ad causes to carrier mobility reductio. It has bee show i [] that the effect of velocity saturatio ca be modeled as a fiite series resistat i source of the trasistors. From [] value of this resistat is give by: R sx Cosiderig this effect, we ca rewrite () as: D GS T x D (6) I V V RI (63) Calculatig I D from (63) ad usig MCLORIN series [] we get: 3 D GS T sx GS T 4 5 Rsx VGS VT I V V R V V (64) If we apply this uatio for CMOS pairs i our proposed circuit ad assumig R =R sx() +R sx(p) ad (B- V T - V Tp =D) we ca rewrite (5) as: V. Simulatio Results I order to verify the circuit operatio ad characteristics several experimetal simulatios have bee carried out usig dvaced Desig System simulator by the TSMC 0.8µm RF CMOS process model. Trasistors dimesios ad other parameters of the circuit i Fig. are listed i Table I. I sectio 3, we aalyzed the miimum iput rage of the multiplier. s we kow, icreasig the iput sigals magitude leads to icrease i oliear effect of the trasistors. s a result, liearity error of the circuit ad also the output THD may icrease. Fig. 3 shows the THD ad liearity error with respect to the iput sigal amplitude. s it ca be see i this figure, liearity error ad THD are icreasig by icrease i iput sigal amplitude. O the other had, iput rage is a fuctio of iput DC bias voltage (30) ad we choose B=V DD, by a larger bias voltage we have a larger voltage supply ad also larger total curret amouts ad this causes to a larger power cosumptio. 3 X Y D X Y D IW R 5 R X Y D 4 (65) Equatios (6)-(8) ca also be rewritte at the same maer. Usig (9)-(3), the differetial output voltage will be ual to: V ' Od R 6 DR 5 D R R X Y XY XY (66) V error RR 6D 5D XY X Y XY (67) Figs. 3. Total harmoic distortio as a fuctio of iput sigal amplitude. Liearity error as a fuctio of iput sigal amplitude Copyright 00 raise Worthy rize S.r.l. - ll rights reserved Iteratioal Review of Electrical Egieerig, Vol. 5, N. 808

7 Fig. 4. ower cosumptio as a fuctio of DC bias voltage (V DD) Fig. 4 Shows power cosumptio as a fuctio of DC bias voltage. Fruecy respose of the proposed circuit is show i Fig. 5. s metioed i bad-width aalysis, trasfer fuctio with respect to the Y iput has a zero ear to domiat pole, it leads to the appearace of overshot i fruecy respose, ad this is show i simulated C respose i Fig. 5.b. lso, from (4),(5) it ca be foud that domiat pole for Y iput is fuctio of R but domiat zero is ot, therefore by choosig larger amouts of R, domiat pole will be far from the domiat zero ad this causes to elimiate overshot, this pheomeo is illustrated i Fig. 6. s it is show i secod order ad o-ideal effects, body effect leads to the appearace of X ad Y harmoics i the output. This error is plotted with respect to the X d amplitude whe Y d is sweepig i Fig. 7. s it ca be see, this error has a liear relatio with the iputs ad it cofirms (55). Fig. 6. Fruecy respose of multiplier with respect to Y iput whe R is sweepig from -4 Fig. 7. Error due to body effect as a fuctio of Xd whe Yd is kept costat Figs. 5. Fruecy respose of multiplier With respect to the X iput. With respect to the Y iput Figs. 8. dditio THD due to tras-coductace mismatch. Output offset error due to tras-coductace mismatch O the other had, it is show i secod order effects that the tras-coductace mismatch leads to the appearace of additioal harmoics ad also DC offset error i the output (6). Fig. 8 shows the additioal Copyright 00 raise Worthy rize S.r.l. - ll rights reserved Iteratioal Review of Electrical Egieerig, Vol. 5, N. 809

8 harmoic distortio respect to tras-coductace mismatch coefficiet ad DC offset error respect to tras-coductace mismatch is show i Fig. 8. DC trasfer characteristics of the proposed multiplier is show i Fig. 9. Time domai respose of the circuit whe it multiplies two sigals (X d =0.4V p-p GHz, Y d =0.4V p-p 00MHz) siusoidal wave-forms is show i Fig. 0 ad FFT of the output voltage is show i Fig. 0. VI. Coclusio useful implemetatio of aalog multiplier which is well desiged for short chael techology has bee described. Simulated results show its better performace with respect to the similar structures. This structure is desiged with sigle low voltage supply ad has better bad-width with a relatively good liearity ad THD. O the other had, by well tuig its supply voltage ad trasistors dimesios we ca achieve higher liearity ad lower THD with relatively lower bad-width. Its compact structure makes it suitable for use i aalog VLSI systems. Comparisos betwee our proposed topology ad the other oes are listed i Table II. TBLE II COMRISONS BETWEEN ROOSED MULTILIER ND THE OTHERS Fig. 9. DC trasfer characteristics of multiplier Figs. 0. Circuit multiplies two siusoidal sigals (X d: GHz 0.4V - ad Y d: 00MHz 0.4V -). Time domai respose of circuit. Output FFT s it is show i secod order effects, velocity 3 3 saturatio leads to appearace of X Y, XY harmoics i the output voltage (67), this pheomeo is show i Fig. 0 which leads to appearace of.3ghz, 0.7GHz, 3.GHz,.9GHz fruecies. We ca see clearly that the maximum distortio peak is 34.dB below the desired compoets. Refereces [] C. Che ad Z. Li, Low-power CMOS alog multiplier, IEEE Tra. Circuit Syst. II, vol. 5, o. 9, Feb. 006, pp []. Demostheous ad M. aovic, Low-voltage MOS Liear Trascoductor/Squarer ad four quadrat multiplier for aalog VLSI, IEEE Tra. Circuit Syst. I, vol.5, o.90, Sept. 005, pp [3] C. Sawigu ad J. Mahattaakul,.5V wide Iput Rage, High Bad-width, CMOS Four-Quadrat alog Multiplier, I roc.008 IEEE It. Symp. Circuits Syst., May 008, pp [4]. Naderi,. hoei ad h. Hadidi, High Speed Low ower Four-Quadrat CMOS Curret-Mode Multiplier, 4 th IEEE cof Circuit Syst., 007 ICECS, pp [5] M. umger, ad. Dejha, Versatile Dual-Mode Class-B Four quadrat alog Multiplier, Iteratioal joural of sigal processig vol. umber ISSN , 005. [6] C. Sawigu,. Demostheous, Compact Low-Voltage CMOS Four-Quadrat alogue multiplier, Electro. Lett., vol.4, pp 49-50, Sept 006. [7] C. Sawigu,. Demostheous ad D. al, Low-Voltage, Low-ower, High-Liearity CMOS Four-Quadrat alog multiplier, IEEE 8 th Europea cof o Circuit theory ad desig. ug 007, pp [8]. rommee, M. Somduyakaok,. gkaeo,. Jodtag ad. Drjha, Sigle Low-Supply ad Low Distortio CMOS alog Multiplier, IEEE It. Symp. Commuicatio ad iformatio Tech, Oct 005, pp [9] S. Sigh ad. Radhakrisha Rao, Low voltage alogue Multiplier, IEEE sia acific cof Circuit Syst. Dec006, pp [0] B. Razavi, Desig of alog CMOS Itegrated Circuits. New York: MacGraw-Hill, 000. []. R. Gray,. J. Hurst, S. H. Lewis, ad R. G. Meyer, alysis ad Desig of alog Itegrated Circuits, 4 th ed. New York: Willy, 00. []. Bult ad H. Walliga, CMOS Four-Quadrat alog Multiplier, IEEE Joural of Solid-State Circuits, vol., o. 6, pp , Ju [3] S. I. Liu, Low-Voltage CMOS Four-Quadrat Multiplier, Electro. Lett., vol. 30, o. 5, pp. 5-6, Dec.994. [4] C. J. Deboo, F. Maloberti ad J. Micallef, O the Desig of Low-Voltage, Low-ower CMOS alog Multiplier for RF plicatios, IEEE Tras. O VLSI Systems, vol. 0, o., pr. 00, pp Copyright 00 raise Worthy rize S.r.l. - ll rights reserved Iteratioal Review of Electrical Egieerig, Vol. 5, N. 80

9 [5] J. Ramirez-gulo et al., Low-Voltage CMOS alog Four- Quadrat Multiplier Based o Flipped Voltage Followers, I roceedigs IEEE ISCS 004. vol., pp , 004. [6] S. Y. Hsiao ad C. Y. Wu, arallel Structure for CMOS Four- Quadrat alog Multipliers ad its pplicatio to -GHz RF Dow Coversio Mixer, IEEE Joural of Solid State Circuits, vol. 33, o. 6, Ju. 998, pp [7] Mehrvars, H. R. Chee Yee wok, Novel Multi-Iput Floatig-Gate MOS Four-Quadrat alog Multiplier, IEEE Joural of Solid State Circuits, vol. 3, o.8, ug. 996, pp [8] She-Iua Liu ad Yuh-Shya Hwag, CMOS Squarer ad Four-Quadrat Multiplier, IEEE Tras. Circuits ad Systems I, vol. 4, o., Feb. 995, pp. 9-. [9] Ho-Ju Sog ad Choog-i im, MOS Four-Quadrat alog Multiplier Usig Simple Two-Iput Squarig Circuits with Source Followers, IEEE Joural of Solid State Circuits, vol. 5, o. 3, Ju. 990, pp [0]. L. Coba ad. E. lle, Low-Voltage, Four-Quadrat, alogue CMOS Multiplier, Electro. Lett., vol.30, o. 3, Ju. 994, pp [] Zhehua Wag, CMOS Four-Quadrat alogue Multiplier with Sigle-Eded Voltage Output ad Improved Temperature erformace, IEEE Joural of Solid State Circuits, vol. 6, o. 9, Sept. 99, pp uthors iformatio Itegrated circuits Research Lab (ICRL), Electrical ad computer Egieerig Departmet, Babol Uiversity of techology, Babol, Mazadara, Ira. (a.ebrahimi@stu.it.ac.ir) Babol Uiversity of Techology, Babol, Mazadara, Ira. (h_miare@it.ac.ir) mir Ebrahimi was bor i Babol, Ira, o September 0, 986. He received the B.Sc. i electrical ad computer egieerig from Uiversity of Mazadara, Babol, Ira, i 008. He is curretly pursuig M.Sc. studet i electroic egieerig at Babol Uiversity of Techology, Babol, Mazadara, Ira ad is with the itegrated circuits Research Laboratory (ICRL), Babol Uiversity of Techology. His research iterests are desig of high-purity CMOS oscillators, mixed aalog-digital itegrated circuits focus o phase locked loops ad CMOS RF circuits for wireless commuicatios. He works as a reviewer of a ISI joural Hossei Miar-Naimi received the B.Sc. from Sharif Uiversity of Techology i 994 ad M.Sc. from Tarbiat Modares Uiversity i 996 ad h.d. from Ira Uiversity of Sciece ad Techology i 00 respectively. Sice 003 He has bee member of Electrical ad Electroics Egieerig Faculty of Babol Uiversity of Techology. His research iterests are aalog CMOS itegrated circuit desig, RF microelectroics, Image processig ad Evolutioal algorithm. Copyright 00 raise Worthy rize S.r.l. - ll rights reserved Iteratioal Review of Electrical Egieerig, Vol. 5, N. 8

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