A New Basic Unit for Cascaded Multilevel Inverters with the Capability of Reducing the Number of Switches

Transcription

1 Joural of Power Electroics, ol, o, pp , July 67 JPE I(Prit: 98-9 / I(Olie: 9-78 A ew Basic Uit for Cascaded Multi Iverters with the Capability of Reducig the umber of witches ara Laali *, Ebrahim Babaei, ad Mohammad Bagher Baae harifia * * Faculty of Electrical ad Computer Egieerig, Uiversity of Tabriz, Tabriz, Ira Abstract I this paper, a ew basic uit is proposed The, a cascaded multi iverter basded o the series coectio of umber of these ew basic uits is proposed I order to geerate all of the voltage s (eve ad odd at the output, three differet algorithms to determie the magitude of the voltage are proposed Reductios i the umber of power es, driver circuits ad voltage s i additio to icreases i the umbr of output voltage s are some of the advatages of the proposed cascaded multi iverter These results are obtaied through a compariso of the proposed iverter ad its algorithms with a H-bridge cascaded multi iverter from the poit of view of the umber of power electroic devices Fially, the capability of the proposed topology with its proposed algorithms i geeratig all of the voltage s is verified through experimetal results o a laboratorary prototype of a 9- iverter Key words: H-Bridge Cascaded Multi Iverter, Multi Iverters, ew Basic Uit I ITRODUCTIO Multi iverters have received more attetio whe compared with traditioal two iverters There are three mai topologies ad several derivatio topologies for multi iverters The mai topologies are the diode-clamped multi iverters, flyig capacitor multi iverters ad cascaded multi iverters [], [] The cascaded multi iverter has received special attetio due to its modularity, simplicity of cotrol, reliability ad lower power electroic devices for the geeratio a specific output voltage []-[6] Cascaded multi iverters are maily classified ito two groups: symmetric cascaded multi iverters ad asymmetric cascaded multi iverters [] I the symmetric cascaded multi iverters the magitudes of all of the voltage s are equal, which results i a higher umber of isulated gate bipolar trasistors (s, power diodes ad voltage s to geerate a high umber of output s These features lead to icreases i terms of the istallatio Mauscript received Ja, ; accepted Apr 9, Recommeded for publicatio by Associate Editor Rae-Youg Kim Correspodig Author: e-babaei@tabrizuacir Tel: , Fax: , Uiversity of Tabriz * Faculty of Electrical ad Computer Egieerig, Uiversity of Tabriz, Ira KIPE space ad total cost of the iverter These are the mai disadvatages of the symmetric cascaded multi iverters while the same value for all of the voltage s are their most sigificat advatage Two symmetric cascaded multi iverters have bee preseted i [7], [8] A H-bridge cascaded multi iverter has bee preseted i [9] I [9], two differet algorithms have bee preseted which leads to symmetric ad asymmetric topologies Asymmetric cascaded multi iverters have bee preseted i several studies i order to icrease the umber of output voltage s I asymmetric topologies, the magitudes of the voltage s are uequal Therefore, there are differet algorithms to determie the value of the voltage s I [], [] two other algorithms of asymmetric topologies have bee preseted for H-bridge cascaded multi iverters I additio, two other topologies for asymmetric cascaded multi iverters have bee preseted i [] ad [] The major advatage of the asymmetric cascaded topology is a cosiderable icrease i the umber of output voltage s by usig a low umber of voltage s ad power es However, high variability i the magitude of the voltage s is their most remarkable disadvatage I this paper, a cascaded multi iverter based o a ew basic uit is proposed This iverter icreases the

2 67 Joural of Power Electroics, ol, o, July v o TABLE I THE OUTPUT OLTAGE OF THE PROPOED BAIC UIT BAED O DIFFERET WITCHIG PATTER tate 6 v o 6 Fig The proposed basic uit umber of output voltage s by usig a miimum umber of power es, driver circuits ad voltage s The, three differet algorithms to geerate all of the voltage s are proposed These advatages are cofirmed by a compariso the proposed iverter ad its algorithms with a H-bridge cascaded multi iverter Fially, experimetal results obtaied from a 9- iverter cofirm the correct performace of the proposed topology i geeratig all of the voltage s II PROPOED TOPOLOGY The ew proposed basic uit is show i Fig As Fig shows, the proposed basic uit cosists of two voltage s, two bidirectioal es ( ad ad four uidirectioal es (,, ad 6 from voltage poit of view The bidirectioal es coduct curret ad voltage i two directio while the uidirectioal es coduct curret i two directios ad block voltage i oe directio I additio, each uidirectioal cosists of a with a ati-parallel power diode ad a driver circuit However, the bidirectioal es iclude two s with two ati-parallel power diodes ad a driver circuits if a with a commo emitter cofiguratio is used Therefore, the umber of driver circuits for the bidirectioal es is as same as the uidirectioal es i the proposed basic uit Accordig to Fig, the es ( ad, ( ad, ( ad, ( ad, ( ad 6 ad ( ad 6 should ot be tured o simultaeously, because a short-circuit across the voltage s will be produced Table I shows the output voltage s of the proposed uit based o differet ig patters I this Table, ad idicate the o ad off states of the es, respectively As show i Table I, the proposed basic uit is able to geerate seve voltage s (three positive s, three egative s ad oe zero at the output It is also obvious that this basic uit is able to geerate all of the positive ad egative voltage s at the output A ew cascaded multi iverter ca be made by a series coectio of umber of basic uits This ew proposed cascaded multi iverter is show i Fig The ( ( +,,,,,,, 6,,,,,,,, 6, Fig eries coectio of umber of the basic uit output voltage of the proposed iverter is equal to addig the output voltage of each uit ad it ca be writte as follows: v ( t = v ( t + v ( t + L + v ( t ( o o, o, o, where is the umber of series coected basic uits I the proposed cascaded multi iverter, the umber of es (, s (, driver circuits ( driver ad voltage s ( are calculated as follows: driver v o, v o, v o = 6 ( = 8 ( = 6 ( = (

3 A ew Basic Uit for Cascaded Multi Iverters with 67 It is importat to ote that i the basic proposed uit determiatio the magitude of the voltage s has the most sigificat ifluece i icreasig the umber of geerated output voltage s It also iflueces the use of power electroic devices ad so the amout of istallatio space ad the total cost of the iverter Therefore, to geerate all of the voltage s, three differet algorithms to determie the value of the used voltage s will be proposed, =, = (6 = for j = L (7 j -, j,,,, j j = - (8 I this coditio, the umber of output voltage s ad the maximum magitude of the output voltage are writte as follows: + = - (9 A First Proposed Algorithm ( P I this sub-sectio, the amplitude of the two used voltage i the basic uits is writte as follows: + æ - ö = ç è ø ( First uit: th uit: = (6, = (7, - = + åå (8, i, j i = j = = (9,, I this algorithm, the umber of output voltage s ( ad the maximum amplitude of the producible output voltage ( are equal to: 7 = ( æ 7 -ö = ç è ø B ecod Proposed Algorithm ( P ( I the secod proposed algorithm, the magitudes of the voltage s are determied as follows: = (, j - j = (, j j Cosiderig this proposed algorithm, the umber of output voltage s ad the maximum magitude of the output voltage are calculated as follows: C Third Proposed Algorithm ( P + = ( - ( = ( - ( I this sub-sectio, the values of the voltage s are selected as follows: III COMPARIG THE PROPOED GEERAL TOPOLOGY WITH THE H-BRIDGE TOPOLOGY The most importat aim of itroducig the ew-cascaded multi iverter ad its proposed algorithms is icreasig the umber of output voltage s while usig fewer power electroic devices such as es, s, power diodes, driver circuits ad so o I this sectio, a compariso betwee the proposed topology ad its algorithms with a H-bridge cascaded multi iverter is doe to ivestigate the advatages ad disadvatages of the proposed cascaded iverter The proposed topology based o the first, secod ad third proposed algorithms are cosidered as P - P i this ivestigatio, respectively I [9], a H-bridge cascaded multi iverter ad two differet algorithms have bee preseted Oe of them is kow as the symmetric cascaded iverter ( = = = L = = while the other oe is kow as the asymmetric cascaded iverter ( =, = L, = - I this compariso, these two differet algorithms are cosidered as R ad R, respectively I order to icrease the umber of output voltage s while usig a miimum of H-bridges, two other algorithms were preseted i [-] They are cosidered by R - R i this compariso ( R for =, = = L = = ad R for =, = = L = = Fig idicates the H-bridge cascaded multi iverter Fig compares the umber of power electroic es i the proposed cascaded multi iverter based o its proposed algorithms with the H-bridge cascaded iverter As show i this figure, the umber of power es required i the proposed cascaded iverter based o the first proposed algorithm is lower tha the H-bridge cascaded iverter I additio, this proposed algorithm has eve better performace tha other preseted algorithms for the proposed topology

4 67 Joural of Power Electroics, ol, o, July, + v o - Fig The H-bridge cascaded multi iverter 6 or 8 driver,,,, i o Fig ariatio of, or driver versus As metioed before ad based o the power es used i the proposed topology ad the H-bridge cascaded iverter, the umber of power es i the proposed cascaded multi iverter is equal to the umber of driver circuits As a result, this topology eeds fewer driver circuits tha the H-bridge cascaded iverter Due to the use of bidirectioal es i the proposed topology, it is ecessary to compare the umber of required s i this topology with that of the H-bridge cascaded multi iverter This compariso is show i Fig As this figure shows, the proposed cascaded topology based o the first proposed algorithm uses fewer s tha the H-bridge cascaded iverter However, uidirectioal es are oly used i the cascaded multi iverter The first proposed algorithm also has the best performace amog the other proposed algorithms i terms of the umber of required s As metioed before, the umber of power diodes is equal to the umber of s As a result, the umber of power diodes i the proposed iverter is lower tha the H-bridge cascaded iverter Fig 6 compares the umber of voltage s i the proposed topology with that of the H-bridge cascaded multi iverter It ca be see that the umber of used voltage s i the proposed topology, especially the oe based o the first proposed algorithm, is lower tha the H-bridge cascaded iverter ad the other preseted algorithms for the proposed topology Table II shows a compariso of the value of the blocked voltage o the power es, s ad driver circuits of the proposed topology with that of the H-bridge cascaded iverter It ca be see that the value of the blocked voltage o the s depeds etirely o the magitude of the used voltage s,, R, R R R P, 6 8 P P,, Fig ariatio of Fig 6 ariatio of 6 8 versus versus TABLE II THE COMPARIO OF THE BLOCKED OLTAGE O I THE PROPOED TOPOLOGY AD CACADED MULTILEEL IERTER Topology Algorithms block H-bridge cascaded iverter Proposed topology P P P Preseted i [9] (symmetric Preseted i [9] (asymmetric Preseted i [] (asymmetric Preseted i [] (asymmetric First proposed algorithm ( P ecod proposed algorithm ( P Third proposed algorithm ( P ( - ( - ( - 8 (7-6 ( - (8 - As the above comparisos idicates, the lower umber of required power electroic es, driver circuits, s, power diodes ad voltage is the most importat advatage of the proposed cascaded multi iverter This results i reductios i the istallatio space ad total cost of the iverter R R R R 6 R 8 R R R P P 6 8 P

5 A ew Basic Uit for Cascaded Multi Iverters with 67 I EXPERIMETAL REULT The correct performace of the proposed cascaded multi iverter i the geeratio of all of the voltage s at the output is verified through experimetal results o a 9- iverter based o the basic proposed uit ad show Fig This iverter cosists of two basic uits, four voltage s, four bidirectioal es ad eight uidirectioal es The magitude of the voltage s are determied by usig the first proposed algorithm Therefore, by assumig that the value of, =, the amplitudes of the voltage s i the first ad secod uits based o (7, (8 ad (9 are equal to, =, =, ad, =, respectively Accordig to, 7 ( ad ( this iverter is able to geerate 9 s (twety-four positive s, twety-four egative s ad oe zero with a maximum amplitude of at the output It is importat to ote that the s used i the prototype are HGTPCID (with a iteral ati-parallel diode A 89C microcotroller by ATMEL Compay has bee used to geerate all of the ig patters The coected load to the iverter is cosidered to be a resistive-iductive load with values of R = 6W ad L = mh I this paper, the fudametal frequecy ig cotrol method is used The mai reaso for selectig this cotrol method is its low ig frequecy whe compared with other cotrol methods This i tur leads to reductios i the ig losses The experimetal output voltage waveforms of the first ad secod uits are show i Fig 7(a ad Fig 7(b, respectively As these figues show, each uit is able to geerat a step waveform with pasitive ad egative amplitudes I additio, the maximum amplitude of the output voltage i each uit is equal to addig the magitude of the used voltage surces Moreover, the experimetal output voltage ad curret waveforms are idicated i Fig 8 As it is obvious from Fig 8, this iverter geerates 9 s with a maximum amplitude of ad 87A at the output I additio, the step geerated output voltage waveform cosists of all of the pasitive ad egative voltage s ad looks like a siosuidal waveform There are two differeces betwee the voltage ad curret waveforms The curret waveform looks more like a siosuidal waveform tha the voltage waveform I additio, there is a phase shift betwee the voltage ad the curret These differeces are due to the resistive-iductive load feature, which acts as a low pass filter As metioed before, the basic proposed uit cosists of two bidirectioal es ad four uidirectioal es from a voltage poit of view I order to ivestigate these facts i the proposed cascaded multi iverter, the blocked voltages o each of the first basic uit are (a (b Fig 7 The output voltages (a First bridge (b ecod bridge Fig 8 oltage ad curret output waveforms show i Fig 9 It is poited out that all of the obtaied results are based o the first proposed algorithm Fig 9(a, 9(b, 9(c ad 9(d show the blocked voltages o es,,,,, ad 6, ms ms ms ma, respectively As show i Figs 9(a ad 9(b, the values of the blocked voltages o es, ad, are or, depedig o the ig patter Moreover, Fig 9(c ad 9(d show that the blocked voltages o es, ad 6, are either or It is clear that the magitudes of the blocked voltage o the es are either positive or zero, so there is ot a egative amout o them I additio, the amout of blocked voltage is equal to the sum of the magitudes of the used voltage s i the first basic uit As a result, the existece of four uidirectioal es is recofirmed i the proposed cascaded multi iverter Fig 9(e ad Fig 9(f show the blocked voltages by es, ad,, respectively As show i these figures, the values of the blocked voltages are either or, depedig o the ig patter

6 676 Joural of Power Electroics, ol, o, July ms (a ms (f Fig 9 The blocked voltage o the power es i the first basic uit; (a, ; (b, ; (c, ; (d 6, ; (e, ; (f, Moreover, there are positive ad egative amout of voltages o the power es This fact verifies that es, ms (b ad, are bidirectioal It is importat to ote that these values deped directly o the cosidered algorithm to determie the magitude of the voltage s By chagig the selected algorithms these magitudes will be differet but their positive ad egative values will be the same COCLUIO ms ms (c (d I this paper, a ew basic uit for cascaded multi iverters is proposed The, three differet algorithms to determie the magitude of the voltage s are proposed Comparisos betwee a H-bridge cascaded multi iverter ad the proposed iverter show the sigificat advatages of the proposed topology i terms of the umber of es, driver cicuits, s, power diodes ad voltage s I additio, it is determied that the first proposed algorithm has the best performace from all of the proposed algorithms ad the H-bridge cascaded iverter O the other had, if it is ecessary to geerate a miimum of 9 s at the output, the proposed topology based o the first proposed algorithm ad equatios ( to ( eeds =, = 6, = ad = Driver However, uder the same coditios, the H-bridge cascaded iverter based o the biary method show by R requires = = Driver = ad = 6 Fially, i order to verify the capability of the proposed cascaded iverter i the geeratio of all of the voltage s, experimetal results o a 9- iverter are used ms (e REFERECE [] F Carielutti, H Piheiro, ad C Rech, Geeralized carrier-based modulatio strategy for cascaded multi

7 A ew Basic Uit for Cascaded Multi Iverters with 677 coverters operatig uder fault coditios, IEEE Tras Id Electro, ol 9, o, pp , Feb [] E Babaei, Charge balace cotrol methods for a class of fudametal frequecy modulated asymmetric cascaded multi iverters, Joural of Power Electroics, ol, o 6, pp 8-88, ov [] E Babaei, Optimal topologies for cascaded sub-multi coverters, Joural of Power Electroics, ol, o, pp -6, May [] J Ebrahimi, E Babaei, ad GB Gharehpetia, A ew topology of cascaded multi coverters with reduced umber of compoets for high-voltage applicatios, IEEE Tras Power Electro, ol 6, o, pp 9-, ov [] J apoles, A J Watso, ad J J Padilla, elective harmoic mitigatio techique for cascaded H-bridge coverter with oequal lik voltages, IEEE Tras Id Electro, ol 6, o, pp 96-97, May [6] X he, AQ Huag, T Zhao, ad G Wag, Couplig effect reductio of a voltage-balacig cotroller i sigle-phase cascaded multi coverters, IEEE Tras Power Electro, ol 7, o 8, pp -, Aug [7] WK Choi ad F Kag, H-bridge based multi iverter usig PWM ig fuctio, i Proc ITELEC, pp -, 9 [8] G Waltrich ad I Barbi, Three-phase cascaded multi iverter usig power cells with two iverter legs i series IEEE Tras Id Appl, ol 7, o 8, pp 6-6, Aug [9] M Majrekar, ad T A Lipo, A hybrid multi iverter topology for drive applicatio, i Proc APEC, pp -9, 998 [] E Babaei ad H Hosseii, Charge balace cotrol methods for asymmetrical cascaded multi coverters, i Proc ICEM, pp 7-79, 7 [] Laali, K Abbaszadeh, ad H Lesai, A ew algorithm to determie the magitudes of voltage s i asymmetrical cascaded multi coverters capable of usig charge balace cotrol methods, i Proc ICEM, pp 6-6, [] Alilu, E Babaei, ad B Mozafari, A ew geeral topology for multi iverters based o developed H-bridge, i Proc PEDTC, ara Laali was bor i Tehra, Ira, i 98 he received her B degree i Electroics Egieerig from the Islamic Azad Uiversity, Tabriz Brach, Tabriz, Ira, i 8, ad her M degree i Electrical Egieerig from the Islamic Azad Uiversity, outh Tehra Brach, Tehra, Ira, i I, she joied the Departmet of Electrical Egieerig, Adiba Higher Educatio Istitute, Garmsar, Ira he is presetly pursuig her PhD degree i Electrical Egieerig with the faculty of Electrical ad Computer Egieerig, Uiversity of Tabriz, Tabriz, Ira Her curret research iterests iclude the aalysis ad cotrol of power electroic coverters, multi coverters, ad FACT devices Ebrahim Babaei was bor i Ahar, Ira, i 97 He received his B ad M degrees i Electrical Egieerig from the Departmet of Egieerig, Uiversity of Tabriz, Tabriz, Ira, i 99 ad, respectively, graduatig with first class hoors He received his PhD degree i Electrical Egieerig from the Departmet of Electrical ad Computer Egieerig, Uiversity of Tabriz, i 7 I, he joied the Faculty of Electrical ad Computer Egieerig, Uiversity of Tabriz He was a Assistat Professor from 7 to ad has bee a Associate Professor sice He is the author of more tha 8 joural ad coferece papers He also holds 6 patets i the area of power electroics ad has more applicatios pedig Dr Babaei has bee the Editor-i-Chief of the Joural of Electrical Egieerig of the Uiversity of Tabriz, sice I, he was the recipiet of the Best Researcher Award from of the Uiversity of Tabirz His curret research iterests iclude the aalysis ad cotrol of power electroic coverters ad their applicatios, power system trasiets, ad power system dyamics Mohammad Bagher Baae harifia was bor i Tabriz, Ira, i 96 He received his B ad M degrees i Electrical Egieerig from the Departmet of Egieerig, Uiversity of Tabriz, Tabriz, Ira, i 989 ad 99, respectively I 99, he joied the Faculty of Electrical ad Computer Egieerig, Uiversity of Tabriz He received his PhD degree i Electrical Egieerig from the Departmet of Electrical ad Computer Egieerig, Uiversity of Tabriz, i He was a Assistat Professor from to, a Associate Professor from to 9 ad has bee a Professor sice 9 His research iterests iclude desig, modelig ad aalysis of electrical machies, trasformers, lier electric motors, ad electric ad hybrid electric vehicle drives