SETTLING-TIME-ORIENTED DESIGN PROCEDURE FOR TWO-STAGE AMPLIFIERS WITH CURRENT-BUFFER MILLER COMPENSATION

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1 SETTING-TIME-ORIENTED DESIGN PROCEDURE FOR TWO-STAGE AMPIFIERS WITH CURRENT-BUFFER MIER COMPENSATION ANDREA PUGIESE, 1 FRANCESCO AMOROSO, 1 GREGORIO CAPPUCCINO, 1 GIUSEPPE COCORUO 1 Key words: Operatioal amplifiers, Settlig time. A ovel desig procedure for two-stage operatioal amplifiers (op-amps) with curretbuffer Miller compesatio (CBMC) is proposed. The method is based o equatios which relate both bias curret ad aspect ratio of trasistors to the mai amplifier parameters. The importat iovatio of the procedure is the defiitio of a systematic strategy to achieve the desired settlig time by performig the op-amp dyamic behaviour optimizatio, which is badly eeded i high-performace discrete-time applicatios. To prove the effectiveess of the proposed approach, a desig example of a CBMC op-amp i 0.35 µm CMOS techology is preseted. 1. INTRODUCTION Two-stage operatioal amplifier (op-amp) cofiguratios are widely employed, because they allow a suitable trade-off amog the dc gai, speed, ad output swig characteristics. As is kow, a opportue frequecy compesatio etwork is required to guaratee the closed-loop stability i two-stage topologies. The curret-buffer Miller compesatio (CBMC) techique is oe of the most popular approaches, owig to its beefits with respect to the other compesatio schemes [1-3]. Desig procedures for CBMC amplifiers were preseted i the past 0[4, 5]. Oe of the most importat objectives of the approaches i [4, 5] is the gaibadwidth-product (GBW) ehacemet by meas of opportue choices of the opamp parameters. However, owig to the third-order settlig behaviour of CBMC op-amps [2, 3, 5] the GBW maximizatio does ot correspod to the settlig time miimizatio for the desired output respose accuracy level [6, 7]. Ufortuately, the settlig performace optimizatio is istead a essetial aspect i desigig op- 1 Departmet of Electroics, Computer Sciece ad Systems Uiversity of Calabria Via P. Bucci, 42C, Rede (CS), Italy {a.pugliese, f.amoroso, g.cappuccio, g.cocorullo}@deis.uical.it Rev. Roum. Sci. Tech. Électrotech. et Éerg., 54, 4, p , Bucarest, 2009

2 376 Adrea Pugliese et al. 2 amps for discrete-time applicatios such as switched-capacitor (SC) circuits, above all i order to avoid system power wastig [6]. Therefore, a ad-hoc approach has to be idetified whe the amplifier settlig time is oe of the mai desig cocers. To the best of the authors kowledge, a complete settlig-time-based desig procedure for CBMC op-amps is ot available i the literature. Actually, a systematic criterio to reach the optimizatio of the CBMC amplifier settlig performaces by properly sizig the compesatio etwork has recetly bee preseted i [7]. As demostrated by the exhaustive aalysis reported i [7], this criterio allows sigificat improvemets o the op-amp settlig-time/powercosumptio ratio with respect to covetioal GBW-orieted approaches, eve i the presece of parametric variatios. Startig from the settlig time miimizatio strategy i [7], a complete desig procedure for CBMC op-amps is preseted i this paper. The proposed approach is based o well-defied rules which relate the bias curret ad the aspect ratio of each trasistor to the mai amplifier parameters, developed to take also settlig time specificatio ito accout. Before eterig ito details of the desig methodology, a set of rules to cotrol the amplifier speed performaces is itroduced i Sectio 2. The desig procedure is the preseted i Sectio 3 ad applied to the desig of a CBMC op-amp i 0.35 µm CMOS techology, i Sectio 4. Fially, some coclusios are reported i Sectio DESIGN RUES FOR CBMC SPEED PERFORMANCES The typical fully-differetial two-stage CBMC op-amp is depicted i Fig. 1. MOSFETs M1-M5 ad M6-M7/M8-M9 implemet the differetial ad the commo-source stages, respectively. M10-M11 implemet the curret buffers which are biased by the curret I b. C C is the compesatio capacitor ad C 0, C are the total lumped output capacitaces to be drive by the first ad the secod stage, respectively. The closed-loop speed performaces of the amplifier deped o both slewig ad liear settlig characteristics. The former ca be roughly imposed by exploitig quite simple early-desig rules. As a first-order approximatio, the opamp slew rate (SR) is ideed determied by the miimum betwee the first (SR 1 ) ad secod stage (SR 2 ) slew rates, which are simply expressed as follows [8]: 2I SR, 1,2 1 = (1) CC 2I7,9 SR 2 =, C + C C (2)

3 3 Settlig-time-orieted desig procedure for two-stage amplifiers 377 where I 1,2 ad I 7,9 are the bias currets of M 1,2 ad M 7,9, respectively. Istead, the liear settlig characteristics are related to the amplifier parameters accordig to a more complex relatioship. I fact, the closed-loop behaviour of the amplifier i Fig. 1 is well-described by the followig third-order trasfer fuctio [2, 7]: CC G0 1+ s gmb Gs () =. C C 1 f C0 2 CCC0C s + ( CC + C) s + s f gm 1,2 g mb fgm 1,2gm7,9 fgm 1,2gm7,9gmb (3) Fig. 1 Fully differetial two-stage amplifier with curret-buffer Miller compesatio. I (3), g m1,2, g m7,9 ad g mb are the trascoductaces of M 1,2, M 7,9 ad M 10,11, respectively, f is the feedback factor which models the feedback etwork i typical applicatios, ad G 0 is the closed-loop dc gai. The trasfer fuctio (3) has, i geeral, oe real pole p 1, two complex-poles characterized by a atural frequecy ω ad a dampig factor ζ, ad oe HP zero z 1. As discussed i [7], a systematic strategy for the settlig performaces optimizatio of (3) ca be idetified by itroducig the ormalized time T=ζω t, ζω ad t beig the real part of the closed-loop complex poles ad the time variable, respectively. By idicatig p1 with ρ = the ormalized real pole, t S ad T S = ζω t S the absolute ad the ζω ormalized liear settlig times, respectively, the followig expressios for t S, C C ad g mb arise uder the typically verified hypothesis that C C is sufficietly smaller tha C [7]:

4 378 Adrea Pugliese et al. 4 t S = ζ T S ρ C fg 0 m1,2 C g m 7,9, (4) 2(1 + 2ρζ + ρ ζ ) m1,2 CC = C0 m7,9 C ( ρ + 2) ζ ρ( ρ + 2) g f g, (5) g mb = 1+ 2ρζ + ρ ζ ρ f gm 1,2. (6) The settlig performace optimizatio is carried out by performig umerical simulatios to determie the values of ρ ad ζ which miimize T S for the desired output respose accuracy level [7]. Thus, (4) (6) ca be profitably used to size the two op-amp stages ad the compesatio etwork i order to reach the desired liear settlig time by meas of a optimized dyamics. 3. PROPOSED DESIGN PROCEDURE The desig procedure will be developed by takig the specificatios o the oise, the liear settlig time, the slew rate, the iput commo rage ad the output swig ito accout. Other amplifier characteristics such as the dc gai, the powersupply ad the commo-mode rejectio ratios are extremely difficult to predict by calculatios, because of their strog depedece o the trasistor output resistaces. Therefore, they ca be evaluated oly by performig circuit simulatios based o complex trasistor models ad caot be simply icluded i a early-desig procedure [4]. To fix both the aspect ratio ad the bias curret of the trasistors, the followig first-order relatioships amog the trascoductace W g m, the aspect ratio, the drai curret I, the process trascoductace K ad the saturatio voltage V DSAT of a geeric MOSFET M i the saturatio regio will be exploited: W 2 m g =, 2K I (7)

5 5 Settlig-time-orieted desig procedure for two-stage amplifiers 379 V DSAT 2 I K W =. (8) The proposed methodology starts from the oise specificatio. The cotributio of the flicker (1/f) oise at low frequecies, which ca be ayway reduced by usig large iput devices, will be eglected i the procedure [4], thus oly the thermal oise is cosidered. The followig equatio relates the trascoductaces of the amplifier first-stage trasistors to the thermal oise [4]: 2 16 KT g = + m3,4 E ( f ) 1, (9) 3 g m1,2 gm 1, 2 where E 2 (f), g m3,4, K ad T are the iput-referred thermal oise power spectral desity, the trascoductace of MOSFETs M 3,4, the Boltzma costat ad the absolute temperature, respectively. Equatio (9) uivocally fixes the value of g m1,2 o the basis of the required value of E 2 (f) whe g m3,4 is eglected 0[4] or is chose as a assiged fractio h (h<1) of g m1,2, for the sake of simplicity: 16 KT gm = ( 1+ h). 1,2 2 (10) 3 E ( f ) Oce g m1,2 is determied, g m7,9 is set o the basis of the required liear settlig time. I fact, the followig relatioship arises from (4): g m7,9 2 T S 1 C0C = tsζ 2 fg 1+ ρ m1,2. (11) Startig from the chose values for g m1,2 ad g m7,9, the compesatio etwork is the sized accordig to (5) ad (6). It is clear that the parasitic capacitaces of amplifier trasistors determie the value of C 0. Moreover, they also affect the values of C ad f. Sice the parasitics are ukow i the early-desig phase, reasoable estimatios for C 0, C ad f, have to be used i (5), (6) ad (11) to carry out a first evaluatio for C C, g mb ad g m7,9. If eeded, the latter parameters ca the be properly adjusted after a first sizig of op-amp trasistors, by cosiderig the actual parasitic capacitace values resultig from circuit simulatios. The bias currets of M 1,2 ad M 7,9 are chose from (1) ad (2) to meet the slew rate requiremet. As a first choice, SR 1 = SR 2 ca be set. The aspect ratios of M 1,2, M 3,4 ad M 7,9 are the determied accordig to (7).

6 380 Adrea Pugliese et al. 6 To complete the procedure, the specificatios o the output swig ad the commo mode iput rage are also cotemplated. The sigle-eded positive (OSW + ) ad egative (OSW ) output swigs are give by: OSW + = V DD V DSAT 7,9, (12) OSW = V SS + V DSAT 6,8. (13) respectively. Accordig to (7) ad (8), V DSAT7,9 is ot a idepedet parameter whe I 7,9 ad g m7,9 are already set to meet the slew rate ad liear settlig requiremets. This meas that if the costrait o the positive output swig (12) is ot satisfied, the values of I 7,9 ad g m7,9 have to be opportuely recalculated. Equatios (8) ad (13) are istead used to determie the aspect ratio of the NMOS M 6,8. The egative (CMR ) ad positive (CMR + ) commo-mode iput voltages are: CMR = V + V + V + V SS DSAT1,2 TN DSAT 5, (14) + CMR = V V 3, 4 + V, (15) DD where V DS3,4 ad V TN are the drai-source voltage of M 3,4 ad the NMOS threshold voltage, respectively. From (8) ad (14), M 5 is sized o the basis of the required value of V DSAT5, V DSAT1,2 beig fixed by I 1,2 ad g m1,2. The value of V DS3,4 i (15) is istead determied by the sizig of M 3,4, arisig from the imposed value for g m3,4. Moreover, V DS3,4 caot be easily predicted by calculatios, as istead occurs i the sigle-eded amplifier cofiguratio 0 [4]. As a cosequece, if circuit simulatios show that the specificatio o CMR + is ot satisfied, the aspect ratio of M 3,4 has to be corrected ad the above desig steps have to be retraced. As previously discussed, accurate circuit simulatios are also iescapable i order to estimate the trasistor chael legths required to reach adequate output resistace values for the two amplifier stages. I this sceario, the proposed welldefied desig procedure allows a aware ad focused use of simulatios, avoidig blid trial-ad-error processes which ca result i poor performaces ad excessive desig time. The proposed desig flow is summarized i Fig. 2. DS TN 4. DESIGN EXAMPE To prove the effectiveess of the proposed desig approach, the CBMC opamp i Fig. 1 was desiged i a commercial 0.35 µm CMOS techology. The amplifier was employed i the uity-gai capacitive buffer of Fig. 3 [10]. I the

7 7 Settlig-time-orieted desig procedure for two-stage amplifiers 381 circuit, C IN models the op-amp iput capacitace ad C EXT represets the exteral load capacitace. g m1,2, g m3,4 (10) E (f) (W /) 1,2,, (W /) 3,4, (W /) 7,9 g m7,9 (11) C C, g mb (5), (6) t S (W/) 6,8 (13) OSW I 1,2, I 7,9 (1), (2) SR (W /) 5 (14) CMR Fig. 2 Proposed desig flow. Fig. 3 Uity-gai capacitive buffer. I this case, the feedback factor f ad the total op-amp output capacitace C are CF CF f = ad ( CI + CIN C ) = CEXT +, respectively [9]. CF + CI + CIN CF + CI + CIN C I = 1 pf, C F = 1 pf ad C EXT = 10 pf were assumed. The desig was carried out to meet the specificatios summarized i Table 1.

8 382 Adrea Pugliese et al. 8 Table 1 Mai amplifier parameters Parameter Specificatio Simulated DC gai 80 db 80 db t + - S / t S (0.1% Accuracy level) 15 s 14.8 s SR 60 V/µs 60 V/µs E T = 300 K 15V / Hz 14V / Hz OSW=OSW + -OSW - >1.5 V 2 V CMR=CMR + -CMR - >1 V 1.1 V GBW _ 58 MHz Phase Margi 3.3 V mw From umerical simulatios 0 [7], ρ = 1.05, ζ = 0.73 ad T SS = 4.73 result, for a desired 0.1% output accuracy level. By exploitig the proposed procedure, the followig values of the mai amplifier parameters were obtaied: g m1,2 =150 µa/v, g m3,4 = 50 µa/v, g m7,9 = 1005µA/V, I 1,2 = 13 µa, I 7,9 = 360 µa, C C = 0.35 pf ad g mb = 380 µa/v. The amplifier trasistors are sized as summarized i Table 2. Table 2 Amplifier MOSFET dimesios MOSFET M 1,2 M 3,4 M 5 M 6,8 M 7,9 M 10,11 W/ (µm) 7/1 10/4 15/2 50/2 25/0.5 5/0.35 The exact parasitic capacitor values, obtaied from HSPICE circuit simulatios, are C 0 = pf ad C IN = 0.03 pf. Simulatio results are reported i Table 1. As is oticeable, the positive/egative step 0.1% settlig time is very close to the target value of 15 s. The amplifier respose for a 300 mv amplitude step is portrayed i Fig. 4. The above example has demostrated the usefuless of the proposed desig methodology i order to properly size both CBMC amplifier stages ad compesatio etwork whe the time respose optimizatio is oe of the mai cocers.

9 9 Settlig-time-orieted desig procedure for two-stage amplifiers 383 Fig mv-amplitude step respose. 5. CONCUSIONS I this paper, a ew complete desig procedure based o the systematic settlig performace optimizatio for two-stage CBMC op-amps has bee developed. Straightforward rules have bee defied i order to fix the bias curret ad the aspect ratio of op-amp trasistors o the basis of the mai desig specificatios. The effectiveess of the procedure has bee proved by the desig of a CBMC amplifier i 0.35 µm CMOS techology. Received o 9 August, 2008 REFERENCES 1. B. K. Ahuja, A Improved Frequecy Compesatio Techique for CMOS Operatioal Amplifiers, IEEE J. Solid-State Circuits, SC-18, 6, pp (1983). 2. G. Palmisao, ad G. Palumbo, A Compesatio Strategy for Two-Stage CMOS Opamps Based o Curret Buffer, IEEE Tras. o Circ. ad Syst. I: Fud. Theory Ad Appl., 44, 3, pp (1997). 3. P.J. Hurst, S.H. ewis, J. P. Keae, F. Aram, ad K.C. Dyer, Miller Compesatio Usig Curret Buffers i Fully-Differetial CMOS Two-Stage Operatioal Amplifiers, IEEE Tras. o Circ. ad Syst. I: Fud. Theory Ad Appl., 51, 2, pp (2004).

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