Transfer Functions For The Reference Clock Jitter In A Serial Link: Theory And Applications in PCI Express

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1 DesigCo 25 Leadig Edge Commuicatio Desig Coferece Trasfer Fuctios For The Referece Clock Jitter I A Serial Lik: Theory Ad Applicatios i PCI Express Mike Li, PhD Wavecrest Corporatio 1735 Techology Drive, Suite 4 Sa Jose, CA 9511 mli@wavecrest.com Gerry Talbot AMD 8 Cetral Street Boxborough, MA 1719 gerry.talbot@amd.com Ady Martwick Itel NW Gilbert Lae Portlad, OR ady.martwick@itel.com Ja Wilstrup Teradye Ic. 531 East River Road, Suite 16, Fridley, MN 55421, wilstruj@mi.teradye.com

2 Abstract Trasfer fuctios for the referece clock jitter i a serial lik such as the PCI Express 1 MHz referece clock are established for various clock ad data recovery circuits (CDRCs). I additio, mathematical iterrelatioships betwee phase, period, ad cycle-to-cycle jitter are established ad phase jitter is used with the jitter trasfer fuctio. Numerical simulatios are carried out for these trasfer fuctios. Relevat eye-closure/total jitter at a certai bit error rate (BER) level for the receiver is estimated by applyig these jitter trasfer fuctios to the measured phase jitter of the referece clock over a rage of trasfer fuctio parameters. Implicatios of this ew developmet to serial lik referece clock testig ad specificatio formulatio are discussed. Author Biography Mike Li Dr. Mike Li is curretly the Chief Techology Officer (CTO) with Wavecrest. Dr. Li pioeered jitter separatio method (Tailfit) ad DJ, RJ, ad TJ cocept ad theory formatio. He has ivolved i settig ad cotributed to stadards for jitter, oise, ad sigal itegrity for leadig serial data commuicatios, such as Fibre Chael, Gigabit Etheret, Serial ATA, ad PCI Express. Curretly he is Co-Chairma for PCI Express jitter stadard committee. Dr. Li is sittig o the techical committees for IEEE ad IEC sposored techical cofereces such as Iteratioal Test Coferece (ITC) ad Desigco ad is a costat speaker, ivited speaker, paelist, sessio ad pael chairs o the subjects of jitter/oise ad sigal itegrity. Dr. Li has more tha 1 years experieces i high-speed related measuremet istrumetatio, testig, ad aalysis/modelig algorithms/tools, with applicatios i IC, microprocessor, clock, serial data commuicatios for both electrical ad optical, ad wireless commuicatio. Prior joiig Wavecrest, Dr. Li had worked i both idustry ad academic istitutio. He has a BS i physics from Uiversity of Sciece ad Techology of Chia, a MSE i electrical egieerig ad a Ph.D. i physics from Uiversity of Alabama i Hutsville. He did his Post Dr. at Uiversity of Califoria, Berkeley ad worked there as a research scietist o high-eergy astrophysics before he joied idustry. Dr Li has published more tha 4 papers i refereed techical jourals, holds 2 patet ad has 7 patets pedig. Ady Martwick Mr. Martwick is a circuit architect at Itel Corporatio s chipset divisio. He authored sectios of the 3GIO physical layer specificatio ad co-chairs the PCI Express jitter workgroup. He has over 2 years of product ad desig experiece, ad over 25 patets i computer architecture ad commuicatios. Gerry Talbot Gerry Talbot is a Seior Follow at AMD, his primary focus is high-speed IO desig, ivolvig the developmet of, ad cotributig to, idustry stadard specificatios such as HyperTrasport, PCI Express, PCI266/533 ad FB-DIMM. His work ivolves silico circuit desig, system level jitter modelig, itercoect chael modelig ad sigal itegrity simulatio. Ja Wilstrup Mr. Wilstrup is a corporate cosultat at Teradye Ic. His preset iterests are SI simulatio ad aalysis, sigal ad oise aalysis methods ad aalog circuits. He holds 4 patets ad has 7 patets pedig i the istrumetatio area. He studied mathematics ad physics at the Uiversity of Miesota.

3 1.) Itroductio The serial data commuicatio architecture has bee prove to have the capability of carryig data over fiber medium at a rate > 1 Gb/s. The architectures of these serial commuicatio liks are characterized by the fact that the bit clock is embedded i the trasmitted bit stream ad it is recovered by a clock recovery (CR) fuctio at the receiver side of the lik. Typically the CR is implemeted by usig a phase-locked loop (PLL). Figure 1 shows a basic block diagram for a simple serial lik ad related clock recovery fuctio. Tx Rx Data Medium D Q Data Clk CR/ PLL C Figure 1. A schematic block diagram for a serial commuicatio Meawhile, persoal computer (PC) ad mai-frame work statio commuicatio liks ad I/O buses have also evolved from a parallel bus where a sychroized global clock is distributed with each data path, to source sychroized I/O where the data is strobed by the clock at the receiver register, to serial data I/O similar to those etwork I/O architectures. At data rates > 1 Gb/s, most of the commuicatio liks coverge to serial architecture with embedded clock or referece clock, plus a clock recovery fuctio. Typical etwork cetric etwork stadards iclude: Fibre Chael (FC) ad Giga Bit Etheret (GBE); ad typical PC I/O stadards at > 1 Gb/s are PCI express (2.5 Gb/s for geeratio I) ad Serial ATA (1.5 Gb/s for geeratio I). The key performace merit for a serial commuicatio lik is the BER. The root causes for o-zero BER are timig jitter ad amplitude oise. However, sice BER is a system performace merit, the system trasfer fuctios for jitter ad oise must be icorporated ito the equatio to quatify it. A simple geeric receiver jitter trasfer fuctio model has bee established [1][2] based o the receiver architecture as show i Figure 1. The schematic diagram of such model is show i Figure 2. Rx: H rx (s) Jitter i + Jitter out H cr (s) CR/ PLL - Figure 2 A schematic diagram showig that the receiver jitter trasfer is the differece fuctio betwee the data ad clock iputs to the receiver data retimig logic. The essece of this model is that the jitter trasfer fuctio is the differece betwee the data sigal ad the recovered clock sigal. I the cotext of Figure 2, such a trasfer fuctio ca be represeted by: H rx (s) = 1-H cr (s), where H rx (s) is the jitter trasfer fuctio for the receiver, H cr (s) is the frequecy trasfer fuctio for the clock recovery, ad s is the complex frequecy. Most clock recovery circuits have a low-pass characteristic, such as PLL-based clock recovery circuits. Sice H cr (s) is low-pass, therefore H rx (s) will be high-pass due to the differece fuctio, resultig low-frequecy jitter beig tracked or atteuated by the receiver. Receiver architectures for etwork I/O liks, such as FC ad GBE, all have high-pass jitter trasfer fuctios. A BER of 1-12 or less is a commoly accepted maximum value for most commuicatio stadards.

4 While both etwork ad PC serial commuicatio stadards share some similarities at rates > 1 Gb/s: they both use asychroous serial data trasfer schemes ad clock recovery at the receivers. However, there are some sigificat differeces. For example, etwork commuicatio lik compoets are typically low-volume ad high-cost, ad this gives the desiger the luxury to use relatively expesive, high-quality, ad low-jitter compoets, such as a oscillator or a clock geerator. I cotrast, PC commuicatio lik compoets are typically high-volume ad low-cost, prevetig the desiger of usig highcost ad low-oise compoets, such as a low-jitter clock source; yet, the system still eeds to maitai a similar BER performace as the etwork I/O lik. This is the major challege for desigig a PC I/O lik, such as PCI Express. Oe key differece i PC serial I/O liks is the CR fuctio of the receiver. I PC serial applicatios the CR may be implemeted usig low-cost digital methods such as a phase iterpolatio (PI) [4] that operates differetly from a covetioal PLL CR. Furthermore, PC I/O liks eed to deal with the spread spectrum clock (SSC) that is ot used for a etwork I/O liks. SSC may degrade the BER. Cosiderig these differeces, etwork serial I/O architecture caot be directly adopted for PC use, ad some chages are eeded for PC I/O eeds. PC I/O liks represet a ew jitter ad oise estimatio ad aalysis problems, ad methods eed to be created for PC I/O liks. Some of the established fudametal jitter models such as the differece fuctio are still valid as the basis. I this paper, we will oly focus o serial lik referece clock jitter ad use the PCI Express I/O lik [3] as a bechmark. Eve though we oly focus o PCI Express, it is ot realistic to address all the jitter ad oise challeges i a sigle paper such as this oe due to their complexity. We will oly focus o the system jitter trasfer fuctio for the 1 MHz referece clock jitter. Our goal is to establish a appropriate relevat jitter defiitio ad jitter trasfer fuctio so that the total eyeclosure (or total jitter) at a certai BER ca be estimated at the receiver side, give the referece clock jitter. We will discuss various jitter defiitios ad their iterrelatioships i sectio 2 ad select the appropriate oe to work the system jitter trasfer fuctio. I sectio 3, we will develop the system jitter trasfer fuctios based o PCI Express I/O lik system architecture, for clock ad data recover schemes that use a PI or a PLL. Correspodig umerical simulatios for the trasfer fuctios ad their depedeces o the model parameters were also carried out. I sectio 4, we apply the developed trasfer fuctio to some measured referece clock phase jitter ad study how will it be chaged by the trasfer fuctios ad estimate the worst case eye-closure at the receiver with the trasfer fuctio parameters. I sectio 5, we will give a summary ad some coclusios, as well as discussio of the topics that are ot covered by curret paper, but will be i future publicatios. 2.) Phase, Period, ad Cycle-to-Cycle Jitter ad Their Iter-relatioships Various jitter defiitios have bee proposed for 111 clock-like sigals. Examples iclude time-domai cycle-to-cycle jitter ad frequecy-domai phase oise. However, there is o publicatio so far that discusses the mathematical implicatios for each defiitio ad the iter-relatioships betwee them. I order to select the appropriate jitter defiitio for PC serial I/O liks, we eed to treat those various jitter defiitios i a same ad coheret theory frame so that the iterrelatioship ca be established, ad persistet ad iterchageable results ca be obtaied. We will start with the threshold crossig timig defiitio first. 2.1) Timestamps of Threshold Crossigs Assumig the data cosists of a repeatig 111. clock patter, the measuremet of each cosecutive threshold crossig ca be recorded ad stored as a array. This is the timestamp array of the threshold crossigs. The time stamp array of the threshold crossigs are equivalet to the accumulated phase of the data UI, also kow as the absolute phase. I the case of the 4 ps UI for PCI Express data stream, every 4 ps the represets oe complete cycle or revolutio ad is equal to 2π radias. The absolute phase, starts at ad proceeds to grow ubouded, at the rate of Θ T, =,1,2..., N (2.1) For the ideal case where there is o phase jitter, the first UI starts at radias ad eds at 2π radias. The secod UI starts at 2 π radias ad eds at 4π radias. The third UI starts at 4π radias ad eds at 6π, ad so o. Thus every UI ca be thought of as oe complete cycle or a complete revolutio of the clock. T ca be replaced by 2π to get the equivalet radias from a UI period as i Θ = 2 π, =,1,2..., N (2.2) This is show i Figure 3, where the straight lie is a measuremet ad the threshold crossigs are exactly 4 ps apart. The stem lies have a siusoidal error term added to them. The Y axis is the absolute phase of the sigals ad is represeted i s ad parethetically i radias. The X axis is the ideal clock for each measuremet ad is give i s.

5 9.6s (48 π ) 8.s (4 π ) id e a l t Absolute Phase, s, (radias) 6.4s (32 π) 4.8s (24 π) 3.2s (16 π ) t 1.6s (8 π ) s s 1.6s 3.2s 4.8s 6.4s 8.s 9.6s T Figure 3 : Absolute phase versus T 2.2) Bit Period (T) ad Uit Iterval (UI) The Uit Iterval is defied as the differece i a measuremet ad the previous measuremet. UI t t, m 1,2,..., N (2.3) m = m m 1 = The ideal bit period, T, is a mathematical coveiece for developig the uderstadig of what jitter is ad how to derive it. I practice, the bit period is extracted from the data itself. This extractio process produces the recovered clock that has the recovered period, ad is actually used i the calculatios. 2.3) Phase Jitter (Φ) The phase jitter is defied as the differece betwee the measured time ad the ideal bit period T. Phase jitter is a accumulatio of the time error from the ideal time of *T. Φ = t T, =,1,..., N (2.4) Figure 4 shows a example of siusoidal phase jitter at 1 MHz with a arbitrary magitude of ± 45 ps show o the Y axis. 4 ps (2 π) Φ Phase Jitter, s, (radias) 2 ps (π) ps ( π) -2 ps ( π) -4 ps ( 2 π) s 1.6s 3.2s 4.8s 6.4s 8.s T 9.6s Figure 4: Phase jitter versus T 2.4) Period Jitter (Φ ) The period Jitter (Φ ) is the differece betwee the measured period ad the ideal period ad is defied as: Φ ' = ( t t ) T, = 1,2,..., N 1 (2.5)

6 Combiig equatios (2.4) ad (2.5), it ca be show that the period jitter, Φ, is also ' Φ = Φ Φ 1 (2.6) This is the first differece fuctio of the phase jitter : Φ. Period jitter, Φ, is show i Figure 5, where T is the ideal 4 ps. The Y axis shows the magitude of the period jitter i ps ad, parethetically, i radias. 4 ps (2 π) Φ Phase ad Period Jitter, s, (radias) 2 ps (π) ps ( π) -2 ps ( π) Φ ' -4 ps ( 2 π) 1.6s 3.2s 4.8s 6.4s 8.s 9.6s T Figure 5: Phase ad period jitter versus T 2.5) Cycle-to-Cycle Jitter (Φ ) The cycle-to-cycle jitter is the differece betwee cosecutive bit periods ad is defied as: Φ " ( t t ) ( t t ), 2,3,..., N = = Combiig equatios (2.5) ad (2.7) it ca be show that this is also Φ " = Φ ' Φ ', 2, 3,..., N 1 = ad is the first differece fuctio of Φ, or the secod differece fuctio of Φ. This is show i Figure 6. The Y axis shows the magitude of the cycle-to-cycle jitter i ps ad parethetically i radias. (2.7) (2.8) 4 ps (2 π) Φ Phase, Period ad Cycle to Cycle Jitter, s, (radias) 2 ps (π) ps ( π) -2 ps ( π) -4 ps ( 2 π) Φ' Φ ' Φ '' 1.6s 3.2s 4.8s 6.4s 8.s 9.6s T Figure 6: Cycle-to-cycle jitter ad differece fuctio of period jitter versus T 2.6) Jitter Relatioships All three jitter types are show i Figure 6 for a phase jitter magitude of 45 ps (2.25 π radias) at a frequecy of 1 MHz. The first ad secod differece fuctio from Φ to Φ to Φ, respectively, ca be see i Figure 6.

7 It follows that all three desigatios of jitter: phase jitter, Φ, period jitter, Φ ', ad cycle-to-cycle jitter, Φ' ', are differet ways to represet the same physical behavior of the clock jitter. Give a complete record i time of jitter i ay oe of the forms, the other two ca be derived. Without a complete record i time, coversio betwee the differet represetatios of jitter is ot possible. For example, if oly a peak-to-peak value for the period jitter is kow the determiig the peak-to-peak value of phase jitter or the peak-topeak value of the cycle-to-cycle jitter is ot possible. A aalogy ca be draw with rotatioal motio: Phase jitter ca be cosidered the relative distace that the actual (measured) phase has moved from the absolute phase of the ideal clock. I other words, it is the umber of radias that the phase of the clock is vs where it should be. Period jitter is the speed at which the phase is chagig. Cycle-to-cycle jitter is the acceleratio of the phase from or to the ideal phase. I all receiver architectures, the goal of the clock recovery is to alig the samplig clock to the icomig data stream. Certai data recovery architectures, such as PI type, rely o the phase of the referece clock to grossly alig the sample clocks, ad the have other mechaisms to provide fie adjustmet of the referece clock phase to the icomig data phase as discussed i [4]. For these types, the presece of phase jitter ad the respose of the compoets to phase jitter are critical for the proper operatio of the system. 3.) Jitter Trasfer Fuctio Derivatio ad Simulatios I this sectio, we will first review the various clock ad data recovery circuits (CDRCs) used i PCI Express I/O lik. We will the establish the jitter trasfer fuctios from the referece clock the receiver based o various CDRC topologies. Oce the trasfer fuctio is obtaied, we will perform the umerical simulatios ad reveal the characteristics of the trasfer fuctios ad its depedecy o key parameters of the circuits. We the apply the trasfer fuctio to the measured jitter from the 1 MHz referece clock to estimate the relevat total jitter (or eye-closure) at the receiver. For a give BER level, the eye-closure ad total jitter is related by: eye-closure (BER) = UI TJ (BER). 3.1) Clock ad Data Recovery Circuits (CDRCs) We will cosider three types of CDRCs for the PCI Express I/O lik, the PI, the Oversampler, ad PLL. The data recovery operatio requires lookig at the icomig data ad recoverig the phase ad frequecy of the icomig data stream, after accoutig for missig threshold crossigs. A clock is geerated locally or through the clock recovery that matches the data phase ad frequecy of the icomig data ad is used to sample the data at the receiver ) Digital Based The PI ad Oversamplig CDRCs use a digital mechaism to achieve phase aligmet of the clock with the data. They belog to the class of digital CDRCs ad are ot easily modeled. They also have limited ability to track chages i frequecy, ad, i geeral, rely o the systems commo referece clock system ad iteral referece PLLs to recover the frequecy iformatio. Digital based CDRCs are kow to have lower silico cost ad power cosumptio ) PLL Based The PLL based CDRC does ot use the commo referece clock to recover the phase or the frequecy. It looks exclusively at the icomig data ad adjusts phase ad frequecy accordigly. This clock recovery scheme is widely used i etwork commuicatio lik ad it has a well-kow trasfer fuctio ad the order of the trasfer fuctio ca be 2 d order or higher, providig better jitter rejectio/tolerace compared with a first-order CDRC trasfer fuctio.

8 3.2) Receiver Eye-closure Figure 7 shows the relatioship of the referece clock jitter to the eye-closure see at the receiver. This is the diagram for a PI type clock recovery. A descriptio of this type of clock recovery ca be foud i [4]. Figure 7: System model for referece clock iput X to eye-closure Y for a digital CDRC For this architecture, the receiver sees phase jitter ot as the absolute value of W_1 (iput sigal to the flip-flop D port), but as the relative differece betwee W_1 ad W_3 (iput sigal to the flip-flop clock port). The closure is give as Y ad cosists of all the sources of jitter. This paper addresses oly the jitter that is caused by the mismatch i the PLLs i respose to jitter cotet of X ad the badwidths of the PLLs. There are may other sources of jitter that cosume the timig budget at the receiver; these will be explored i some detail i a future paper. 3.3) System Trasfer Fuctios I this sectio, we will defie the model ad system trasfer fuctio for the PLLs. A review of system trasfer fuctios ca be foud i refereces [5][6], from which we adopt the otatio covetios used i this paper. More iformatio o PLL trasfer fuctios ad modelig PLLs i the s-domai ca be foud i refereces [7][8] ) PLL Trasfer Fuctio The iput sigal to a PLL is ad the output sigal of the PLL is ( t P ( )) V t) = A si ω + t (3.1) i ( i i i ( t P ( )) V ( t) = A si ω + t (3.2) out out Here ω i is the iput carrier frequecy ad ω out is the multiplied output frequecy, both give i radias per secod. The terms P i (t) ad P out (t), expressed i radias, represet the absolute phase i time of the iput ad output sigals ad are sometimes referred to as excess phase or, i this discussio, phase jitter. I a properly desiged PLL, the iput ad output frequecies ad amplitudes do ot chage with time. The phase sigals P i (t) ad P out (t) are a fuctio of time, so the PLL has a phase trasfer fuctio. I the complex s domai, the phase trasfer fuctio of the PLL H(s) is give by out out Pout ( s) H ( s) = (3.3) P ( s) P out (s) ad P i (s) are the Laplace trasforms of P out (t) ad P i (t). The PLL is also a cotrol system that trasfers the phase modulatio at its iput to its output. Kowig the trasfer fuctio ad the iput phase, the output phase ca be calculated. Or i geeral, kowig two of the three fuctios i equatio (3.3), the third oe ca be estimated through it. Actual PLLs used i typical CMOS process are ofte havig a third-order trasfer fuctios ad the additioal pole for the 3 rd - order ca steep the trasfer fuctio magitude respose at high frequecies. However, they ca still be approximated as a i

9 secod-order trasfer fuctio over the bulk of the iterested frequecy rage. This discussio exclusively uses the simpler secod-order trasfer fuctio as a approximatio ) Secod-Order PLL Trasfer Fuctios We will use a two-pole, oe-zero secod-order model for the PLL trasfer fuctio. The secod order model is based o the active proportioal itegratio cotrol loop with the trasfer fuctio give by: 2 2ζωs + ω H ( s) = (3.4) 2 s + 2ζω s + ω where ζ is the dampig factor, ad ω is the atural frequecy. This fuctio is ot meat as a requiremet for a implemetatio. It is used as a boudig fuctio for modelig purposes to establish the lower limit for the f_3 db frequecy ad the maximum peakig. The traslatio betwee atural frequecy ω ad the 3 db frequecy is give by: ω db = ω 1+ 2ζ + (1 + 2ζ ) 1 (3.5) 3 + A upper allowed boud of 3 db of peakig was chose for aalysis i order to limit the resultat worst case gai, resultig i ζ of.54 miimum. This results i the trasfer fuctios show i Figure 8 for the example where the 3 db frequecy (f_3 db) is 15 MHz. 1 Magitude of Trasfer Fuctio 5 Mag (db) Frequecy (Hz) Figure 8: Trasfer fuctios for f_3db = 15 MHz ad ζ = ) Digital CDRC System Trasfer Fuctio Referrig to the system model diagram i Figure 7, the iput phase jitter sigal x(t) is trasformed to the s domai as X(s) ad is acted o by the trasfer fuctios of the system model as discussed i sectio The system model ca be simplified ad draw as show i Figure 9.

10 Figure 9: Simplified system model for iput jitter to receiver eye-closure Here X(s) is the iput sigal represetig the iput phase jitter, H_1(s) is the trasfer fuctio of the Tx PLL, H_2(s) is the trasfer fuctio of the Rx PLL, H_3(s) is the high-pass trasfer fuctio of the CDRC, ad Y(s) is the output sigal that represets the eye-closure at the receiver caused oly by the jitter o the referece clock propagatig through the system. The total trasfer fuctio of this system is give by H t ( _ 1 _ 2 _ 3 s) = [ H ( s) H ( s)] H ( s) (3.6) The output sigal ca the be calculated for ay X(s) as Y(s) = H t (s) X(s). Note that there is a phase delay that is ot show ad will be discussed i ext sectio. The trasfer fuctio H_ 3 (s) is the respose of the CDRC circuit. H_ 3 (s) is assumed to have a f3_3db respose of 1 MHz or higher. This is ecessary so that the CDRC ca track out the phase jitter caused by the combiatio of SSC (at 33 KHz) ad trasport delay. The trasfer fuctio of H_ 3 (s) is a sigle-pole high-pass fuctio that is give by s H _ 3( s) = (3.7) s + ω where ω 3 is simply ω = 2 f 3 _ 3dB. 3 π It is clear that if H_ 1 (s) ad H_ 2 (s) are perfectly matched; o eye-closure occurs regardless of the phase jitter cotet of the referece clock sice H t (s) =. Whe there is a mismatch i the trasfer fuctio, a eye-closure occurs that is depedet o the phase jitter cotet of the referece clock ad the differece of the trasfer fuctios. I practice, the cotrol of the trasfer fuctio is iexact ad the variace is large eve betwee two devices of the exact same desig, process, ad maufacturig lot. Mag (db) Magitude of Trasfer Fuctios F1: 1.e+6 F2: 2.2e+7 F3: 1.5e Frequecy (Hz) H1 H2 H3 Ht

11 Figure 1: Iput jitter to eye-closure for f1_3db = 1MHz, f2_3db=22 MHz, ad f3_3db = 1.5MHz ad ζ 1 = ζ 2 =.54 Figure 1 gives the trasfer fuctio of referece clock phase jitter to receiver eye-closure. All of the phase jitter frequecies preset i a iput sigal X(s) i the frequecy rage of ~ 4 khz to ~2 MHz will cause the eye to close at Y(s), with atteuatio occurrig outside this rage. Due to the peakig, there is gai i this rage, ad the phase jitter gets amplified. Oly a portio of the phase jitter outside this rage cotributes to the eye-closure at Y(s). This meas that low-frequecy o the clock referece phase jitter is tracked equally by both the Tx ad Rx devices ad does ot cotribute to eye-closure. Jitter at ~ 4 khz, the f_3 db lower corer of the bad-pass fuctio as show i Figure 1, trasfers ~.77 of its magitude to eye-closure. Jitter i the rage of approximately 4 khz to 1 MHz is amplified ad cotributes directly to eye-closure. Settig the miimum f1_3db frequecy to 7 MHz for Tx ad the maximum f2_3db set at 22 MHz for Rx, or vice verse, we get the trasfer fuctio show i Figure 11. This is the trasfer fuctio that is to be applied to the referece clock phase jitter X(s) to produce Y(s) eye-closure at the Rx i order to model this rage of PLLs i the Tx ad Rx. The upper limit of 22MHz was chose as the theoretical limit of stability for a PLL with a 1 MHz iput referece [8]. The resultig peak value i y(t) is the peak jitter output of the referece clock. Mag (db) Magitude of Trasfer Fuctios F1: 7.e+6 F2: 2.2e+7 F3: 1.5e Frequecy (Hz) Figure11: Worst case iput jitter to eye-closure for f1_3db = 7MHz, f2_3db=22 MHz, ad f3_3db = 1.5MHz ad ζ 1 = ζ 2 = ) PLL CDRC System Trasfer Fuctio A simplified PLL clock recovery system model is show i Figure 12 where X(s) is the iput phase jitter, H_1(s) is the trasfer fuctio of the Tx PLL, H_2(s) is the trasfer fuctio for the Rx PLL, ad Y(s) is the output. H1 H2 H3 Ht Figure 12: Simplified system trasfer fuctio for a PLL based CDRC The total trasfer fuctio is the H t ( _ 1 _ 2 s) = H ( s)[1 H ( s)] (3.8)

12 I this case, a solutio that miimizes H t (s) is whe the 3dB frequecy f1_3db for H_ 1 (s) is smaller f2_3db of H_ 2 (s). Usig the PLL trasfer fuctio ad the frequecies of f1_3db = 7 MHz ad f2_3db = 22 MHz, the total system trasfer fuctio is show i Figure 13. Mag (db) F1: 7.e+6 F2: 2.2e+7 Magitude of Trasfer Fuctios Frequecy (Hz) Figure 13: Iput jitter to Rx eye-closure for a PLL with f1_3 db of the Tx PLL at 7 MHz ad f2_3 db of the Rx PLL at 22 MHz H1 H2 Ht Settig f1_3db to 22 MHz ad f2_3db to 7 MHz, we get the results show i Figure 14. Mag (db) Magitude of Trasfer Fuctios F1: 2.2e+7 F2: 7.e Frequecy (Hz) Figure 14: Iput jitter to Rx eye-closure for a PLL with f1_3db of 22 MHz at Tx ad f2_3db of the Rx PLL at 7 MHz H1 H2 Ht This results i a similar performace as the digital clock recovery model, amely they both show the bad-pass characteristic. Clearly the case of havig the Rx PLL badwidth higher tha the Tx PLL badwidth provides better overall jitter rejectio. Obviously, to miimize the effect of the referece clock phase jitter it is a advatage for the PLL based CDRC to have a high Rx badwidth ) Trasport Delay ad System Phase Respose The delay ad phase respose also cotributes to timig error. Oe compoet of the phase respose is the fixed phase delay due to the routig legth differeces of the 1 MHz clock ad the data chael, as show i Figure 15. Aother compoet of the phase respose is the differeces i the trasfer fuctios of the Tx ad Rx PLLs. Additioal delay may come from the isertio delay of the chips themselves. This is all lumped ito the category of phase differece.

13 Figure 15: Gai iduced by routig phase delay The phase differece ca cause additioal eye-closure. The eye-closure ca be modeled by multiplyig either H_1(s) or H_2(s) by exp(-s t_delay), where t_delay is the maximum time for the itercoect phase delay ad is the relative differece i flight time. This is show i Figure 15 as [(L1 + L2) L3] / v g, where v g is the propagatio velocity of the clock sigal ad is assumed to be a costat. A example of the phase delay effect ca be see i the trasfer fuctio as show i Figure16. 1 Magitude of Trasfer Fuctios 5 Mag (db) F1: 7.e+6 F2: 2.2e+7 F3: 1.5e Frequecy (Hz) No Delay 1 s Delay 2 s Delay Figure 16: Effect of phase delay o trasfer fuctio We make a assumptio that the total delay differece for PCI Express liks does ot exceed 3 s, ad this is based o the total legth of cables that carry the 1 MHz referece clock o a PC board. As the delay betwee the paths icrease beyod 3 s, the referece clocks become ucorrelated at the higher frequecies ad the delay effects become domiat i the trasfer fuctios. I the case of delay beyod 3 s, the eye-closure ca exceed 6 db at the lower frequecies. The miimum respose of H_ 3 (s) serves to keep the delay effects from domiatig the low frequecy respose. This is show i Figure 17 where the delayed trasfer fuctio, show i gree, rolls off to the left at -4 db/decade due to the additio of H_ 3 (s). Without H_ 3 (s), the delay becomes domiat at the low ed ad the roll-off is -2 db/decade.

14 1 5 Magitude of Trasfer Fuctios Ht with 3 s D elay -5 Mag (db) F1: 7.e+6 F2: 2.2e+7 F3: 1.5e H1 H2-35 H3 Ht No Delay Frequecy (Hz) Figure 17 : 3 s delay effect o eye-closure 4.) Applicatios of Jitter Trasfer Fuctio to Platform 1 MHz Referece Clock for PCI Express The trasfer fuctios developed i sectio 3 will be used to estimate the eye-closure at the receiver give the phase jitter of the referece clock ad the trasfer fuctio from the referece clock jitter to receiver eye-closure established i sectio 3. Due to the page limitatio, as well as the fact that most of the PCI Express receivers use digital CDRC, we will oly focus o the PI digital CDRC aalysis usig the theory developed i sectio 3.3.3, leavig the PLL based CDRC aalysis to a future publicatio usig the theory sectio ad a similar method developed i this sectio. Oe-way to establish the 1 MHz platform referece clock phase jitter upper limit is to idetify the maximum amout of jitter after the followig trasfer fuctio has bee applied to the phase jitter ad coduct the iverse Laplace trasform: 1 ( _1 _ 2 _ 3 y t ) = L { X ( s) [ H ( s) H ( s)] H ( s)} (4.1) I this example, we use the 3 db frequecy f1_3db of H_ 1 (s) as 7 MHz, the 3 db frequecy f2_3db of H_ 2 (s) as 22 MHz, ad the dampig factor ζ =.54. H_3(s) is the first order high-pass with a 3 db frequecy of 1.5 MHz. X(s) is the iput spectrum of the referece clock ad L -1 { } is the iverse Laplace trasform. The maximum routig delay as discussed i Sectio to accout for the worst-case phase delay is accouted for by providig 2x estimatio. The phase modulatio of oe clock referece chip is show i Figure 18, where the 33 khz SS that domiates the phase modulatio, ca be see. The SSC compoet has a magitude of ~1 s.

15 x 1-8 Phase Jitter vs Time 1.5 time (S) time (S) x 1-4 Figure 18: Time-domai phase jitter with SSC as the domiat feature The spectrum of this referece clock before ad after the differece fuctio is applied is show i Figure Phase Jitter Frequecy Cotet Before filter fuctio applied Magitude (S) After filter fuctio applied Frequecy (Hz) Figure 19: Phase jitter spectrum before ad after the system trasfer fuctio The iverse Laplace trasform of the spectrum after the differece fuctio of the eye-closure is show i Figure 2. Here the total eye-closure for this limited sample is o the order of 7 ps.

16 6 x Eye closure (S) Time (S) x 1-3 Figure 2: Time-domai of the eye-closure The phase jitter sample size i Figure 19 ad 2 is ~ 1.5x1 5, givig rise to a BER level of ~1-6. The method for establishig a eye-closure dow to 1-12 will be discussed i a future paper. 5.) Summary ad Coclusios We have show that clock jitter ca be characterized i a umber of ways, phase jitter, period jitter, or cycle-to-cycle jitter. They are differet represetatios of same physical pheomea ad therefore are iterrelated. Period jitter is equivalet to the first differece of phase jitter, ad cycle-to-cycle jitter is equivalet to the first differece of period jitter or the secod differece of phase jitter. Give a complete fiite record i time of jitter i ay oe of those three forms, the other two ca be derived. However, if oly a peak-to-peak value for oe form of jitter is kow, determiatio of the peak-to-peak values of the other forms of jitter is ot possible. Trasfer fuctios are traditioal way of accurately predictig a liear system behavior ad they have bee developed to model the performace of serial commuicatio system such as PCI Express devices ad I/O liks whe icludig the effects of referece clock jitter. This paper establishes a method that properly determies the overall performace of the system merited by the eye-closure (or total jitter) at a certai BER, give the referece clock phase jitter ad the characteristics of the parts of the system, such as PLL trasfer fuctios. These methods will serve as a foudatio i establishig the requiremets for both trasmitter ad receiver PLL trasfer fuctios ad referece clock jitter i way that the eye-closure at the receiver meets certai eeds. Without these foudatios, it is ot possible to establish ay ratioal boud for the referece clock jitter, trade-off betwee trasmitter, medium, ad receiver eye-closure budget, ad appropriate scalable, ad iterchageable jitter measuremet methods. We did ot discuss the trasmitter ad receiver eye-closure estimatio ad measuremet methods for the PCI Express serial lik i this paper. Those topics will be discussed i a future publicatio. However, the groud work that we established i this paper for referece clock are still applicable to trasmitter ad receiver eye-closure estimatio ad measuremet. I fact, we believe that the method we established here ca also serve as a guidelie for other computer serial lik stadards where digital or PLL based CDRC are used, alog with a oisy referece clock such as the oe with SSC. Oe example would be Serial ATA. We realize that we have used a secod-order trasfer fuctio to model the PLL behavior. Experimets desiged to evaluate the accuracy ad goodess of the secod-order PLL model are i progress by usig actual PCI Express lik system. If, however, the experimets show too big error, the extesio of the curret secod order PLL to a higher order PLL may be ecessary to achieve better accuracy. Cosequetly, the system jitter trasfer fuctio will be modified. Those will be the topics for the future publicatios. Nevertheless, the basic theory foudatio established i the curret paper will still apply. We have used s-domai cotiuous system trasfer fuctio to model the PCI Express I/O lik where CDRC operates discretely. It is well kow that a s-domai trasfer fuctio provides a simple ad ituitive approach to model the system behavior ad yet still provides a good approximatio to a correspodig sampled digital system. For higher order accuracy, a Z-domai trasfer fuctio approach is eeded ad we will address the Z-domai trasfer fuctio i a future publicatio.

17 We wat to emphasis that the method established i this paper of first covert the time-domai phase jitter to s-domai spectrum, the multiply the phase jitter spectrum by the jitter trasfer fuctio i s-domai, ad the apply the iverse Laplace to their product to get back the time domai eye-closure, is, oly oe-way to obtai the eye-closure. Other alterative methods are also possible. For example, trasfer fuctio ca also be represeted equivaletly by a ifiitive impulse respose (IIR) filter respose fuctio i-time domai, ad eye-closure ca be estimated directly i time-domai give the phase jitter i time-domai for the referece clock. I aother example the trasfer fuctio ca be also equated by a clock recovery circuit fuctio ad the phase differeces betwee this recovered clock ad the referece clock will give the eye-closure estimatio directly i time domai. We will address those iterestig topics i future publicatios. Refereces [1] Natioal Committee for Iformatio Techology Stadardizatio (NCITS), Workig Draft for Fibre Chael Methodologies for Jitter Specificatio-MJSQ, Rev 1, 23. [2] M. Li ad J. Wilstrup Paradigm Shift For Jitter ad Noise I Desig ad Test > 1 Gb/s Commuicatio Systems, ICCD, 23 [3] PCI-SIG, PCI Express Base Specificatio, Rev. 1.a, ( 23 [4] W. J. Dally ad J. W. Poulto, Digital Systems Egieerig, Cambridge Uiversity Press, [5] A. V. Oppeheim, A. S. Willsky, ad S. H. Nawab Sigals & Systems, Pretice Hall, 1996 [6] G. E. Carlso Sigals ad Liear System Aalysis, 2d editio, Joh Wiley ad Sos, 1998 [7] R. E. Best Phase-Locked Loops: Desig, Simulatio, ad Applicatios, 4 th editio, McGraw Hill, [8] F. M. Garder Phaselock Techiques, Joh Wiley & Sos, 2 d Editio, Ackowledgemets: This paper is beefited from may stimulatig discussios amog PCI Express jitter workig group (JWG) members.

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