The Silicon Controlled Rectifier (SCR)

Transcription

1 The Silico Cotrolled Rectifier (SCR The Silico Cotrolled Rectifier, also called Thyristor, is oe of the oldest power devices, ad it is actually employed as power switch for the largest currets (several kiloamperes ad voltages (several kilovolts as preseted i the itroductory lesso. ts ame idicates that the device behaves a a diode (or rectifier i his O state, with a very low forward drop (if compared with the oe of the other devices, but it is ormally i OFF state, ad to be brought i the O state it requires a trigger o a separate cotrol termial (called gate. From this effect we ca cosider the SCR as a silico device that behaves as a diode or rectifier - i forward bias if a commad is doe o the cotrol termial. The mai drawback of the SCR is that we ca ot cotrol it i the opposite way i.e. we ca ot act o the cotrol termial to brig it i the OFF state whe it is already coductig (O state. The i order to switch off the SCR we ca oly rely o the atural curret commutatio, i other words we must revert the voltage across it, from forward to reverse bias (as for the diode to iterrupt the curret flowig ito it. The device, like the diode ad the BJT, is a bipolar device: its operatio relies o both type of carriers, ad the low voltage drop i coductio is actually due to the coductivity modulatio (already discussed for the diode that takes place at high ijectio i the thick ad low doped regio (eeded to sustai high voltages i OFF state. Uiversity Federico The cross-sectio of the structure of a SCR is depicted i fig. (a: the two mai termials are the aode (o the bottom of the chip that is biased at positive voltages i forward state, ad the cathode (o top of the chip that is grouded. The gate termial is the cotrol electrode that allows to switch o the SCR. Cosiderig the mai portio idicated i dashed lie, we see that there are four dopig layers( ad three / juctios from cathode to aode (fig. (b. simple aalysis of this structure ca be doe by cosiderig it made by two complemetary BJT ( ad closely coected, as idicated i fig. (c,d: gate cathode + J J J J - w + aode (a (b (c Uiversity Federico J 3 J 3 (d

2 D.C. aalysis a trigger coditio of the SCR SCR approximate aalysis, to uderstad the behavior i forward bias (V >0, ad to defie the trigger coditio that will chage its state from OFF to O, ca be doe by referrig to the cofiguratio with two BJT see before. a forward blockig (OFF state Whe B 0, ad assumig V > 0, both BJT are i the active regio ad we have: C + C. t high voltage where multiplicatio takes place (as see for BJT eq. (6 we have: C C M M E E + M + M C 0 C 0 Summig the two currets: M + M M C 0 + M C 0 ( C+ C ( M+ M + M ( C 0+ C 0 M ( C 0 + C M( + 0 The curret is egligible at low voltages ad icrease largely oly whe M( +. The max voltage V MX is ear to the breakdow voltage of J because the of the BJT is quite low. ( E Q C B 0 E Q B C Uiversity Federico 3 the forward blockig state the / juctios J ad J 3 are forward biased, while the / juctio J is reverse biased, as idicated i figure. The cetral regio must be thick ad low doped to sustai high reverse voltages with V positive, eeded to keep the SCR i the OFF coditio eve at high aode voltages if the SCR is ot triggered. The trasistor Q has very low (< 0.5, because the width of the base regio is large; also the trasistor Q has a relatively low because the layer is ot thi or low doped. We must cosider that both ad deped o the V voltage, because the effective width of the base for the two BJT (maily Q decreases if V is icreased, due to the depletio width of regio J. The voltage depedece of alphas is importat i defiig the V curves of the SCR i the off-state regio. Uiversity Federico 4

3 b the triggerig coditio f a gate curret is ijected from the gate electrode : + ad eq. ( are chaged as: C C M M + M + M C 0 C 0 M ( + + M C 0 C+ C M + M ( + + M ( C 0+ C 0 ad we have: M + M ( C 0 + C 0 (4 M( + (3 E Q Eq. (4 is the geeral equatio for the trigger coditio of the SCR, valid also for low voltages with o multiplicatio (M: C CB + ( C ( ( 0 C B Q i that case we ca still have a curret icreasig idefiitely (trigger coditio if the coditio + ( holds. E Uiversity Federico 5 Why the emitter curret gai is a fuctio the juctio curret? s see i the curret gai aalysis of BJT (pag. 4, is basically the ijectio factor γ of the emitter juctio: γ E / E. t low curret we must cosider for the curret E ot oly the hole ad electro compoets but also the geeratio/recombiatio curret i the depleted layer, that has a depedece exp(v J /V T from the juctio voltage. the case of SCR we have for the expressio: + p V exp V 0 J T VJ exp VT VJ + 0 exp V T (5 log t low currets is a substatial part of the total curret, ad is low; if the curret icreases (because V J is icreased, the compoet becomes egligible with respect to ad icreases ear to uity. f we the icrease the total J 3 curret by ijectig a gate curret, will be icreased from <0.5 to about , ad the trigger coditio will be met. Uiversity Federico 6

4 Whe the coditio ( + is met, we reach the tur-over poit i the V curve of the SCR, because d /dv 0. The total curret icreases without limits, because both BJTs Q ad Q eter ito saturatio mode. positive feedback develops for this cofiguratio, because the icrease of C curret of Q correspods a icrease of the drive base curret B of Q, ad that i tur icreases C ad hece the drive base curret B of Q, ad so o. This situatio is self-sustaiig (latchig state, because it ca be maitaied eve if the iitial gate curret is removed, because ow the base curret B of Q is geerated by the C curret of Q. The curret ca be the a short pulse to trigger the switch from OFF to O state, but it does ot eed to be maitaied after the triggerig (this is a importat aspect for the drive circuitry. f both Q ad Q are i saturatio, the / collector juctio J (for both BJT must be forward biased, as idicated i figure, ad the whole V voltage drops to a very low value, beig the (algebric sum of three forward biased juctios, with J ad J summig ad J 3 subtractig: V V + V V 3. Uiversity Federico 7 the latchig coditio (O state the thick a low doped - regio is i coductivity modulatio, but i that case we have a much higher coductivity, because i this state both the juctios J ad J are i forward bias ad iject holes from both sides of the - regio. s a cosequece the hole distributio is more flat tha i BJT i saturatio, as idicated i the figure, eve with thicker layers, (more tha 00 µm, as eeded to sustai reverse voltage of several kilovolts, ad the voltage drop V across this layer is still low. V V V3 J J J3 log,p p Uiversity Federico 8

5 V characteristics of the SCR From the previous aalysis, we ca ow uderstad the V characteristics of the SCR. reverse bias (V <0, both J ad J 3 are reverse biased, ad J will sustai the voltage up to his breakdow voltage. forward bias, if we iject a g pulse the turover poit is reduced ad the SCR eters i a egative resistace regio (dashed lie up to the stable O state (latchig state where the voltage drop V O is of the order of that of a sigle / diode. For larger values of, the voltage V of the turover poit gets lower, because a lower voltage is eeded to hold the coditio + (V,. H VO 0 VMX v To brig the SCR from O to OFF state, we must reduce the curret below the holdig value H, (a value quite low respect to the operatig curret. This is ormally doe by revertig the V voltage, as doe for the diode. Uiversity Federico 9 Tur-o dyamics The lay-out of a typical SCR is reported i fig. (a, together with the electrical symbol for the SCR device (fig. (b. For large curret ratigs (up to several kiloamp, the device is usually made o a sigle wafer, as idicated i the figure for a wafer of iches. The small gate area with respect to the large cathode oe (here the cathode lateral legth is about cm, will make a importat issue i the tur-o dyamics, due to the lateral spreadig of the carriers. (a Uiversity Federico (b 0

6 - + (a With referece to the cross-sectio picture durig the tur-o phase, just after the reachig of the turover voltage (fig. a, the high ijectio regio (p>> D i the - regio iitially starts to develop dow the gate cotact area, where the curret iject holes ito the base. - + (b The the coductivity modulatio regio spreads laterally i the large cathode area (fig. b, through the carrier diffusio (there is o large lateral electric field, fillig evetually the whole cathode. Oly at that time the whole - regio will preset a low voltage drop, ad the curret will grow up to the fial trasiet value, because it is equally distributed across the whole cathode area. Uiversity Federico a di/dt limitatio The curret costrictio i the iitial part of the tur-o trasiet poses some limitatio o the curret rise time, that must be ot less tha the time eeded for the coductivity regio to spread across the whole cathode area. f the curret rise time is lower tha this di/dt MX value (usually give i the datasheet, the curret forced ito the SCR will flow oly i the cetral part of the chip, givig rise to a excessive curret desity ad to a strog power dissipatio i that small area, with a uacceptable temperature rise (ad device failure. The speed of the lateral carrier propagatio is about some hudreds of µm/µs, so the curret rise time ca be of the order of hudreds of µs if the lateral cathode dimetio is of some cm. b dv/dt limitatio The limitatio o a dv /dt MX is due to the uwated tur-o that could be caused by a excessively short rise time of the aode voltage, eve if there is o pulse applied (the device should stay i OFF state. Recallig the two BJT model itroduced, if the V has a rapid icrease, the curret C i the off state (eq. 3 is the sum of the leakage curret C0 ad the capacitive curret i C C : C C0 + C C dv /dt. This iduces a extra curret C that has the same effect i the base of Q as a added. The SCR the ca be triggered i O if that displacemet curret is of the order of the eeded for triggerig. The dv/dt limitatio idicated the max allowed voltage rise time that does ot geerate a critical C. Uiversity Federico

7 Tur-o waveforms (a The tur-o dyamics of the SCR is sketched i these plots. Startig from the time t* whe the curret is applied (fig. a, we mist cosider (fig. b: V (b t* td tr ts t D t the delay time t d, that is the time eeded to reach the triggerig coditio ( + ad the turover poit. the rise time t r that is the time eeded to create the high ijectio regio ad the coductivity modulatio ear the gate regio the spreadig time t s that is the time eeded to the spreadig of the high ijectio regio across the cathode area. The miimum gate pulse duratio must be the sum of these three times to allow the full switchig of the SCR. Uiversity Federico 3 Why the SCR ca ot be switched OFF by revertig the gate curret? Whe the gate curret is reversed, it will remove oly the stored charges udereath the gate cotact, as idicated i figure. The oly the lateral part of juctio J will be reverse biased: the spreadig resistace of the thi ad log regio uder the cathode area will give rise to a trasverse voltage drop that will keep i forward bias most part of the cathode/gate J juctio. The the SCR will cotiue to stay i its latchig coditio, despite of the reverse gate curret applied. The oly way to switch off the SCR, as said before, is to reduce the aode curret below the holdig value H. J J Uiversity Federico 4

8 Tur-off waveforms (a t The tur-off dyamics of the SCR whe the aode voltage (ad curret is reverted, is similar to the oe of the diode, because both devices rely o the atural curret commutatio (the aode voltage must be reverted to switch off the device. (b V t trr t t3 t4 t The curret the start to decrease below the H value ad the reverse (fig. a. The stored charges i the wide - regio must recombie ad at time t 3 the curret reaches its miimum value. The V voltage first reduces below the V O (fig. b ad the start to icrease i reverse bias whe the curret reaches it miimum (the - regio start to be depleted from mobile charge. Uiversity Federico 5 The ate Tur-Off Thyristor (TO The TO is basically a SCR with the capability to beig switched off eve with positive aode voltages, with a egative gate curret pulse applied; it is switched o (aalogously to the SCR with a positive gate curret pulse. The electrical symbol of the TO is reported i figure, where the bidirectioal gate curret is idicated. The O state characteristic ad the tur-o behavior is equal to the oe of the SCR so we will cocetrate o the tur-off capability of this device. The tur-off ca be iitially idetified i a approximate way by usig the two complemetary BJT cofiguratio see before for the SCR. Recallig the previous aalysis doe, the latchig state is maitaied by the regeerative feedback actio of the two trasistors Q ad Q coected i curret loop. To ihibit the regeerative actio we must brig the trasistor Q out from saturatio usig a egative gate curret ; i the active regio the collector juctio (J of Q will become reverse biased ad the egeerative feedback is blocked. The coditio for Q to exit from saturatio is: C > where β (6 B β Uiversity Federico 6

9 Recallig the schematic for the two trasistors equivalet, we have: B C ' ' C ( Substitutig (7 i (6 we have: ' > ' > ( β ad from the value of β : ( ( + > ' (7 β OFF E Q C B E Q CB where a tur-off curret gai: β OFF ' + ca be defied. Uiversity Federico 7 From the simplified oe-dimesioal aalysis made with the two trasistor equivalet, i priciple it will be possible to tur-off the SCR, but with the usual values of ad the turoff β is about, ad we eed to switch off the device a gate curret equal to the aode oe. Moreover, this aalysis eglect the trasverse voltage drop due to the base spreadig resistace that iibit the SCR tur-off. We eed to chage the gate ad cathode structure i order to a icrease the value of the trasistor, so to have a tur-off β 0, ad b reduce the base spreadig resistace. The mai chage is to resort to a iterdigitated structure for the gate ad cathode cotacts, as schematically idicated i the TO cross sectio. The cathode is raised above the gate, ad its lateral width W C is cotaied, ad the gate is cotacted by a ier metallizatio plae. s a result the TO is made of may elemetary cells as idicated. W C Uiversity Federico TO cross-sectio 8

10 gate cathode aode gate w With referece to the elemetary cell structure of the TO, we ca do the followig commets: a the gate cotact is obtaied by etchig the top surface after ad + dopig o the whole wafer; i this way the cathode has a high periphery/area ratio ad the charge removal from the cathode regio is more effective b the dopig ad thickess of the gate layer are chose to obtai a quite high value ad a tur-off β of about 0. c the aode regio is made of alterate + ad + regios (the + with a lower area tha the + oe: the + layers are amed aode shorts because they act as localized short circuits across the aode juctio J 3. Their role is to allow a faster removal of the stored charge i the - regio ad to reduce the tur-off time. Uiversity Federico 9 TO tur-off The tur-of dyamics is sketched i this figure, with referece to the elemetary cell of the TO. t the begiig of the tur-off trasiet, the egative gate curret removes the stored charge from the gate area far from the cathode regio. The high ijectio regio with p ad carriers the cocetrates below the cathode area, ad subsequetly it shriks dow due to the carrier removal through the gate lateral regio, util the / - juctio (collector juctio of the Q becomes reverse biased, ad the regeerative feedback betwee Q ad Q is blocked. Uiversity Federico 0

11 The aode shorts - i the aode layer help i removig the stored charge accumulated ear the aode juctio that would be otherwise blocked by the / juctio. The the recovery time is reduced ad the switchig speed is icreased. s for the diode, the dyamics of the tur-off is depedet also from the lifetime i the low doped regio: the combied effects of the lifetime cotrol ad of the aode shorts are beeficial i the recovery time reductio, but are egative o the o-state voltage V O i forward coductio: as a result a trade-off relatio betwee the reverse recovery losses ad forward steady-state losses ca be defied for ay TO (ad SCR device, likig the best choice of the relevat parametersa to the specific applicatio (high frequecy operatio or low frequecy/high curret operatio. t must be oted that the aode shorts will pose a sigificat limitatio i the TO ratigs with respect to the SCR oes: the TO ca ot withstad reverse voltages (cotrarily to the SCR because the J juctio is shorted by the + shorts, ad ca ot sustai reverse bias. sd a cosequece, the TO ca be used oly as a cotrolled switch for positive aode voltages. Uiversity Federico