ELEC 350 Electronics I Fall 2014

Transcription

1 ELEC 350 Electroics I Fall 04 Fial Exam Geeral Iformatio Rough breakdow of topic coverage: 0-5% JT fudametals ad regios of operatio 0-40% MOSFET fudametals biasig ad small-sigal modelig 0-5% iodes (p-juctio diodes zeer diodes) 0-5% asic differece amplifiers istrumetatio amplifiers ad CMRR 0-5% C imperfectios i op amps (iput bias curret iput offset voltage) See the Course Outcomes sectio of the Course escriptio page at the ELEC 350 web site for a more detailed list of specific competecies that are likely to be assessed. The fial exam will take place 3:30-6:30 pm o Tuesday ecember 6 i reakiro 66 [day of week ad locatio corrected /3/04]. The exam will be desiged to be approximately.5 hours i legth but you will have the full three hours to complete it. You will be allowed to use up to four 8.5 x -ich two-sided help sheets ad a o-wireless eabled calculator such as a TI-99. There are o restrictios o the material you may place o the help sheets except that they must be etirely hadwritte. Please ote that all help sheets will be collected at the ed of the exam but will be retured to you later if you wish to have them back. The fial exam score caot be dropped. Solutios to the fial exam will ot be posted but you may review your fial exam ad discuss it with me after it has bee graded. Review Topics for Fial Exam The followig is a list of topics that could appear i oe form or aother o the exam. Not all of these topics will be covered ad it is possible that a exam problem could cover a detail ot specifically listed here. However this list has bee made as comprehesive as possible. You should be familiar with the topics o the previous review sheets i additio to those listed below. Although every effort has bee made to esure that there are o errors i this review sheet some might evertheless appear. The textbook is the fial authority i all factual matters uless errors have bee specifically idetified there either by the authors (i the form of published errata) or by me. You are ultimately resposible for obtaiig accurate ad authoritative iformatio whe preparig for your exam. etermiatio of MOSFET regio of operatio - try to determie gate voltage if possible; helps to rule out (or ot) cut-off regio - assume MOSFET is i oe regio ad aalyze the circuit based o that assumptio - check all voltages ad currets ad determie whether or ot their values are cosistet with the iitial assumptio. If so aalysis is complete. If ot use the results of the iitial aalysis to determie likely regio of operatio. Repeat aalysis uder ew assumptio ad cofirm. of 6

2 iasig MOSFET circuits - cocept of biasig ad why it is ecessary - parameters k k p ad V t decrease with icreasig temperature (strog depedece) - desig for quiescet output voltage drai curret ad/or voltage drop across source resistor - usually bias MOSFET for operatio i the saturatio regio if it s used as amplifier - must pay attetio to swig rage of v to avoid cutoff ad triode regios o i cutoff regio i = 0; this is also true at the boudary betwee the cutoff ad saturatio regios o saturatio-triode boudary defied by (for NMOS devices): V VG sat. triode t or (equivaletly) VS sat. triode V t - parameter-idepedet biasig (source degeeratio) or 4-resistor biasig V R A I R R V G + V V R S 0 t ad V VG RS simultaeously o square-law relatioship sometimes leads to solutio of quadratic equatios o must determie which solutio to quadratic equatio is the physical solutio VG t o exact solutio: I krs G t RS krs krs o desig rules of thumb: I R RS V ad 3 V R k o must satisfy I.5k G S t but V value could be explicitly specified which could mea I R V 3 o establishmet of gate bias voltage simplified because I G = 0: R VG V where R is the lower resistor (b/w gate ad groud) RA R - biasig usig a drai-to-gate feedback resistor icludig variat with gate-to-groud resistor - gate biasig resistors should be i the M rage or several 00s of k to avoid excessive curret draw from power supply ad to avoid loadig dow sigal source applied to amplifier s iput C blockig capacitors - act as ope circuits at C - act as short circuits (or have sufficietly low reactace) at sigal frequecies - isolate C biasig from effects of sigal source ad/or load of 6

3 Geeral small-sigal modelig - defiitio of icremetal sigal or small sigal (fluctuatios are a small fractio of bias level) - separatio of bias cosideratios (quiescet levels; output voltage swig rage) from small-sigal cosideratios (gai iput ad output resistace) - for small-sigal (AC) aalysis o replace C voltage sources with short circuits (because voltage across a C voltage source ca t chage; alterative reaso: a 0-V source is a short) o replace C curret sources with ope circuits (because curret through a C curret source ca t chage; alterative reaso: a 0-A source is a ope) o replace large capacitors with short circuits (if capacitive reactace is isigificat at operatig frequecy) o replace small capacitors with ope circuits (if capacitive reactace is eormous at operatig frequecy) o replace large iductors with ope circuits (if iductive reactace is very large at operatig frequecy) o replace small iductors with short circuits (if iductive reactace is isigificat at operatig frequecy) - C voltage sources are typically bypassed at AC (i.e. at sigal frequecy) usig large capacitors to esure that the source acts as a AC groud. - small-sigal model of MOSFET comprised of g m ad r o is oly valid whe device operates i the saturatio regio - small-sigal model of drai-to-source path represeted by r S is oly valid whe MOSFET operates i the low-v S triode regio - small-sigal model of MOSFET i cut-off regio cosists of ope circuits betwee all termials (gate source drai) - derivatio of small-sigal voltage gai v o /v i or (v o /v sig ) - simplificatios ca sometimes be made i gai expressios whe oe term is much greater/smaller tha aother term Small-sigal modelig of MOSFET amplifier circuits - gate-source path modeled as a ope circuit - small-sigal trascoductace g m i o basic defiitio: g m ; ca also be derived from v v v k k I id k gs t t t vgs k k t k t v gs id k t vgs g mvgs where v gs << (V V t ) ad g m = k (V V t ) o equivalet formulas (these are for NMOS devices; similar for PMOS): I g m kvov k t ki V where k k W L C ox W L o derivatios of these formulas - effect of source degeeratio resistor (R S ) o gai 3 of 6 t v gs

4 - icremetal drai-source resistace r o o represets o-zero slope of i -v S characteristic i the saturatio regio due to chael-legth modulatio (sometimes referred to as the Early effect although that term techically applies oly to JTs) o i-v characteristic i saturatio regio that icludes : i kv OV v S vov kv OV vs where v OV = v V t o chael-legth modulatio parameter: VA OV VA where V A = Early voltage o r o is typically 0-00 k for MOSFETs but ca be much lower for some types o r o is ot equal to r S of MOSFET i low-v S triode regio! VA o ro I I Commo-source (CS) ad commo-drai (source follower) amplifiers - commo refers to termial coected either directly to groud or to groud through a few resistors capacitor ad maybe iductors. Sigal source ad load are coected to other termials (directly or idirectly) ot idicated as commo. - CS amps ad source followers ca be biased i multiple ways; i.e. the biasig etwork does ot determie the amplifier s omeclature Iteral structure of bipolar juctio trasistor (JT) - p: thi p-type base sadwiched betwee -type emitter ad collector - pp: opposite of p - base-emitter (E) ad collector-base (C) juctios are regular p juctios ad act the same way (i.e. they ca be forward or reverse-biased; they have tur-o voltages) - JTs ca be modeled as back-to-back diodes (base is the ode b/w diodes) JT circuit symbols - pay attetio to directios of arrows (arrow idicates the emitter termial ad JT type; arrow of p is ot poitig i ) p C E pp C p vs. pp JTs - v E ad v CE of p JTs have positive values i ormal operatio - v E ad v CE of pp JTs have egative values i ormal operatio (use v E ad v EC which are positive istead) - i ad i C flow ito base ad collector termials of p JTs ad out of base ad collector termials of pp JTs - i-v characteristics of p ad pp JTs have voltages of opposite sig Qualitative uderstadig of operatio of JT - tur-o voltage (V F ) of base-emitter juctio (approx. 0.7 V for Si) - effect of chagig base curret i - effect of chagig collector-emitter voltage v CE (ormally C juctio is reverse biased or at least ot heavily forward biased; ecessary for collector curret to flow) - directios ad polarities of importat currets ad voltages (i i C i E v E v CE ) 4 of 6 E

5 - thi base regio required to allow electros (p) or holes (pp) to flow from emitter to collector - emitter more heavily doped tha base allows base to fill with miority carriers (electros for p; holes for pp) whe base curret flows - base-emitter juctio is forward biased if v E is at tur-o voltage (V F ) - i-v characteristic of E juctio is the same as that of a p-juctio diode: v E V i T Se where I S = saturatio curret of E juctio = emissio coefficiet (typically assumed to equal oe) ad V T = thermal voltage which is give by T V T where T = temperature i kelvis (V T = 5 mv at room temp.) collector-base juctio is usually reverse biased (produces depletio regio) or lightly forward biased - collector curret related to base curret by i C = i i the active regio where = forward C curret gai (values are typically but vary amog JT types eve amog idividual uits of a give type withi the same maufacturig batch; varies strogly with temperature) JT i-v characteristic (i C vs. v CE for selected values of i ) - cut-off regio (v E < V F where V F = tur-o voltage of E juctio; i = i C = 0) - active (costat-curret) regio (v E = V F i C = i v CE > V) - saturatio regio (v E = V F v CE V ad i C < i but i C is ozero) Geeral aalysis techiques for JT circuits - determiatio of regio of operatio (cutoff active or saturatio) o try to determie if base-emitter juctio is forward biased if possible; helps to rule out (or ot) cut-off regio o assume JT is i oe regio ad aalyze the circuit based o that assumptio o check all voltages ad currets ad determie whether or ot their values are cosistet with the iitial assumptio. If so aalysis is complete. If ot use the results of the iitial aalysis to determie likely regio of operatio. Repeat aalysis uder ew assumptio ad cofirm. - v CE (for p JTs) is always positive (egative for pp; i.e. v EC is positive) - v E 0.7 V (for Si p) i the active ad saturatio regios - i cut-off regio i = i C = 0 ad v E < 0.7 V (for Si p) - i active regio v E 0.7 V i C = i ad v CE > v CE sat V - i saturatio regio v E 0.7 V i C < i ad v CE = v CE sat V - for more accurate aalysis (rarely ecessary) use v E V i T Se where I S = saturatio curret = emissio coefficiet (typically assumed to equal oe) ad V T = thermal voltage JT iverter circuits - ca be used as logical NOT gates - trasfer characteristic (v o vs. v i ) has egative slope i active regio ad early zero slope i cut-off ad saturatio regios - JT iverter is also called a commo-emitter amplifier - has a almost liear trasfer characteristic i active regio 5 of 6

6 Four-resistor JT biasig circuit V CC V CC R C R C R V C equiv. to R V C R V E V + V E R E R E - for aalysis purposes ca represet base biasig etwork by a Thévei equivalet circuit cosistig of: V R VCC R R ad R R R simplifies evaluatio of I - desig for quiescet output voltage collector curret ad/or voltage drop across emitter resistor (if preset) - usually bias JT for operatio i the active regio - the parameter has strog temperature depedece ad device variatio - egative feedback via emitter degeeratio resistor stabilizes I C - curret through R ad R is typically desiged to be 0. to times I E (or 0-00 times I ) - resistors R ad R do ot behave as a true voltage divider because I 0; however they approximate a voltage divider because I should be small compared to curret through R ad R (/0 or less) - trade-off: higher curret through R ad R leads to more stable quiescet poit but lower iput resistace ad higher curret demad from power supply - commo desig rule of thumb: I C RC E RE VCC although the voltage across R E 3 is sometimes desiged to be less tha this (if V set to V CC /3) - variatio for bipolar (pos./eg.) power supplies: use R E ad R C but oly a sigle resistor (R ) from base to groud Relevat course material: HW: #8 Labs: #6 Textbook: Sectios Lecture otes: Source egeeratio iasig for iscrete MOSFET Amplifiers Web Liks: (oe) Mathcad: (oe) Matlab: (oe) 6 of 6