Performance and Analysis with Power Quality improvement with Cascaded Multi-Level Inverter Fed BLDC Motor Drive

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1 Iteratioal Joural of Recet Advaces i Egieerig & Techology (IJRAET) Performace ad Aalysis with Power Quality improvemet with Cascaded Multi-Level Iverter Fed BLDC Motor Drive 1 N. Raveedra, 2 V.Madhu Sudha 1 Dept. of Electrical & Electroics Egieerig, Malla Reddy Egieerig College for Wome,Hyderabad, TS, Idia. 2 Dept. of Electrical & Electroics Egieerig, KSRM COLLEGE OF ENGINEERING, KADAPA(Dt); AP, Idia. Abstract- The multilevel iverters has become popular i recet years for high-power applicatios. Various topologies ad modulatio strategies have bee ivestigated for utility ad drive applicatios i the literature. The THD cotets i output voltage of iverters is very sigificat idex as the performace of drive depeds very much o the quality of voltage applied to drive. The THD depeds o the switchig agles for differet uits of multilevel iverters. I this paper multilevel coverter fed BLDC drive with differet voltage levels are cosidered ad simulatio results are preseted i terms of total harmoic distortio (THD) ad dv/dt stress. The simulatios have bee carried out i MATLAB ad Simulik. Keywords- BLDC Drive, Cascaded H-bridge (CHB), Multilevel Iverter, LSPWM, PSPWM Modulatio Scheme, THD. I. INTRODUCTION Brushless DC motors with trapezoidal Back-EMF have several iheret advatages. Most promiet amog them are high efficiecy ad high power desity due to the absece of field widig, i additio the absece of brushes leads to high reliability, low maiteace ad high capability. However i a practical BLDC drive, sigificat torque pulsatios may arise due to the back emf waveform departig from the ideal. As well as commutatio torque ripple, pulse width modulatio (PWM) switchig. Torque ripple due to the curret commutatio is caused by the mismatches betwee the applied electromotive force ad the phase currets with the motor electrical dyamics. It is oe of the mai drawbacks of BLDC drives. These torque ripples produces oise ad degrade speed-cotrol characteristics especially at low speed. Due the power electroic commutatio, the usage of high frequecy switchig of power devices, Imperfectios i the stator ad the associated cotrol system. The iput supply voltage to the motor cotais various harmoics compoets. Durig its operatio, high frequecy compoet preset i the iput voltage will cause Electromagetic Iterferece (EMI) problem. Fig. 1 BLDC Motor with Cascaded H-bridge MLI Nowadays researchers are tryig to reduce the torque ripple ad harmoic compoet i the BLDC motor. A active topology to reduce the torque ripple is sychroous motor preseted i [1]. This paper discusses the hysteresis voltage cotrol method. The torque ripple is miimized usig PWM switchig is preseted i paper [2], this scheme has bee implemeted usig a PIC microcotroller to geerate modified pulse width modulatio (PWM) sigals for drivig power iverter bridge. I paper [3] the curret cotroller method is used for reducig the torque ripple ad harmoics. This method is based upo the geeratio of the quasi-square wave armature curret. To reduce torque ripple the idirect positio detectio is used i [4], it is based o the detectio of the zero crossig poits of the lie voltage measured at the termial of the motor. The proposed MLI fed BLDC drive is shows i Fig.1 to miimize the total harmoic distortio (THD) ad dv/dt stress by usig the cascaded H-bridge MLI proposed i this paper. The various topologies are used for the multilevel iverters. Amog this the most commoly used topologies are eutral-poit-clamped (NPC), flyig capacitors (capacitor clamped), ad cascaded H-bridge (CHB) with separate dc sources. I additio, several modulatio ad cotrol strategies have bee developed or adopted for multilevel iverters icludig the followig: multilevel siusoidal pulse width modulatio (SPWM). ISSN (Olie): , Volume-3, Issue -9,

2 Iteratioal Joural of Recet Advaces i Egieerig & Techology (IJRAET) II. ABOUT CASCADED H-BRIDGE MLI TOPOLOGY A three-phase structure of a m-level cascaded iverter is illustrated i Fig.2. Each separate dc source (SDCS) is coected to a sigle-phase full-bridge, or H-bridge, iverter. Each iverter level ca geerate three differet voltage outputs, +Vdc, 0, ad Vdc by coectig the dc source to the ac output by differet combiatios of the four switches, S1, S2, S3, ad S4. To obtai +Vdc, switches S1 ad S4 are tured o, whereas Vdc ca be obtaied by turig o switches S2 ad S3. By turig o S1 ad S2 or S3 ad S4, the output voltage is 0. The ac outputs of each of the differet full-bridge iverter levels are coected i series such that the sythesized voltage waveform is the sum of the iverter outputs. The umber of output phase voltage levels m i a cascade iverter is defied by m = 2s+1, where s is the umber of separate dc sources. A example phase voltage waveform for a 11-level cascaded H-bridge iverter with 5 SDCSs ad 5 full bridges is show i Figure 3. The phase voltage va = va1 + va2 + va3+ va4 + va5. For a stepped waveform such as the oe depicted i Figure 3 with s steps, the Fourier Trasform for this waveform follows: From (1), the magitudes of the Fourier coefficiets whe ormalized with respect to Vdc are as follows: (2) The coductig agles, θ1, θ2,..., θs, ca be chose such that the voltage total harmoic distortio is a miimum. Geerally, these agles are chose so that predomiat lower frequecy harmoics, 5th, 7th, 11th, ad 13th, harmoics are elimiated. III. BLDC MODEL The BLDC motor is a AC sychroous motor with permaet magets o the rotor (movig part) ad widigs o the stator (fix part). Permaet magets create the rotor flux. The eergized stator widigs create electromaget poles. The rotor (equivalet to a bar maget) is attracted by the eergized stator phase, geeratig a rotatio. By usig the appropriate sequece to supply the stator phases, a rotatig field o the stator is created ad maitaied. This actio of the rotor - chasig after the electromaget poles o the stator - is the fudametal actio used i sychroous permaet maget motors. The lead betwee the rotor ad the rotatig field must be cotrolled to produce torque. This sychroizatio implies kowledge of the rotor positio. (1) Fig.2. Three-phase structure of a multilevel cascaded H-bridges iverter Fig.4: A 3-Phase Sychroous Motor with a Sigle Permaet Maget Pair Pole Rotor O the stator side, three phase motors are the most commo. These offer a good compromise betwee precise cotrol ad the umber of power electroic devices required to cotrol the stator currets. For the rotor, a greater umber of poles usually create a greater torque for the same level of curret. O the other had, by addig more magets, a poit is reached where, because of the space eeded betwee magets [10] [12], the torque o loger icreases. The maufacturig cost also icreases with the umber of poles. As a cosequece, the umber of poles is a compromise betwee cost, torque ad volume. The BLDC Motor Cotrol: Fig.3. Output phase voltage waveform of a 11-level cascade iverter with 5 separate dc sources. The key to effective torque ad speed cotrol of a BLDC motor is based o relatively simple torque ad ISSN (Olie): , Volume-3, Issue -9,

3 Iteratioal Joural of Recet Advaces i Egieerig & Techology (IJRAET) Back EMF equatios, which are similar to those of the DC motor. The Back EMF magitude ca be writte as: Ad the torque term as (3) (4) Where N is the umber of widig turs per phase, l is the legth of the rotor, r is the iteral radius of the rotor, B is the rotor maget flux desity, ω is the motor s agular velocity, i is the phase curret, L is the phase iductace, θ is the rotor positio, R is the phase resistace. IV. SEVERAL MODULATION SCHEMES May PWM techiques were developed to cotrol the power iverter gai, ad tried to improve the iverter operatio, based o miimum harmoic cotets i the output voltage. They are quite popular i idustrial applicatios. I that PSPWM ad LSPWM methods are merely preferred by may idustrial applicatios. A. Phase Shifted Pulse Width Modulatio Scheme (PSPWM) Phase shifted PWM (PS-PWM) is used with cascaded H-bridge (CHB) ad flyig capacitor (FC) iverters, sice each cell is modulated idepedetly usig siusoidal uipolar PWM ad bipolar PWM, respectively, providig a eve power distributio amog the cells. A carrier phase shift of /m for the CHB ad of /m for the FC is itroduced across the cells to geerate the stepped multilevel output waveform with lower distortio (where m is the umber of cells). The differece betwee the phase shifts ad the type of PWM (uipolar or bipolar) is because oe CHB cell geerates 3-level outputs, while oe FC cell geerates two level outputs ad also used for may levels as show i Fig.5. the same frequecy f c ad the same peak-to-peak amplitude A C. The zero referece is placed i the middle of the carrier set. The modulatig sigal is a siusoid of frequecy f m ad amplitude A m. At every istat, each carrier is compared with the modulatig sigal. Each compariso switches the switch "o" if the modulatig sigal is greater tha the triagular carrier assiged to that switch. Fig.6 LSPWM Scheme V. MATLAB MODELING AND SIMULATION RESULTS Here simulatio is carried out i differet cases, i that 1). Cascaded H-bridge five level Iverter Fed BLDC Motor Employig Phase shifted carrier PWM techique 2). Cascaded ie level H-bridge Multi level Iverter Fed BLDC Motor Employig phase shifted carrier PWM techique. Case 1: Cascaded H-bridge Multi level Iverter Fed BLDC Motor Employig Phase shifted carrier PWM techique Fig.5 PSPWM Scheme B. Level Shifted PWM Scheme (LSPWM) Level shifted PWM (LS-PWM) is used for cotrollig voltage of a diode clamped multilevel iverter. The cotrol priciple of the level shifted SPWM is to use several triagular carrier sigals keepig oly oe modulatig siusoidal sigal. For a three level iverter two carriers ad for a five level iverter, four triagular carriers are eeded. I geeral if a m-level iverter is Fig 7: Matlab/Simulik Circuit of the Phase Shifted MLI fed BLDC motor Fig.7 shows the Matlab/simulik diagram of BLDC Motor which is fed from the Cascaded H-bridge Multi level Iverter Usig phase shifted carrier PWM techiques. employed, (m-1) carriers are eeded. The carriers have ISSN (Olie): , Volume-3, Issue -9,

4 p p p Iteratioal Joural of Recet Advaces i Egieerig & Techology (IJRAET) Fig.12 Electromagetic Torque of the BLDC Motor Fig.8 Phase Voltages of Phase Shifted Multi Level Iverter The Fig.8 shows the three phase voltages of the MLI, which are displaced by 120 degrees apart. Fig. 10, 11 ad 12 represets the Back emf, speed ad Electromagetic torque of the BLDC motor respectively operated uder Phase Shifted Modulatio Scheme. Fig 13 THD of the Phase Shifted MLI output Voltage Fig 9: Back Emf s of the BLDC Motor Fig.13 shows the THD of the Cascaded H-bridge Multilevel Iverter Employig Phase shifted carrier PWM techique, attai 21.72% as a distorted value. Case2: Cascaded ie-level H-bridge Multi level Iverter Fed BLDC Motor Employig phase shifted carrier PWM techique. scope DC 1 DC 3 DC 5 Scope2 Step Tm <Stator curret is_a (A)> Gai full bridge full bridge1 full bridge2 A B m <Stator curret is_b (A)> ea -K- I2 C <Stator curret is_c (A)> Brushless DC Motor <Stator back EMF e_a (V)> Subsystem DC 2 DC 4 DC 6 Gai1 full bridge full bridge1 full bridge2 <Stator back EMF e_b (V)> <Stator back EMF e_cv)> N (rpm) eb -K- I2 DC 8 DC 9 <Rotor speed wm (rad/s)> -Krad2rpm Fig Phase Stator Curret s of BLDC Motor (5- level) Scope1 Gai2 Subsystem1 full bridge3 Scope3 DC 10 DC 7 full bridge4 DC 11 full bridge5 DC 12 v + - v + - v + - <Electromagetic torque Te (N*m)> <Hall ef f ect sigal h_a> ea eb ec Te (N.m) ec -K- I2 full bridge6 full bridge7 full bridge8 <Hall ef f ect sigal h_b> Subsystem2 Discrete, Ts = 5e-005 s. pow ergui <Hall ef f ect sigal h_c> Fig 14: Matlab/Simulik Circuit of the ie level Phase Shifted MLI fed BLDC motor Fig 11 Speed of the BLDC Motor ISSN (Olie): , Volume-3, Issue -9,

5 Iteratioal Joural of Recet Advaces i Egieerig & Techology (IJRAET) Fig 15: Phase Voltages of Phase Shifted Multi Level Iverter Fig 16: Back Emf s of the BLDC Motor Fig Phase Stator Curret s of BLDC Motor (9- level) Fig 18 Speed of the BLDC Motor Fig 19 Electromagetic Torque of the BLDC Motor Fig.16, 18, 19 represets the Back emf, speed ad Electromagetic torque of the BLDC motor respectively operated uder Phase Shifted Modulatio Scheme. Fig 20: THD of the Various Level Shifted MLI output Voltage Fig.20 THD of the Cascaded H-bridge Multilevel Iverter Employig Phase shifted carrier PWM techique attai 12.03%. VI. CONCLUSIONS The multilevel coverters achieve high-voltage switchig by meas of a series of voltage steps, each of which lies withi the ratigs of the idividual power devices. I this paper, a ew iverter topology has bee proposed which has superior features over covetioal topologies i terms of the required power switches ad isolated dc supplies, cotrol requiremets, cost, ad reliability. This will add up to the efficiecy of the coverter as well as reducig the size ad cost of the fial prototype. The PSPWM cotrol method is used to drive the iverter. The simulatio results of the developed prototype for a ie-level iverter of the proposed topology are demostrated i this paper. The results clearly show that the proposed topology ca effectively work as a multilevel iverter with a reduced umber of carriers for PWM, the proposed coverter applied to BLDC motor drive to check the performace characteristics of drive. REFERENCES [1] C. Govidaraju ad K. Baskara, Aalysis ad implemetatio of multiphase multilevel hybrid sigle carrier siusoidal modulatio, J. Power Electro., vol. 10, o. 4, pp , Jul [2] A. Rada, A. H. Shahiriia, ad M. Falahi, Evaluatio of carrier-based PWM methods for multi-level iverters, i Proc. IEEE ISIE, 2007, pp [3]. K.N.V Prasad, G.Rajith Kumar, T. Vamsee Kira, G.Satyaarayaa., "Compariso of differet topologies of cascaded H-Bridge multilevel iverter," Computer Commuicatio ad Iformatics (ICCCI), 2013 Iteratioal Coferece o, vol., o., pp.1,6, 4-6 Ja [4] Y.-M. Park, H.-S. Ryu, H.-W. Lee, M.-G. Jug, ad S.-H. Lee, Desig of a cascaded H-bridge multilevel iverter based o power electroics buildig blocks ad cotrol for high performace, J. Power Electro., vol. 10, o. 3, pp , May ISSN (Olie): , Volume-3, Issue -9,

6 Iteratioal Joural of Recet Advaces i Egieerig & Techology (IJRAET) [5] K.Lakshmi Gaesh, G. Satyaarayaa, CH. Naredra Kumar, N. Sriivasa Rao Power Quality Improvemet by Usig 7-Level Multistrig APF Iterfacig to Distributio Geeratio Systems, Iteratioal Joural of Egieerig Associates, Vol-1, Issue 3, p.p , Feb, [6] M. Maliowski, K. Gopal kumar, J. Rodriguez, ad M. A. Perez, A survey o cascaded multilevel iverters, IEEE Tras. Id. Electro., vol. 57, o. 7, pp , Jul [7] C. Cecati, F. Ciacetta, ad P. Siao, A multilevel iverter for photovoltaic systems with fuzzy logic cotrol, IEEE Tras. Id. Electro., vol. 57, o. 12, pp , Dec [8] G.-J. Su, Multilevel dc-lik iverter, IEEE Tras. Id. Appl., vol. 41, o. 3, pp , May/Ju [9] J.-S. Lai ad F. Z. Peg, Multilevel covertersa ew breed of power coverters, IEEE Tras. Id. Appl., vol. 32, o. 3, pp , May/Ju [10] C. A. C. Cavaliere, E. H. Wataabe, ad M. Aredes, Multi-pulse STATCOM operatio uder ubalaced voltages, i Proc. IEEE Power Eg. Soc. Witer Meetig, 2002, vol. 1, pp ISSN (Olie): , Volume-3, Issue -9,