Chapter 3 Digital Logic Structures

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1 Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. Computig Layers Chapter 3 Digital Logic Structures Problems Algorithms Laguage Istructio Set Architecture Microarchitecture Origial slides from Gregory Byrd, North Carolia State Uiversity Modified slides by Chris Wilco, Colorado State Uiversity Circuits Devices CS270 - Sprig Semester Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. Trasistor: Buildig Block of Computers Microprocessors cotai lots of trasistors Itel 8086 (978): 29 thousad Itel 8086 (982): 55 thousad Itel (985): 275 thousad Itel (989):. millio Itel Petium (993): 3. millio Itel Petium II (998): 7.5 millio Itel Petium III (200): 45 millio Itel Petium 4 (2006): 84 millio Itel Core 2 Duo (2006): 29 millio Itel Quad Core i7 (20):. billio Itel 8-core Xeo (202): 2.3 billio CS270 - Sprig Semester CS270 - Sprig Semester 206 4

2 Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. Trasistor: Buildig Block of Computers Logically, each trasistor acts as a switch Combied to implemet logic fuctios (gates) AND, OR, NOT Combied to build higher-level structures Multipleer, decoder, register, memory Adder, multiplier Combied to build simple processor LC-3 CS270 - Sprig Semester Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. Simple Switch Circuit Switch ope: Ope circuit, o curret Light is off V out is +2.9V Switch closed: Short circuit across switch, curret flows Light is o V out is 0V Switch-based circuits ca easily represet two states: o/off, ope/closed, voltage/o voltage. CS270 - Sprig Semester Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. -type MOS Trasistor MOS = Metal Oide Semicoductor two types: -type ad p-type -type whe Gate has positive voltage, short circuit betwee # ad #2 (switch closed) whe Gate has zero voltage, ope circuit betwee # ad #2 (switch ope) Termial #2 must be coected to GND (0V). Gate = Gate = 0 Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. p-type MOS Trasistor p-type is complemetary to -type whe Gate has positive voltage, ope circuit betwee # ad #2 (switch ope) Gate = whe Gate has zero voltage, short circuit betwee # ad #2 (switch closed) Termial # must be coected to +2.9V. Gate = 0 CS270 - Sprig Semester CS270 - Sprig Semester

3 Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. Physical Trasistor Trasistor Output (Ideal) Logic aalyzer view of waveforms CS270 - Sprig Semester CS270 - Sprig Semester Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. Trasistor Output (Actual) Propagatio Delay Each gate has a propagatio delay, typically fractio of a aosecod (0-9 sec). Delays accumulate depedig o the chai of gates the sigals have to go through. Clock frequecy of a processor is determied by the delay of the logest combiatioal path betwee storage elemets, i.e. cycle time. Actual waveform is ot ideal! CS270 - Sprig Semester 206 CS270 - Sprig Semester

4 Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. Logic Gates Use switch behavior of MOS trasistors to implemet logical fuctios: AND, OR, NOT. Digital symbols: recall that we assig a rage of aalog voltages to each digital (logic) symbol assigmet of voltage rages depeds o electrical properties of trasistors beig used typical values for "": +5V, +3.3V, +2.9V from ow o we'll use +2.9V CMOS Circuit Complemetary MOS Uses both -type ad p-type MOS trasistors p-type Attached to + voltage Pulls output voltage UP whe iput is zero -type Attached to GND Pulls output voltage DOWN whe iput is oe For all iputs, make sure that output is either coected to GND or to +, but ot both! CS270 - Sprig Semester CS270 - Sprig Semester Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. Iverter (NOT Gate) Logical Operatio: OR ad NOR A B OR A B NOR Iputs: 2 or more I Out 0 V 2.9 V 2.9 V 0 V I Out 0 0 Output=A+B Output=A+B CS270 - Sprig Semester CS270 - Sprig 6 Semester 206 4

5 Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. AND ad NAND Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. NOR Gate (OR-NOT) A B AND A B NAND Iputs: 2 or more A B C 0 0 Output = AB Output = AB Note: Serial structure o top, parallel o bottom. 0 CS270 - Sprig 7 Semester 206 CS270 - Sprig Semester Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. OR Gate A B C Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. NAND Gate (AND-NOT) Add iverter to NOR. A B C Note: Parallel structure o top, serial o bottom. 0 CS270 - Sprig Semester CS270 - Sprig Semester

6 Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. AND Gate A B C Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. Basic Logic Gates Add iverter to NAND. CS270 - Sprig Semester CS270 - Sprig Semester Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. Boolea Algebra Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. Boolea Algebra Laws = 0 = = 0 +0 = + = + = CS270 - Sprig 23 Semester 206 Remember Idetify, Domiatio, Negatio Laws from Logic! 0 Commutative A+B = B+A AB = BA Associative A+(B+C)=(A+B)+C = A+B+C A(BC)=(AB)C = ABC Distributive A(B+C)=AB+AC A+(BC)=(A+B)(A+C) CS270 - Sprig 24 Semester 206 6

7 Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. Some Useful Idetities for simplificatio AB+AB = A Proof: AB+AB = A(B+B) // Distributive Law = A(T) // Negatio Law = A // Idetity Law A+AB = A Proof: A+AB = A(+B) // Distributive Law = A() // Domiatio Law = A // Idetity Law Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. DeMorga's Law Covertig AND to OR (with some help from NOT) Cosider the followig gate: A B A B A B A B Same as A OR B! To c ov ert AND t o OR (or vice versa), ivert iputs ad output. CS270 - Sprig 25 Semester 206 CS270 - Sprig Semester Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. More tha 2 Iputs? AND/OR ca take ay umber of iputs. AND = if all iputs are. OR = if ay iput is. Similar for NAND/NOR. Ca implemet with multiple two-iput gates, or with sigle CMOS circuit. Summary MOS trasistors are used as switches to implemet logic fuctios. -type: coect to GND, tur o () to pull dow to 0 p-type: coect to +2.9V, tur o (0) to pull up to Basic gates: NOT, NOR, NAND Logic fuctios are usually epressed with AND, OR, ad NOT DeMorga's Law Covert AND to OR (ad vice versa) by ivertig iputs ad output CS270 - Sprig Semester CS270 - Sprig Semester

8 Copyright The McGraw-HillCompaies, Ic. Permissio required for reproductio or display. Buildig Fuctios from Logic Gates Combiatioal Logic Circuit output depeds oly o the curret iputs stateless Sequetial Logic Circuit output depeds o the sequece of iputs (past ad preset) stores iformatio (state) from past iputs We'll first look at some useful combiatioal circuits, the show how to use sequetial circuits to store iformatio. CS270 - Sprig Semester