VLSI Implementations of Threshold Logic A Comprehensive Survey

Transcription

1 BEIU, QUINTANA, AVEDILLO: VLSI IMPLEMENTATION OF THRESHOLD LOGIC 1 VLSI Implemetatios of Threshold Logic A Comprehesive Survey Valeriu Beiu, Seior Member, IEEE, José M. Quitaa, ad María J. Avedillo Abstract This is a i-depth review paper o silico implemetatios of threshold logic gates, coverig several decades (i.e., from the early days till ow). The paper starts by describig early MOS implemetatios followed by differet VLSI solutios icludig: capacitive (switched capacitor ad floatig gate with their variatios), coductace/curret (pseudomos ad output-wired-iverters icludig a plethora of solutios evolved from them as well as may differetial solutios), ad shortly metios other implemetatios (e.g., based o egative resistace devices ad o sigle electro techologies). Idex Terms Itegrated circuits, eural etwork hardware, threshold logic, VLSI. I. INTRODUCTION RESEARCH o eural etworks (NNs) goes back sixty years ago. The semial year for the developmet of the sciece of mid was 1943 whe the article A Logical Calculus of the Ideas Immaet i Nervous Activity by Warre McCulloch ad Walter Pitts was published [13]. They itroduced the first, very simplified, mathematical model of a euro operatig i a all-or-oe fashio: the threshold logic (TL) gate (TLG). It computes the sig of the weighted sum of its iputs: f ( x 1, K, x ) = sg( w1x1 + K + w x θ) = sg w i x i θ (1) i= 1 w i beig the syaptic weight associated to x i, θ the threshold, ad the fa-i of the TLG. It did ot take too log for a hardware implemetatio to be developed. I 1951 Marvi Misky teamed with Dea Edmods ad desiged the first 40-euro eurocomputer Sark [14]. Although it was a electro-mechaical implemetatio built of tubes, motors, ad clutches, it successfully modeled the behavior of a rat searchig for food i a maze. I 1957 Frak Roseblatt geeralized the McCulloch-Pitts euro ivetig the perceptro [20]. Durig Draft: September 15, 2002 V. Beiu is with the School of Electrical Egieer ad Computer Sciece, Washigto State Uiversity, Pullma, WA , USA (phoe: +1 (509) ; fax: +1 (509) ; vbeiu@ eecs.wsu.edu). J.M. Quitaa ad M.J. Avedillo are with the Cetro Natioal de Microelectróica (CNM), Uiversty of Sevilla, Edificio CICA, Avda. Reia Mercedes s/, Sevilla, Spai (phoe: +34 (95) , fax +34 (95) , {josem, avedillo}@imse.cm.es) ad 1958, Roseblatt together with Charles Wightma ad others costructed ad successfully demostrated the Mark I Perceptro. The Mark I Perceptro had 512 adjustable weights implemeted as a array of potetiometers. Because of the successful presetatio of the Mark I Perceptro, the eurocomputig field became a subject of itesive research. Shortly afterwards, Berard Widrow together with his studets developed aother type of eural computatioal elemet: the ADALINE (ADAptive LINear Elemet) [21]. They used a electrically adjustable resistor called a memistor. This ca be cosidered the first electrical implemetatio of threshold logic circuits (TLCs), i.e. circuits made of TLGs. Widrow also fouded the first eurocomputer hardware compay: Memistor Corporatio, producig eurocomputers durig the early to mid 1960s. More details ca be foud i Nils Nilsso s book Learig Machies [17]. The eurocomputer idustry was bor. The geeral belief that a euro is a threshold elemet (or TL elemet, or TLG), which fires whe some variable reaches a threshold, ca be questioable as to whether such a drastic simplificatio ca be justified. For aswerig that, the precise four-dimesioal euro model of Hodgki ad Huxley has bee used, ad the threshold model has bee tested o a spike trai geerated by the Hodgki-Huxley model with a stochastic iput curret. The result was that the threshold model correctly predicts early 90% of the spikes, justifyig the descriptio of a euro as a TLG [11]. I the last decade the tremedous impetuous of VLSI techology has made eurocomputer desig a really lively research topic. Research o hardware implemetatios of NNs i geeral, ad TL i particular, has recetly bee very active. While there is a large body of literature o hardware implemetatios of NNs (see for example Part E: Neural Network Implemetatios i [2], ad the may refereces therei), to the kowledge of the authors there are o up-todate review papers o hardware implemetatios of TL sice [10] ad [7]. Books o TL have bee writte some time ago [9], [16], with oly oe recet chapter as a exceptio [1]. Particular TL implemetatios usig either currets [4], or a few capacitive solutios [3], [18], are the exceptio rather the the rule, ad they have covered oly particular subclasses of solutios. Eve more, aoelectroics devices like those based o sigle electro techology (SET) or o egative resistace devices (NRDs) e.g., resoat tuellig devices (RTDs) have ot bee icluded [6], [15], [19]. Besides, there are may theoretical results showig that TLCs are more

2 BEIU, QUINTANA, AVEDILLO: VLSI IMPLEMENTATION OF THRESHOLD LOGIC 2 powerful/efficiet tha classical BCs. These have bee aother motivatio to ivestigate various VLSI implemetatios. Oe importat aspect for NNs is their adaptive behaviour, but i this i-depth review paper we shall focus oly o the may differet approaches that have bee tried for implemetig TL i silico. Effectiveess of TL as a alterative for moder VLSI desig is determied by the availability, cost ad capabilities of the basic buildig blocks. I this sese, may iterestig circuit cocepts for developig stadard-cmos compatible TLGs have bee explored. As the umber of differet proposed solutios ad fabricated chips reported i the literature is o the order of hudreds, we caot metio all of them here. Istead, we shall try to cover importat types of architectures ad preset oly a few represetative examples although some readers might at times disagree with our choice. The paper is structured i four mai Sectios II V. Each of these Sectios is dedicated to a differet desig approach. Sectio II is coverig a few CMOS solutios. Sectio III is dedicated to capacitive implemetatios, dealig both with switched capacitor solutios ad with floatig gate approaches. Sectio IV details may coductace/curret implemetatios startig from pseudo-mos ad the output-wired-iverters. It presets may solutios which have evolved from these two, as well as a large variety of differetial solutios. Fially, Sectio V is dedicated to several other implemetatios icludig those based o SET ad RTD. I most cases the various solutios discussed are sorted chroologically by order of their publicatio date, although i some cases the order would be somehow differet by submissio date. For keepig the paper s legth reasoable, the very early days of TL implemetatios (i.e., whe the techologies were TTL, ECL, I 2 L, ad MOS) will ot be covered. However, it is worth metioig here that there have bee may differet proposals. A few represetative MOS oes are [8] (Fig. 1a), [12] (Fig. 1b), ad [5] (Fig. 2). I coclusios we discuss ad compare the differet implemetatios, ad commet o the future directios of research. II. CMOS SOLUTIONS Most of the early solutios have represeted each distict weighted sum (of iputs) by a aalogue value (voltage or curret). This implies static power dissipatio, which is hardly acceptable aymore. Curretly, low power solutios are at a premium, ad three differet low power CMOS solutios will be detailed further. Probably the first pure CMOS solutio is due to Hampel [22] (Fig. 3). The CMOS devices form a plurality of TLG cofiguratios havig MAJORITY logic fuctios with ear symmetrical switchig delay times. MAJORITY fuctios are TLF havig idetical (uit) weights. Ay TLF ca be represeted as a MAJORITY fuctio by repeatig/complemetig the iputs. Hece, the gate ca implemet arbitrary TLFs by tyig together several iputs. Correspodig gate termials of idividual MOS devices withi the idetical MOS ad pmos complemetary stacks are commoly coected to the iput sigals. The fact that the MOS ad pmos stacks are alike leads to symmetrical switchig delay times. The gate has low power cosumptio ad large oise margis. A variatio of this type of gate ca be foud i almost ay textbook o VLSI: the mirrored adder. The oly disadvatage is that larger fa-i gates are quite slow due to the large umber of series trasistors ad the larger capacitace. Eve more, if implemetig arbitrary TLF, the fa-i is reduced because several iputs have to be tied together for implemetig weights differet from the uit weight. A NULL Covetio Logic (NCL ) gate [24], [25], [26], receives a plurality of iputs, each havig a asserted state ad a NULL state. The TLG switches its output to a asserted state whe the umber of asserted iputs exceeds a threshold umber. The TLG switches its output to the NULL state oly after all iputs have retured to NULL. Sigal states may be implemeted as distict voltage or curret levels. This approach implemets m-of- TLGs with hysteresis. This gate is a geeralizatio of both a Muller C-elemet (-of-) ad a Boolea OR (1-of-) gate. NCL is a asychroous delayisesitive logic desig methodology. Several implemetatios are possible: static (show i Fig. 4), semistatic, ad dyamic. The gate has low power ad large oise margis, beig reasoably fast for small fa-is (the large umber of trasistors i series slows it dow for larger fais). Recetly, aother low power solutio based o a passtrasistor logic style has bee detailed [23]. It offers a attractive alterative to CMOS solutios. I particular, Complemetary Pass-trasistor Logic (CPL) is a well-kow low-power logic desig style. A steerig circuit, which produces all the TLFs for a -iput logic fuctio was preseted i [23]. Weights differet from 1 are implemeted by modifyig the diagoal coectio patter i the steerig circuit (istead of tyig together as may iputs as give by w i ). Fig. 5 shows the steerig logic circuit realizig all the six possible TL fuctios that ca be obtaied with the set of weights [1, 1, 2, 2]. A distiguishig characteristic differetiatig this approach from others TLG realizatios is that pass-trasistor-based oes deped oly o the umber of variables, ot o their associated weights. However, as the CPL-based desig is a class of static pass-trasistor logic, it iherits the problems that are specific to this class of circuits. III. CAPACITIVE IMPLEMENTATIONS The cocept uderlyig capacitive TLGs is the use of a array of capacitors to implemet the weighted sum of iputs. Distict circuits structures have bee proposed which differ i the way the value of the threshold is set, ad i the circuit techiques used to carry out the compariso ivolved i determiig the output value. Capacitive threshold-logic gates

3 BEIU, QUINTANA, AVEDILLO: VLSI IMPLEMENTATION OF THRESHOLD LOGIC 3 ca be classified ito two major groups: Capacitive Threshold Logic (CTL), ad Neuro MOS (νmos), also kow as multi iput floatig gate trasistor (MIFG or MFMOS). Although closely related, these two origial approaches were differet at the begiig: static versus clocked ad differet mechaisms for settig the threshold value, while their curret developmets have become icreasigly similar. Several comparisos [18], ad [3] (see also [33]) draw the followig coclusios: the operatio of the νmos is simpler tha that of the CTL; the maximum fa-i attaiable by νmos is a order of magitude less tha that of CTL gate (the CTL gate is less limited by process variatios); both solutios have large power cosumptios (as the floatig gate voltage of the primary iverter i the comparator chai causes DC curret); the delay has a logarithmic depedece with respect to large fa-is (fa-i 255 i [33], fa-i 64 i [18]), while for small fa-is (fa-i 20 [3]) the behaviour of the ormalized delay looks liear: ( beig the fa-i). A. The switched capacitor Origially itroduced i 1987 the mai idea was to use switched capacitors, switches ad iverters, ad to take advatage of the iheret saturatio of the iverters to implemet the euro o-liearity without additioal elemets [36], [37]. This first approach required a somehow complex three-phase clock, as show i Fig. 6. The priciple of capacitive syapse was preseted also i [27], [28], with the same three-phase clock. It has quickly evolved ito a simpler two-phase clock solutio [33], kow as the capacitive threshold logic (CTL) gate. Its coceptual circuit schematic is show i Fig. 7 for a -iput gate. It cosists of a row of capacitors C i, i = 1, 2,, with capacitaces proportioal to the correspodig iput weight, C i = w i C u, ad a chai of iverters which fuctios as a comparator to geerate the output. This TLG operates with two o-overlappig clock phases Φ R ad Φ E. Durig the reset phase, Φ R is high ad the row voltage V R is reset to the first iverter threshold voltage, while the capacitors bottom plates are precharged to a referece voltage V ref. Evaluatio begis whe Φ E is at a logic 1, coectig the gate iputs to the capacitor bottom plates. As a result, the chage of voltage i the capacitor top plates is give by V = = Ci ( Vi Vref )]/ Ctot where Ctot is the total row R [ i 1 capacitace icludig parasitics. Choosig adequate defiitios for V ref ad C i as fuctios of the iput weight ad threshold values, the above relatioship ca be expressed as [ 1 ( ]. Together with the V R = i wi xi θ) CuVDD / C tot = compariso fuctio of the chai of iverters, this gives the TL operatio: Vo = V DD if i= 1 w i x i θ, ad Vo = GND if i = 1 w i x i < θ. Betwee two cosecutive reset phases, a large umber of iput vectors ca be processed. Experimetal results from differet CTL gates fabricated i stadard-cmos techology [33], [29], [30], [31], have show the proper fuctioality of this type of TLG ad its large fai capability (gates with fa-i = 255 have bee simulated). This later feature is due to the auto-offset cacellatio techique widely used i chopper-type CMOS comparators. Origially, CTL gates required a double-poly process, but some developmets (like dyamic ad differetial CTL [29]) use the MOS cap with a small pealty o the fa-i (fai 64). CTL gates have a simple regular structure, ad are able to implemet large fa-is, while their mai drawbacks are: large delays, large area, DC power cosumptio, ad the threshold value programmig mechaism. The reset time grows quickly with the fa-i of the gate due to the high capacitace ad ca be quite large (thousads of evaluatio phases) [18]. Propagatio delay is logarithmic i the umber of iputs, ad has a strog depedece o the uit capacitor [33]. The estimated area of the uit capacitor is equivalet to several miimum sized iverters, makig the capacitor array area large. Due to the liear operatio of the sese amplifier, the power cosumptio is high. Several developmets proposed for overcomig CTL s limitatios are summarized below. The fact that the threshold value is set by a aalogue referece voltage complicates its itegratio. I additio, each CTL gate may require a differet referece voltage, thus it is practically impossible to build circuits with a large umber of CTL gates. This problem is solved by the improved CTL gate [29] which operates exclusively with biary iput logic levels. Aother solutio to this problem is the Capacitor Programmable CTL gate (CP-CTL) [34], [35], which does ot rely o the presece of additioal exteral voltages. Fig. 8 depicts its circuit schematic. The origial CTL gate is augmeted with a umber of capacitors. The programmig of the gate is ow achieved by settig V ref, V eval1, V eval2, ad V reset to readily available voltage levels. Differet combiatios of GND, V DD ad V DD /2 (programmig method) ca be used. Fially, aother variatio called Balaced-CTL (B-CTL) [32] is show i Fig. 9. The requiremet for a highly precise referece voltage is elimiated by implemetig fuctios with thresholds equal to 0. This is ot a restrictio o the class of TLFs that ca be implemeted, sice ay TLF ca be coverted ito a equivalet TLF with threshold equal to zero by ivertig certai iputs, ad chagig the sig of their associated weights [16]. The basic structure is formed by two baks of capacitors (Bak A ad Bak B i Fig. 9). Both baks are coected to a differetial amplifier that determies which bak has a larger umber of iputs at logic oe. That bak has a higher voltage level o its commo lie. This gate implemets TLFs, with thresholds equal to zero, if the iputs havig positive weights are coected to oe bak ad the iputs havig egative weights are coected to the other oe. Oe additioal half capacitor ubalaces the voltage level at the amplifier iputs i case both baks have a idetical

4 BEIU, QUINTANA, AVEDILLO: VLSI IMPLEMENTATION OF THRESHOLD LOGIC 4 umber of high-level iputs. B-CTL gates operate from oe clock that switches the gate betwee two states: reset ad evaluate. B-CTL gates are reported to be faster tha CIAL gates [122] (to be described i Sectio IV.D). Their mai characteristics are high fa-i ad low power cosumptio. B. The euro-mos trasistor Neuro-MOS (νmos) TLGs are based o the νmos trasistor [54]. This trasistor has a buried floatig polysilico gate ad a umber of iput polysilico gates capacitively coupled to the floatig gate (Fig. 10a). The voltage of the floatig gate becomes a weighted sum of the voltages o the iput gates, ad cotrols the curret i the trasistor chael. The most simple νmos-based TLG is the complemetary iverter usig both pmos ad MOS νmos devices [55], [56], [57], [58]. A schematic of this TLG is show i Fig. 10b. The floatig gate is commo to both the pmos ad MOS trasistors, ad the iput gates correspod to the TLG iputs x 1, x 2,, x. The weights are proportioal to the ratio betwee the correspodig iput capacitace C i (betwee the floatig gate ad each of the iput gates), ad the total capacitace (icludig the trasistor chael capacitace) betwee the floatig gate ad the substrate C cha. Without usig the extra cotrol iputs, the voltage i the floatig gate is give by VF = ( i = 1Ci Vx ) / Ctot, where C. i tot = Ccha + i = 1Ci Whe VF becomes higher tha the iverter threshold voltage, the output switches to logic 0. I the case of the simple static νmos, the gate s threshold is adjusted via additioal threshold-settig capacitors. It is obvious that this νmos TLG is very simple ad very compact. However, there are a umber of problems. Degradatio i the log-term stability is aticipated due to the use of a floatig gate. Sesitivity to parasitic charges i the floatig gate ad to process variatios could limit its effective fa-i, uless adequate cotrol is provided. I particular, ultraviolet light erasure is required for iitializatio/reprogrammig. Static νmos gates have DC power cosumptio, ad differet schemes have bee proposed to alleviate at least some of these problems. I the clock-cotrolled νmos TLG [48], [49], a clockdrive switch is attached to the floatig gate to iitialize the floatig-gate charge (reset phase). This switch short-circuits the floatig gate ad the iverter output, thus biasig the iverter at the most sesitive poit of the ivertig characteristics (see Fig. 11). This is the same auto-offset cacellatio techique used for CTL gates (ad i chopper type CMOS comparators). At the same time, each iput capacitors is fixed to either GND or V DD, such that the logical threshold of the gate is correlated with the physical threshold of the iverter. This meas that, i each reset phase, the floatig-gate charge is refreshed, avoidig the problems due to parasitic capacitaces ad log-term stability. The iverter threshold is also automatically readjusted, reducig the sesitivity to process ad ambiet parameters variatios, ad icreasig the fa-i of the gates. As a example, static νmos TLGs for MAJORITY with up to 9 iputs are possible (typically the fa-i of a static νmos is limited by 12), while clocked νmos ca reach up to 30 iputs. The gate is ot very fast: a euro with 32 syapses of 5-bit accuracy i 0.8 µm CMOS exhibit delays i the 3 17 s rage [50]. The same cocept is used i Cotrolled Floatig-Gate Devices (CFGDs) [38]. These dyamic versios have relatively high static power ad might require multiple phase clocks. The static power cosumptio of the basic νmos TG ca be elimiated, ad its speed icreased, by a curret compariso betwee a νmos trasistor ad a referece device, usig a positive feedback circuit. May differet cofiguratios takig advatage of this cocept have bee reported [48]. Oe example is the cofiguratio called seseamplifier νmos TL [49] (Fig. 12a). It applies a curretcotrolled latch-sese amplifier circuit to the basic νmos TLG. Variatios ca be foud i [60], [61], followed by several patets [59], [62], [51], [52] (Fig. 12b). They use a solutio similar to the digital comparator based o the clockcoupled iverters itroduced i [123] (this is a differetial coductace solutio to be described i Sectio IV.D). I [61], sigificat speed improvemets (100 MHz to 500 MHz) ad power savigs for the νmos gate from Fig. 12a over the static νmos gate are reported. I [52] a very thorough aalysis with respect to parameter variatios, amely couplig capacitaces of the floatig gate ad the sesig amplifiers of νmos TLGs usig a dyamic comparator latch for sesig, is carried out. The domiat mismatch origiates from the iput offset voltage variatios of the sesig circuits. Measured results show that the most critical compoets are the comparators circuits. Improved oise margis ca be traded off for icreased layout areas ad icreased power cosumptio (due to icreased capacitaces). The coclusio is that this is a problem that will be exacerbated by future CMOS techologies, sice lower supply voltages ad icreased device mismatch will have a dimiishig effect o the threshold widow, sesig margis, sigal to oise ratio, ad reliability. I additio, it is claimed that a careful compariso with the area cosumptio of a stadard CMOS logic circuit is absolutely ecessary, ad that the use of νmos gates is ot always advisable. However, they explicitly metio that there are applicatios where floatig gate MOS devices ca be employed advatageously, like TLCs with low logic depth implemeted i fault tolerat architectures requirig high fuctioal desities (e.g., data processig architectures i image sesors). Aother variatio, called CMOS Capacitor Couplig Logic (C 3 L), uses the capacitor couplig techique ad a curret sese amplifier [45] (Fig. 13). Although these circuits do ot have a offset cacellatio mechaism, fluctuatio i device parameters ca be compesated by the differetial cofiguratio. Fig. 14a shows the structure of aother TLG based o a charge recyclig differetial sese-amplifier. It is called

5 BEIU, QUINTANA, AVEDILLO: VLSI IMPLEMENTATION OF THRESHOLD LOGIC 5 charge recyclig threshold logic (CRTL) gate [42], [41]. The iputs are capacitively coupled oto the floatig gate of trasistor M 5, ad the gate voltage of trasistor M 6 sets the threshold. A CRTL gate has two operatio phases cotrolled by a sigle-phase clock. Whe E is high the output voltages are equalized. Whe E is high, the outputs are discoected ad the differetial circuit (trasistors M 5, M 6 ad M 7 ) draws differet currets from the OUT ad OUT. The sese amplifier is activated ad amplifies the differece of potetial betwee OUT ad OUT, acceleratig the trasitio. Thus, it evaluates if the weighted sum of the iputs is greater or less tha the threshold. It is based o a charge recyclig asychroous sese differetial amplifier (ASDL) [46], [47]. The symmetry of the layout is importat. CRTL gates exhibit high-speeds, ad are suitable for high fa-is, while also havig low power cosumptio. I fact, CRTL gates achieve the highest speed ad 15-20% lower power cosumptio whe compared with clocked νmos [49], C 3 L [45], ad LCTL [118] (to be described i Sectio IV.D). CRTL gates have bee tested for process variatios at 45 corers, ad seem to be robust. A 4-bit carry look-ahead adder usig CRTL gates with fa-i up to 9, was implemeted i a 0.25 µm double poly CMOS process [41]. It rus at MHz at V DD = 2 V, dissipatig MHz. Very recetly, a ovel self-timed threshold logic (STTL) has bee proposed [43], [44]. The self-timig idea comes from asychroous circuits, the goal beig to elimiate the clock ad thus reduce power cosumptio (a self-timed power-dow mechaism applied to coductace TLGs [94], [95], [96], [98] will be detailed i Sectio IV.C). The gate is based o the cross-coupled MOS trasistor pair, M3 ad M4 (Fig. 14b). Precharge ad evaluate are specified by a eable sigal: E ad E. Two curret mirrors are used M8-M1 ad M9-M2. Because the capacitaces of ode A ad B have to be matched, the two bufferig iverters have to be idetically sized. The eable sigals E ad E are geerated from the outputs ad passed to the ext stage, beig propagate i a selftimed fashio. The solutio is low-power (as beig differetial), ad elimiates the clock at the expese of a double-rail sigallig ad the additioal eable geerate block. It is too early to say if the power reductio due to the elimiatio of the clock ad its distributio is off-balaced by the eable geerate block required by each gate. Obviously, low power solutios have to be used i desigig this block. The oly results reported so far are for a (7,3) couter, a fudametal buildig block for biary multipliers (used for reducig the partial products). I a 0.25 µm double poly CMOS, the (7,3) couter has a delay of 1.4 s ad dissipates V whe drive by a 300 MHz eable sigal. IV. CONDUCTANCE / CURRENT IMPLEMENTATIONS A. Early solutios The first coductace/curret based implemetatios of TLG s were made i the mid-1950 s usig resistive circuits. Later, bipolar realizatios [8], [12], [66] were proposed, ad MOS solutios followed [5] (see Fig. 2). I this sectio we shall discuss two early TL solutios i CMOS 1), which time has proved to be edurig: the pseudo-mos (also kow as grouded-pmos), ad the output-wired-iverters (also kow as gaged CMOS). The MOS techology was suitable for high fa-i gates. A depletio MOS trasistor was used as a load (pull-up), makig NOR gates very fast (the pull-dow etwork has oly parallel trasistors). I CMOS, the solutio was to use a pmos with its gate grouded. This is the pseudo-mos (also kow as grouded pmos) solutio: fast, havig DC power, ad usig ratio rules. The reduced output voltage swig ad gai makes the gate more susceptible to oise. That is why, istead of just groudig the pmos load, its curret should track the MOS device (makig the gate less sesitive to process variatios), e.g., by usig a curret mirror. This also accelerates the rise time. I time critical sigal paths, pseudo-mos logic wisely combied with static CMOS, led to substatial speed improvemets at the cost of oly slightly icreasig the power cosumptio. Furthermore, because the gate of the pull-up pmos trasistor ca be tured off, pseudomos supports a power-dow mechaism at o extra cost. Large fa-i gates with very fast switchig times ad almost without static power ca be built. Oe last advatage of such gates is their low trasistor cout. The ratio rules make it possible to implemet TLFs, but these TLGs exhibit all the advatages ad disadvatages metioed above. I the particular case of pseudo-mos TLG, the oise margis are reduced as the commo output ode has meaigful aalog voltages. That is why these gates are limited to small fa-i values ad a iverter is used both for bufferig ad for recoverig the voltage. The secod solutio is based o a plurality of iverters with their outputs hard-wired together. The first TLG implemetatio based o output-wired-iverters followed by a recoverig buffer iverter (see origial drawig i Fig. 15a) was detailed i 1973 by Lerch [71]: A threshold gate comprisig a plurality of complemetary-symmetry, fieldeffect trasistor iverters, each iverter receivig at its commo gate coectio a differet iput sigal ad each coected at its output termial to a commo circuit output termial [aother iverter]. The gate may have iputs all of the same weight or, with appropriately chose values of trasistor coductio chael impedace or parallel coected iverters, may have iputs of differet weight. It produces a o-liear voltage divider that drives a restorig iverter (or a chai of iverters) whose purpose is to quatize the o-biary (aalogue) sigal at the commo ode v g. Fig. 1) These are ot pure CMOS solutios like those detailed i Sectio II.

6 BEIU, QUINTANA, AVEDILLO: VLSI IMPLEMENTATION OF THRESHOLD LOGIC 6 15b shows the circuit structure for these output-wirediverters TLGs. Each iput x i drives a ratioed CMOS iverter with oly oe trasistor coductig at a time (because the iput is either logic 1 or 0 ). Both the pmos ad the MOS trasistors are operated as resistors (coductace). That is why the voltage o v g depeds o how may pmos ad MOS trasistors are coductig, beig proportioal to i =1 w i x i. The output iverter is desiged to switch whe this sum is greater tha θ, ad as a output buffer for recoverig the sigal. It also provides additioal drivig capability. The desig process for these threshold gates ivolves sizig oly two differet iverters [70]. Assumig the same legth for all the trasistors, the widths [Wp, W ] i,b for each iverter are chose takig ito accout the permissible sum of the weights i = 1 w i ad the θ value to be implemeted. Oly positive ad iteger weight ad threshold values are allowed whe usig this techique. Still, this is ot a limitig factor because ay TLG ca be implemeted usig oly positive iteger weights ad threshold. Moreover, o-uit weight values w i = k > 1 ca be realized by simply coectig i parallel k basic iverters (oe iverter correspodig to w i = 1). The threshold value θ is determied by the output iverter s threshold voltage V th. The v g ode is effectively isolated from exteral circuitry, thereby toleratig some local oise. Ufortuately, due to the sesitivity of the voltage o v g ad of the V th of the output iverter to process variatios, the output-wired-iverter TLGs are fa-i limited. A good study of this limitatio ca be foud i [63], while i [69] upper ad lower bouds o the chael width ratio were obtaied aalytically. These prove that process variatios ad operatig coditios drastically limit the fa-i. A differet approach for the determiatio of the W/L-ratios of the trasistors uses a evolutioary algorithm [65]. Still, these TLGs are extremely fast, while exhibitig high power cosumptio (assumable whe traded-off for speed), as well as arrow oise margis. Two very similar solutios were shortly proposed [64], [76]. Afterwards, output-wired-iverters TLGs have bee rediscovered several times. I [67], a very fast CMOS NOR gate is preseted which is Lech s costructio [71] without the fial restorig iverter. Later, Schultz et al. [75] rediscovered Lerch s origial costructio [71], ad called it gaged-cmos logic (GCMOS), the ame uder which it became well-kow. The desig was exteded to multiplevalued logic [74]. The output-wire-iverters techique has bee employed to build TLCs for o-liear filterig [68], [69], [70], Muller C-elemets [73], Losq s voters with multithreshold TLGs [73], or TLCs for D flip-flops [72]. Both pseudo-mos ad output-wired-iverters solutios are very fast. By the time they were itroduced, the DC power cosumptio was ot such a striget cocer/limitatio as it is today. Eve more, the higher supply voltage made their reduced oise margis acceptable for TLGs with small fais. As a example of that era, output-wired iverters implemetig NOR fuctios with 2 ad 3 iputs have bee used i the MIPS R2010, the FPU of MIPS R2000 [67]. Both solutios have represeted the startig poits of two log series of variatios/modificatios, which made icremetal ehacemets o their two major drawbacks: the DC power cosumptio ad their reduced oise margis. A almost exhaustive eumeratio follows i the ext two sectios. B. Beyod pseudo-mos The DC power cosumptio was the major drawback of pseudo-mos gates whe implemetig BL, while oise margis became a cocer oly whe the gates were used to implemet TL. As may applicatios have focused o very fast BGs, pseudo-mos was a attractive alterative. Especially for large fa-i they are much faster tha equivalet CMOS gates (slowed dow by log series of trasistors). That is why a lot of effort has bee devoted to reducig the power cosumptio of large fa-i (wide) pseudo-mos gates (e.g., implemetig NOR fuctio). Although TLGs are ot always metioed explicitly, the results obtaied are immediately applicable to TLGs. The other drawback, the reduced oise margis, was left uresolved as a ope questio for TL research. The mai idea for reducig the DC power was to replace the pmos load trasistor (which was always o ) with a more or less complex load circuit. Such solutios rely o: usig asychroous feedback ad/or feedforward, reducig the voltage swigs (ufortuately, this reduces the oise margis eve more), usig a clock sigal (dyamic solutios), usig cotrolled curret mirrors, or eve data-depedet solutios. As we shall see, combiatios of several of such techiques have also bee proposed. The origial pseudo-mos has DC curret i 2 1 of the 2 possible states (where is the fa-i of the gate), beig a data-depedet DC power cosumptio. For uiformly distributed radom iputs, a approximatio is give by the ratio (2 1)/2. Eve for relatively small fa-i values, this ratio is close to 1, ad will be cosidered as 100% DC power. The data-depedet DC power cosumptio of the differet solutios will be estimated as a percet of this 100% DC power, or the exact percet will be give whe kow. Oe of the first solutios is due to [88] (see Fig. 16a). It is a pseudo-mos desig with feedback: a iverter receives the output of the gate ad drives the pmos load. O average, the power is reduced to 50% (supposig that the output is also a uiformly distributed radom variable). This solutio is ow cosidered as grated ad icluded i may textbooks. A similar solutio was preseted later by Raza ad Nazaria [84], the mai differeces beig that the feedback loop has two iverters (istead of oe), ad that a additioal referece voltage was used to cotrol a secod parallel load trasistor. A solutio for a MAJORITY gate usig a curret load was preseted i [85]. A othreshold logic (NTL) was derived from its bipolar couterpart [92], beig by that time speedcomparable to I 2 L ad ECL. The power-delay product is

7 BEIU, QUINTANA, AVEDILLO: VLSI IMPLEMENTATION OF THRESHOLD LOGIC 7 early the same as that of covetioal CMOS operated at high frequecies. Reduced voltage swigs decrease the power cosumptio, but also degrade the oise margis. A ehacemet over [88] is detailed i [91] (Fig. 16b). It is a high speed low power dissipatio, all parallel FET logic circuit. The basic improvemet is that the iverter is used both for cotrollig the active pull-up (load) trasistor, as well as recoverig the voltage ad bufferig the output. The output is recovered by a iverter, ad latched through the pmos load. The voltage trasfer fuctio of the iverter is deliberately skewed for improvig the speed. O average the power is reduced to 50% (as i the previous solutios). A multigate serial load trasistor may further reduce power cosumptio, ufortuately also slowig dow the gate. A precharged dyamic (clocked) load desig, with feedforward for icreased speed is preseted i [79] (Fig. 17). It has a screeig trasistor (Q20) ad clockig circuitry (Q17, Q18, Q19). The clockig circuitry alterately precharges odes (30) ad (34) to V DD, ad evaluates the voltage o ode (30) to output a logic level. Two latchig trasistors (Q21, Q22) improve the behavior with respect to process variatios ad circuit istabilities. The outputs are buffered by iverters, isolatig ode (30). O average the power is reduced to about 25%. Aother method for reducig the DC curret uses both feedback ad feedforward [83] (Fig. 18a). This desig is selftimed, i.e., it does ot use a clock. This circuit has both a strog (310) ad a weak (309) pull-up pmos. The weak pullup device (309) is always o ad holds the ode high if the pull-dow device is i a off state. However, if the pulldow device is i a o state, the strog pull-up device (310) is also tured o, thereby providig a stable itermediate voltage o the ode. A feedback path from the output (317, 316, 315 ad 314) cotrols the state of the strog pull-up device (310). The feedback path ca be made sesitive to both the temperature of the circuit ad the supply voltage through a cotrol iput (320). The power reductio is difficult to estimate as depedig o the sizig of the trasistors, but should be better tha 50% (probably as low as 25% with a carefully desiged layout). A similar solutio, usig both a weak ad a strog pull-up, is the asychroous high-speed large fa-i NOR gate, ispired by pseudo-nmos ad dyamic desigs, ad itroduced i [93] (Fig. 18b). The basic idea is to use feedback from the output to cotrol the load, ad also to cut the DC curret (Q9B). A regulator (VREF) is coupled to the strog pull-up trasistor (Q7B) for regulatig the drive curret i respose to temperature ad power supply voltage variatios (for maitaiig the speed). Four differet versios allow for: (i) high speed; (ii) reduced voltage swigs o the iputs; (iii) temperature ad voltage compesatio; ad (iv) limited low voltage o the output (usig a feedback techique). Power reductio is difficult to estimate, but should be better tha 50%, while the regulator providig the referece voltage VREF complicates the desig. A method for sigificatly reducig the DC power cosumptio of clocked pseudo-mos (ratioed) gates is preseted i [81], [82] (Fig. 19). A sesig circuit (#1) aalyzes the voltage trasitios of the ratioed ode, ad cotrols the DC curret flow (#2) through the etire circuit. Simulatios have show that DC power is reduced to 14%, makig it oe of the best solutio with respect to DC power reductio (for pseudo-mos/ratioed circuits). A simple improved pseudo-mos desig for miimizig power is described i [80] (see Fig. 20a). The solutio is usig a clock to cotrol a curret mirror. Voltage floatig of the output is also elimiated. O average power is reduced to 50%. Aother more complex versio of the gate uses both a clock sigal (508) ad a power-up sigal (806). The power-up sigal is a delayed versio of the clock sigal ad, together with the feedback from the output, further dimiishes the power cosumptio. This secod solutio (Fig. 20b) is complex ad requires a demadig timig scheme, but could be rewarded by a DC power reductio eve better tha the previous oe ([81], [82]). By far the simplest solutio for reducig the power cosumptio to 50% (o average) is preseted i [89], [90] (see Fig. 21a). This is a data-depedet pseudo-mos gate, the pull-up trasistor beig cotrolled by oe of the iput variables. The idea has bee used also i [87] (see Fig. 21b) for a m-of- TLG [86]. Fially, we metio a hybrid solutio preseted by [77], [78] (see Fig. 22). It correspods to the category of coductace with oe pmos trasistor drive by the threshold ad all the MOS trasistors drive by iputs through floatig gates, i.e., istead of settig the weights by the width to legth ratio (W/L) of the trasistors, the weights are ecoded as charges o the floatig gates. These charges modify the trasistor threshold voltage ad therefore its curret. Hece, weights are programmable ad ca be quadratic or expoetial i the voltage stored o the floatig gate resultig i a large dyamic rage. A 16-iput programmable gate is reported. Programmig is achieved through tuelig ad ijectio of hot electros. The solutio is sesitive to oise, relatively slow, ad has data depedet static power dissipatio, but would allow for larger fa-is. C. Beyod output-wired-iverters Output-wired-iverters suffer from the same disadvatages as pseudo-mos solutios: DC power cosumptio ad reduced oise margis, so solutios for tryig to overcome either oe or the other of these disadvatages have bee o the research ageda for quite some time. A first ehacemet ca be see i Fig. 23. It showed how to coect the iputs oly to the MOS trasistors [103]. It reduces iput capacitace by havig the iput sigals coected oly to the MOS stack. The threshold of the fuctio to be implemeted is set by pre-wirig all the pmos trasistors to either V DD or GND. The solutio slightly icreases the speed due to reduced capacitace, but does ot improve o either power cosumptio or o oise margis.

8 BEIU, QUINTANA, AVEDILLO: VLSI IMPLEMENTATION OF THRESHOLD LOGIC 8 A modificatio to the basic idea was itroduced i [110], [111], where a ew class of logic gates called Source Follower Pull-up Logic (SFPL) is described. The pull-up ad pulldow structures are separated ad coected through a iverter. A high fa-i gate implemeted followig this techique is show i Fig. 24a. The power dissipatio is similar to that of pseudo-mos implemetatios. It is metioed that SFPL has acceptable oise margis. A ehacemet over SFPL is detailed i [108] (see Fig. 24b), ad used i custom comparators to speedup critical stages i a superscalar processor [109]. Other comparators specifically desiged for low-power are described i [107], ad compared agaist SFPL. The origial output-wire-iverters have two trasistors per iput. Usig oly oe trasistor per iput was show for particular BFs i [104], [105], [102], [106], [101]. The formal proof, ad the systematic method o how to desig TLGs havig oe trasistor per iput (either MOS or pmos), led to the β-drive threshold elemet (βdte) [112]. The computig block is a voltage divider (the β-comparator) formed by pmos ad MOS trasistors, ad ca be see i Fig. 25a. The feasibility of such a implemetatio follows from the fact that ay threshold fuctio ca be represeted i a ratio form as: y = sg w i x i θ i= 1 = sg w j x j w j S j S j x j w j x j j S = sg 1 (2) w j x j j S where S is a certai subset of idices such that j S w j = θ. The voltage o ode vβ is determied by the ratio of sums of β s of pmos ad MOS trasistors. A remarkable feature of βdte is that its implemetability depeds oly o the threshold value θ, ad does ot deped o the umber of iputs ad their weights. The βdte solutio reduces the iput capacitace ad the iteral ode capacitace, makig the gate eve faster, but does ot tackle ay of the disadvatages: high power cosumptio ad arrow oise margis. A improved β-comparator havig higher o-liearity i the threshold zoe improves o the oise margi [115], [116] (Fig. 25b). This is achieved usig three additioal highly stable referece voltages (a quite demadig coditio). SPICE simulatios for 0.8 µm CMOS have prove that the fa-i is limited to about 10. Artificial learable euros based o βdtes have also bee reported [113], [114], [116], [117]. Aother method for ehacig the oise margis of TLGs implemeted by a β-comparator is preseted i [94], [95], [96], [99]. The method is data-depedet, beig simpler tha [115], [116]. It adds data-depedet o-liear terms to the βdtes, practically covertig the TLG ito a high order perceptro. The o-liear terms form a oise suppressio logic (NSL), which ca always be determied from the Boolea form of the TLF by subtractig the miterms implemeted by the pmos stack: f NSL = f \ ( j ). S x j Fig. 26a shows the βdte implemetatio of f4 = g i (p i g i 1 ), which ca be expressed as f 4 = sg(2g i + p i + g i 1 1.5). Fig. 26b shows the implemetatio whe the additioal NSL has bee added. By properly sizig the trasistors the oise immuity ca be improved (i.e., better oise margis are traded off for larger area), ad the speed ca be icreased (at the expese of higher DC power cosumptio). NSL has bee tested for gates with fa-i 7. The TLG with NSL implemetig f 4 i 0.5 µm CMOS has a delay of less tha 80 ps at V DD = 3.3 V (whe drivig four idetical gates). A 5- layer 32-bit adder usig f 4, ad three other BFs f 6 = g i (p i g i 1) (p i p i 1 g i 2 ), h 4 = (a i b i ) [(a i b i ) (a i-1 b i 1 )], ad g i:i+3 = g i+2:i+3 (p i+3 p i+2 g i:i+1 ) (see [97], [99], [100]) has bee implemeted usig TLGs with NSL i 0.18 µm CMOS. It achieves a delay of less tha 300 ps dissipatig GHz (ruig cotiuously). For reducig the DC power a data-depedet self-timed power-dow mechaism (STPD) has bee recetly developed [94], [96], [97], [98]. It uses either oe or two additioal trasistors isolatig the gate from V DD ad/or GND (Fig. 27a). Each of these trasistors is drive by a cotrol logic havig as iputs the icomig data, the output of the gate ad a asychroous exteral sigal PW. Oe of the solutios reduces the DC power to about 50% (Fig. 27b), while aother solutio reduces the DC power to about 25% (see [97], [98]). For the 32-bit adder metioed above, the power ca be reduced from 142 mw to GHz. A differetial versio of the STPD has also bee developed (patet applicatio pedig), ad is expected to reduce the power cosumptio to about 10%. It is curretly tested i the desig of a 4-layer 32-bit adder [100]. We aticipate that i 0.18 µm CMOS this adder will have a overall delay of less tha 250 ps, while dissipatig about 11 3 GHz (ruig cotiuously). The power reductio comes both from havig fewer TLGs (tha the 5-layer adder) ad from usig the differetial STPD 2). D. Differetial solutios May of the differetial TLG implemetatios i the curret/coductace category have i commo two parallel coected sets of MOS trasistors implemetig the weightig operatio, ad a curret CMOS comparator for the threshold operatio, e.g., the CMOS cascode othreshold [92]. The mai advatage over the previous solutios is their low power cosumptio (oly dyamic power). The operatio of cross-coupled iverters with asymmetrical loads (CIAL) was exploited to implemet digital bus comparators [123], a particular example of a TLG (see Fig. 28a). At the same time, a geeric latch-type threshold gate (LCTL) was proposed i [118] (Fig. 28b). Its cosists of a 2) All the TLGs used i these adders iclude NSL.

9 BEIU, QUINTANA, AVEDILLO: VLSI IMPLEMENTATION OF THRESHOLD LOGIC 9 CMOS curret-cotrolled latch (trasistors M 2 /M 5 ad M 7 /M 10 ) providig both the output ad its complemet, ad two iput arrays ( M ) ad ( M ) havig a M M equal umber of parallel trasistors whose gates are the iputs of the TLG. Trasistor pairs M1/M 3 ad M 6 /M 8 specify the precharge or evaluate phase, ad two extra trasistors M M esure correct operatio for the case whe the 4 / weighted sum of iputs is equal to the threshold value. Prechargig occurs whe the reset sigal ΦR is at logic 0. M 1 ad M 6 are o, while M 3 ad M 8 off, ad both OUT ad OUT are at logic 1. Evaluatio begis whe Φ R is at logic 1. M 1 ad M 6 are tured off, while M 3 ad M 8 are tured o, ad odes OUT ad OUT begi to be discharged. I this situatio, depedig o the logic values at the iputs of the two trasistor arrays, oe of the paths will sik more curret tha the other. This accelerates the fallig of its correspodig output voltage (either OUT or OUT ). Whe the output ode of the path with the highest curret value falls below the threshold voltage of either M 5 or M 10, it turs it off, fixig the latch situatio completely. Supply curret oly flows durig trasitios ad, cosequetly this TG does ot cosume static power. Iput termial coectios ad iput trasistor sizes i this TLG implemetatio must be established accordig to the threshold value θ to be implemeted. Whe all trasistors ad (i = 1, 2,, ) have the same dimesios ad M 4i the same voltage is applied to their gates, Ii > I ref due to M M 9i The speed performace of this gate is improved by the solutio proposed i [122] where the MOS baks are exteral to the latch (see Fig. 28c), avoidig the large log feedback chai of LCTL. It is called Cross-couple Iverters with Asymmetrical Loads Threshold Logic (CIALTL). Note that i spite of usig the same ame, circuit topologies i [122] ad [123] are differet. I this gate, the iput trasistor arrays ( M M, i = 1, 2,, ) are coected directly to xi y i the latch s output odes, ad prechargig occurs whe Φ1 ad Φ 2 are at logic 0, puttig odes D, OUT ad OUT at logic 1. For the evaluatio phase, both Φ 1 ad Φ 2 are at logic 1, but Φ 2 must retur to a low level before Φ 1 i order to allow the latch to switch. CIALTL eeds two cotrol sigals, which have to be obtaied from a geeral clock. Still, a great deal of power is dissipated i the iteral clock frot ed. The circuit arragemet for realizig logic elemets that ca be represeted by threshold value equatios pateted by Prage et al. [128] is a simplified versio of CIAL (see Fig. 28d). More recetly, a umber of TLGs have bee proposed based o advaced clocked CMOS differetial logic structures by implemetig the pull-dow etwork with two baks of parallel MOS trasistors, istead of usig MOS complemetary logic trees. Examples are: Sigle Iput Curret-Sesig Differetial Logic (SCSDL) [131], [132] after the Curret Sesig Differetial Logic (CSDL) [124]. Fig. 29 shows its schematic for a geeric pull-dow tree ad the circuit structure for a -iput MAJORITY gate. Differetial Curret-Switch Threshold Logic (DCSTL) [125], [126], [127] (Fig. 30) after the Differetial-Curret Switch Logic (DCSL) [129], [130], a Differetial Cascove Voltage Swig (DCVS) approach which restricts the voltage swig of the iteral odes for lowerig the power cosumptio. DCSTL requires a sigle clock. Reported experimets from a 31-iput AND show that DCSTL exhibits better power-delay product tha the other two latch-based TLG implemetatios described above: LCTL [118] ad CIALTL [122]. Curret-Mode Threshold Logic (CMTL) [119] also uses two baks of parallel trasistor for iputs ad threshold followed by sesig. Low power is achieve by limitig the voltage swig o itercoects ad the iteral odes of the CMTL gates. Various clocked cross-coupled loads have led to Discharged CMTL (DCMTL) ad Equalized CMTL (ECMTL). These TLGs based o curret comparisos are relatively sesitive to oise ad mismatch of process parameters. Clearly, icreasig the umber of iputs reduces the allowed mismatch. Reliability ca be improved by kow layout ad circuits techiques where the devices behaviour is matched (substrate voltage cotrol, shield ad isolatios, layout of trasistors with the same orietatio, use the same size for trasistors, i.e., use multiple smaller trasistors coected together to realize a larger device with reduced statistical parameter variatios). Yield cosideratios limit the fa-i. As a example, yield aalysis for SCSDL implemeted i 0.35 µm CMOS showed that the fa-i 14 [131], [132]. All the solutios detailed above fall uder oe of the followig two cases: either compare the sum of weights with a threshold [128], [132], [119], or compare two weighted sums [123], [118], [122]. For the secod case, additioal trasistors are eeded to differetiate whe the two weighted sums are equal. A slightly better solutio (patet applicatio pedig) is to implemet fuctio f with oe bak, while implemetig f with the other. It is well kow that ivertig a TL fuctio requires oly to ivert the iputs ad to chage the threshold. The fact that f ad f always have trasitios i opposite directios leads to icreased speed ad better oise margis. By usig the NSL scheme both for f ad f oe ca do eve better. Fially a coceptually differet implemetatio is proposed i [120], [121]. The key computatioal cocept is to use a floatig-gate device as a programmable-switched coductace. By storig oe aalogue value as the threshold of a floatig gate device ad applyig a secod digital value o the gate of the device, the coductace ca be either zero or a pre-programmed aalogue value. These coductaces store the weights associated to each iput. Fig. 31 depicts the