DESIGN OF A COFFEE VENDING MACHINE USING SINGLE ELECTRON DEVICES

Transcription

1 1 Iteratioal Symposium o Electroic System Desig DESIGN OF A COFFEE VENDING MACHINE USING SINGLE ELECTRON DEVICES (A example of sequetial circuit desig) Biplab Roy (1), ad Biswarup Mukherjee () Dept. Of Electroics ad Commuicatio Istitute of Techology ad Marie Egieerig, West Begal, Idia (1) biplabroy@ieee.org, () biswarup8@gmail.com Abstract I this paper we propose a implemetatio techique for sequetial circuit usig sigle electro tuelig techology (SET-s) with the example of desigig of a coffee vedig machie with the goal of gettig low power ad faster operatio. We implemet the proposed desig based o sigle electro ecoded logic (SEEL).The circuit is tested ad compared with the existig CMOS techology. Keywords- SED; coulomb blockade; SEEL I. INTRODUCTION It is well kow that i desigig a sequetial circuit [1], oe has to go through the steps- i) drawig state trasitio graph ii) sate assigmet iii) combiatioal logic sythesis iv) The circuit realizatio usig a specific techology. The techology has so far bee the CMOS oe for low power operatio. But it is expected to be limited i further power ad/or area reductio. To overcome that recetly various device architectures have bee proposed with Sigle electro tuelig devices (SET-s) as the most studied oe for future low power devices. Sigle electro devices work o the priciple of Coulomb Blockade [] to trasfer a sigle electro charge ad provide a alterative way to realize digital logic. The SET devices have got the advatages of fast ad low power operatio because they use oly oe electro to do logic ad arithmetic operatios. Sigle electro trasistors ad memories have already bee proposed [3, 4] though the replacemet of the CMOS Compoets have ot yet bee possible. I this paper, we desig a coffee vedig machie as a example to implemet sequetial circuit usig sigle electro devices to achieve low power ad faster operatio. The example is take because of its critical power requiremet II. SET JUNCTION Sigle electro tuelig devices are ow really cosidered as elemets for future devices because of their small size, high speed, ad low power cosumptio. The devices work o the priciple of tuelig pheomea.the most importat oe beig the Sigle Electro Trasistor is a three termial device. From the costructioal poit of view it ca be see as electro islad that has two separate juctios for electro etrace & exit of a sigle electro with two gates attached to it. Oe gate tues the voltage of the whole system whereas aother cotrols the umber of electros comig i ad out of the islad oe at a time. The coductio process is solely based o Coulomb-blockade priciple The device is made operatioal by overcomig the critical voltage Vc of a tuel juctio give by [5]. V c =q/[(c e +C j )] (1) where Cj is the capacitace of tuel juctio ad Ce is the equivalet capacitace viewed from the juctio s perspective ad q is the electro charge. The tuelig evet (flow of a electro through a tuel juctio) beig a stochastic process takes time (also called switchig delay) Td give by [5] Td = [-l(p error )q e R t ]/[ Vj -Vc] () where q e =1.6x1-19 C, ad R t = the resistace of the juctio ad requires the eergy Es give by E s =e[ V j -V c ] mev (3) For circuit desig usig SET devices, two differet architecture is used. Oe beig the CMOS/SET hybrid architecture provides high voltage gai & drivig ability whereas sacrificig low power feature of SETs partially. The /1 $6. 1 IEEE DOI 1.119/ISED

2 other is the SET oly architecture. Here we proceed with the secod oe where the charge trasport through the juctio is essetially cosidered to be of oe electro. III. SEEL(SINGLE ELECTRON ENCODED LOGIC) It is the digital logic, where 1 is represeted by oe electro charge (the presece of oe electro) ad beig the absece of the electro. So here, curret beig the flow of oly oe electro, the power cosumptio ca be expected to be low. I this architecture, the threshold logic scheme is reported [6, 7] where a geeric threshold logic gate is the mai buildig compoet ad is show i fig 1(b). I this gate, the critical voltage Vc acts as the threshold. If the voltage across the tuel juctio is made higher tha this, oe electro ca tuel through the juctio to/from the output termial, thus represetig / 1. the voltage of poit x is icreased by the iput voltage Vp weighted by their iput capacitors Cp ad similarly the voltage of poit y is cotrolled by the V iputs thus decreasig the juctio voltage with the directio take as show. Ad Vb sets the iitial coditio. The symbol of this Threshold-Logic-Gate(LTG) is show i fig.1(a),where x1,x....x are the iputs, ω1, ω ω are the weights of the correspodig iputs ad φ deotes the threshold uit value. Usig this scheme, with the weights set properly ay two dimesioal logic ca be implemeted ad with mare tha oe such gates actig together ca implemet more complex fuctios. It has bee reported [7] that the gate show i fig 1(b) aloe does ot work well due to loadig effect. To get better performace, buffer is geerally coected with it ad oe buffer agai implemeted with SET devices is show i fig. 1(c) (ad its symbol i fig. 1(d)) which ca also act as a stad aloe iverter. (c) V i V Figure 1. (a) Symbol of threshold logic gate (b) circuit of threshold logic gate (c) SET -buffer / iverter (d) symbol of SET -buffer / iverter IV. DESIGN OF A COFFEE VENDORING MACHINE A coffee vedig machie ca be desiged with the help of several BDD devices which i our case are SED-s. For that we start with the statemet:- To get a cup of coffee out of the machie, oe should first press Reset butto (which is ot the must). The he/she should put i either Rs 1 or Rs or Rs 5 or Rs 1 cois to make a total of Rs 5 which is the cost of a cup of coffee. If oe gives extra amout he/she will get back the balace(here it is Rs1 / Rs 5) together with the coffee with the optio of resettig the machie ay time. With this statemet we draw the state diagram:- (d) Figure. state diagram (a) (b) 39

3 Now except the case of iput D=coi uit of 1 & actios to be take for Reset butto, the cases for other three types of iputs are cosidered & they are tabulated i the State table (Table I): (The cases for i/p D & Reset butto are cosidered separately i the fial desig & also will be explaied there. I the State table the iput combiatios other tha those give i the table are cosidered that they will ot occur). The successive procedure of (i)gettig state trasitio table (ii) drawig K-maps leads to the expressios for the iputs of the flip-flops used (here we have used D FF-s) to get the iteral states as give i equatios (4-8) TABLE I. STATE TABLE PS I/P-s NS O/P-s C B A C R 1 S S S 1 S 1 S 1 S S 1 S 5 S 1 S 1 S 1 1 S S 1 1 S 3 S S S 1 S 3 S 1 S 4 S 3 S 3 S 3 1 S 4 S 3 1 S 5 S 4 S 4 S 4 1 S 5 S 4 1 S 6 S 5 S 1 S 6 S 1 1 S 7 S S =, S 1 =1, S = S 3 =3, S 4 =4, S 5 =, S 6 =6, S 7 =7 D = Q ( C+ Q AC) + QCAQ ( + Q1 ) = D1+ D+ D3+ D4 (4) D 1 = BQ + QQ 1AB + QQ 1 AC + QQQ 1 AC = D11 + D1 + D13 + D (5) 14 D = CQ + QQQ 1 + BQQ 1+ QQQ 1 AC = D1+ D+ D3+ D4 (6) C = QQQ 1 + QQQ 1 + D= C1+ C+ C3 (7) R = QQ (8) 1 1Q Ad we have Retur coi of 5 uit (R5) = D for the same reaso that if oe gives a coi of 1 uit the he should get a coi of 5 uit as retur. After gettig the expressios for all those iteral variables & the o/p variables i terms of the iputs as well as iteral state, we proceed to get SEEL gate circuits for D, D1,D iteral iput lies for the three D-FFs used ad also the three output lies of the cotroller (C,R1,R5). For that, the idividual compoets of D, D 1, D as give i equatios (4),(5) ad (6) are implemeted first ad the they are OR-ed to get the D-s (the correspodig gates are show i figure 3(a-l & q)) as proposed i [8]. Similarly the C ad R 1 (as give i equatios (7) & (8)) are implemeted (show i figure 3(m-p)). Figure 3. (a-q) LTG-s(Liear-Threshold-Gates)U for the combiatioal expressios(parts of D,D 1,D, C,R 1) (r) ve edge triggered D-F/F (s) +ve edge triggered D-F/F. 4

4 V. EXPLANATION As here we have cosidered that the exteral iputs (take as As, Bs, Cs Ds) are asychroous which ca occur ay time, we first pick up the iputs i the ve edge of our system clock with the ve edge triggered D-FF (which is also implemeted by SEEL architecture ad is show i fig. 3(s)). After gettig the iputs, they are processed by the combiatioal circuits to get the iputs of the iteral state D-FFs. Ad the at the +ve edge of our system clock, the correspodig state trasitio is made with the +ve edge triggered D-FFs (implemeted usig SEEL architecture ad is show i fig.3(r)).the RS lie(as show i fig.3(r)) ca be used ay time to reset the system such that it starts agai from state. The compoet values of the buffers used as show i fig.1(c) are calculated [9] ad give i the table II. These values are same for all the buffers used i this paper. TABLE II. ( ALL NOTATIONS ARE AS IN FIG. A(3)) V s C g C 1 C C 3 C 4 C b C l 16mV.5C.1C.5C.5C.1C 4.5C 9C The compoet values of the threshold gates used to implemet the combiatioal expressios as well as for the D flip-flops are give i the table V. I our logic circuit we have used C (the uit capacitor) =1aF=1-18 F givig logic 1 =16mv ad logic =mv. The switchig time-delay (calculated usig equatio (1) ad with the procedure give i [7]) ad the switchig eergy (calculated usig equatio (3) ad with the procedure give i [7]) for all the gates ad the flip-flops are tabulated i table VI. VI. RESULTS The fial circuit was formed usig the figs.3 (a-s) ad was tested for several sequece of iputs usig well established SIMON simulator ad it was foud workig satisfactorily. Some of the results are tabulated i table III. TABLE III. Seq. No. 1 RESULTS OF SIMULATION USING SIMON I/P O/P-s sequece C R 1 R 5 A s B s A s A s 1 B s B s B s C s 1 4 D s 1 1 VII. DELAY AND POWER ESTIMATION The maximum time delay & the maximum switchig eergy of all the gates ad the flip-flops are listed i table VI. A. Delay From the table VI ad otig that the critical path starts from the ve edge of the clock where the iputs are picked up ad eds o makig coffee out output lie o we get a total maximum delay=.68l(perror) Assumig Perror=the probability of o-occurrece of a tuel evet=1-8, this becomes=1.53s [1] B. PowerCosumptio From table VI ad otig that the maximum power cosumptio will be whe the system state chages from state 1 to state 6, ad assumig a clock frequecy of 5 MHz, we calculate the maximum power cosumptio =54.8 x 1-3 x 1.6x1-19 x 5 x 1 6 =4.pW. VIII. SAMPLE CALCULATION PROCEDURE FOR THE COMPONENT VALUES OF A BUFFERED LTG Takig the case of realizig the Boolea fuctio Y=C.Q which is writte as: Y=AND (C,Q ) =sg {C+Q -1.5} =sg(c+1-q -1.5) =sg(c-q -.5) As the gate is a buffered oe, so the LTG without the buffer has to be first realized with the expressio: Y=NAND (C.Q ) =sg (-C+Q +.5) Comparig this with the equatios (7) & (19) of ref. [7] we get Φ=-.5 uit ad C C 1 p = C p C 1 which represets a weight of 1 uit Agai as we have take [.1e/C] to represet the logic 1(=16mV with C=1aF), so we have: Φ= (-.5). C C 1 p.(.1e/c) Takig C =1C,C 1 p =.5C ad V b =16mV(logic 1) ad usig equatios (9) & () of ref. [7] we get C b =11C ad C p =11.5C which gives C 1 =.43C[from equatio (9)] Ad usig equatio (1) of ref. [7] we get C =9.57C IX. COMPARISON Here we preset a compariso (table IV) betwee SED implemetatio ad CMOS implemetatio of the whole circuit ad takig the same critical path. TABLE IV. parameters COMPARISON TABLE Usig SED-s (as calculated i colum VII) Usig cov. CMOS devices (Typical) Switchig delay time 1.53s 3s Total dyamic power 4.pW 6.7mW dissipatio (9) 41

5 X. DISCUSSION We have preseted a method to desig a sequetial circuit desig based o sigle electro logic systems usig Biary Decisio Diagram. We have take the coffee vedig machie as a example to show the details of the desig procedure. The results show sigificat time ad power savig over the covetioal CMOS circuits. Here we have igored the electro eergy quatizatio iside the coductors, the time take by a electro to tuel through a barrier ad the co-tuelig evets. We have also igored the operatioal error due to thermal agitatio. TABLE V. COMPONENT VALUES FOR THE THRESHOLD LOGIC GATES (ALL NOTATIONS ARE AS GIVEN IN FIG A(1 & ) TABLE VI. Tlg Of fig Φ C j p C 1 p C p C 3 C 1 C C 3 C 4 C b C o a -.5.1C.5C C C 9.57C b -.5.1C.5C.5C.5C.37C C 9.53C c -.5.1C.5C.5C.5C.37C C 9.53C d -.5.1C.5C.5C.5C.37C C 9.53C e -.5.1C.5C C C 9.57C f -.5.1C.5C.5C.5C.37C C 9.53C g C.5C.5C -.37C.37C C 9.6C h C.5C.5C.5C.35C.35C C 9.3C i -.5.1C.5C C C 9.57C j -.5.1C.5C.5C -.4C C 9.6C k C.5C - -.4C.4C - - 1C 9.C l -.5.1C.5C.5C -.34C.34C.34C C 8.98C m C.5C - -.4C.4C - - 1C 9.C C.5C - -.4C.4C - - 1C 9.C o C.5C - -.4C.4C - - 1C 9.C p -.5.1C C.5C.5C - 1.5C 8.5C q -.5.1C C.5C.5C.5C 1.5C 8C Fig r Tkg1.1C.5C - -.4C C 8.6C Tlg.1C 1C.5C.5C C 9C Tlg3 1.1C C.5C C 8C Tlg4 1.1C 1C.5C -.4C C 8.6C Tlg5.5.1C.5.5C C 1C Fig s Tlg1 1.1C C.5C C 8C Tlg 1.1C 1C.5C -.4C C 8.6C Tlg3.1C.5C - -.4C C 8.6C Tlg4.1C 1C.5C.5C C 9C MAXIMUM TIME DELAY & THE MAXIMUM SWITCHING ENERGY OF ALL THE GATES AND THE FLIP-FLOPS Gate/ FF Delay time(max)*[l(p error )] s Switchig eergy(max) (mev) Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig Fig

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