FPGA Implementation of SVPWM Technique for Seven-Phase VSI

Transcription

1 Iteratioal Joural of Electroics ad Electrical Egieerig Vol., No. 4, December, 203 FPGA Implemetatio of SVPWM Techique for Seve-Phase VSI G. Reukadevi Dept. of Electrical ad Electroics Egieerig, Jeppiaar Istitute of Techology, Sriperumbudur, Cheai K. Rajambal Dept. of Electrical ad Electroics Egieerig, Podicherry Egieerig College, Podicherry Abstract This paper presets the performace ivestigatio of FPGA implemetatio of SVPWM techique for seve-phase voltage source iverter (VSI). Seve-phase voltage source iverters are domiatly used to supply the seve-phase drives which are used for high power applicatios. I the SVPWM techique a large space vectors are detailed. A voltage source iverter with the proposed SVPWM is simulated i Matlab/Simulik. The performace of the 7-phase VSI is aalyzed i terms of fudametal voltage ad THD. I the proposed work, SVPWM algorithm is described i high-speed itegrated circuit hardware descriptio laguage codig ad implemeted i a XILINX Sparta 3A FPGA processor. The selectio of zero ad active space vector sequece are discussed ad the possibilities of realizatio o FPGA are aalyzed. Idex Terms FPGA, switchig techiques, THD, voltage source iverter I. INTRODUCTION Multi-phase VSI are becomig as a frot ed coverter for multi-phase drive applicatios, such as ship propulsio, electric aircraft, ad electric/hybrid electric vehicles etc. The multi-phase iverter circuit topology uses two switches coected i series as oe iverter pole. The umber of iverter poles depeds o umber of phases. For example, a three-phase iverter will have three iverter arms whereas a seve-phase iverter will have seve iverter arms. Covetioal PWM techique adapted for covetioal three phase VSI which ca be exteded for multi-phase VSI also. The most widely used PWM techiques for multi-phase iverters are the carrierbased SPWM ad SVPWM []-[8]. The SPWM schemes are more flexible ad easy to implemet []-[3]. However the output waveforms cotai more harmoics resultig i reduced fudametal compoet ad efficiecy. To achieve the better output voltage, the several space vector pulse width modulatio (SVPWM) techiques are discussed. The SVPWM techique for the multi phase iductio machie has bee widely reported i [4]-[8]. SVPWM techique for Asymmetrical sixmauscript received August 5, 203; revised December 23, Egieerig ad Techology Publishig doi: /ijeee phase ad five-phase VSI are discussed i [9]-[6]. These issues are extesio of three phase VSI. The SVPWM techique with seve phase voltage source iverter is discussed i [7], [8]. I this paper differet combiatios of switchig techiques are aalyzed. Oly limited issues are available for SVPWM techique used i digital platform. May issues related to SVPWM techique is implemeted usig the DSP platform. The DSP executes istructios sequetially ad it requires more time for processig. The ew software of fieldprogrammable gate array (FPGA) is compute istructios parallel ad it requires less time to execute [9]-[22]. The FPGA comprises thousads of logic gates, some of which are grouped together as a cofigurable logic block (CLB) to simplify higher level circuit desig. The itercoectios of the gates are defied by exteral RAM or ROM. The simplicity ad programmability of FPGA desig as the most favorable choice for prototypig a ASIC. The advet of FPGA techology has eabled rapid prototypig of digital systems. I this paper FPGA implemetatio of SVPWM techique for seve-phase VSI is developed. A attempt is made i this paper for various simulatio results are obtaied for seve-phase iverter at differet modulatio idices for both i Matlab/Simulik ad FPGA eviromet. The effectiveess of this method is ivestigated i terms of percetage icrease of fudametal voltage ad THD. II. POWER CIRCUIT OF SEVEN-PHASE VSI The power circuit of seve-phase VSI is show i Fig.. The circuit cosists of 7 half-bridges, which are mutually displaced by 2π/ degrees to geerate the 7phase voltage waves. The iput dc supply is obtaied from a sigle phase or 3-phase utility power supply through a diode-bridge rectifier. The voltages Va, Vb, Vc, Vd, Ve, Vf ad Vg are the iverter pole voltages coected to load termials. It is see that the switchig states of each pole should be combied with each other pole to create the required 7-phase output voltages. The phase voltages of the iverter ad modulatio idex are as give i the expressios () & (2). The Modulatio Idex (MI) is the cotrol parameter of the iverter which adjusts the

2 Iteratioal Joural of Electroics ad Electrical Egieerig Vol., No. 4, December, 203 output voltage of the iverter accordig to the amplitude of the referece waveform. It is defied as the ratio of magitude of the referece to magitude of the carrier sigals. Figure 2. d-q plae of seve-phase VSI Figure. Power circuit diagram of seve-phase VSI Va (Vb Vc Vd Ve V f Vb (Va Vc Vd Ve V f Vc (Va Vb Vd Ve V f Vd (Va Vb Vc Ve V f Ve (Va Vb Vc Vd V f V f (Va Vb Vc Vd Ve Vg (Va Vb Vc Vd Ve VaN VbN Vc N VdN Ve N V fn VgN M Vref Vtri where α=2*pi/ Thus d-q plae ca be visualized as beig composed of three differet space vectors, each plae ca be divided ito 4 sectors. I the proposed work, a large (outer-most) space vector is cosidered. This is the simplest extesio of a three-phase SVPWM ad oly the outer most plae is cosidered i order to geerate output voltages, based o the referece space vector. The large space vectors are discussed detailed i the followig sectios. () IV. I this sectio, the outer-most of large space vectors i d q plae is cosidered. The iput referece voltage vector is sythesised from two active vectors ad zero space vectors respectively. The switchig times are calculated by usig the referece space vector Vref, magitude of the larger plae ad sector (sec) umber respectively. The switchig time sequece of active ad zero space voltage vectors are derived from the expressios (4) & (5). Vf ) Peak value of V 0.5Vdc (2) The d-q plae for seve-phase VSI, SVPWM usig large space vectors ad FPGA implemetatio of SVPWM algorithm are discussed detail i the followig sectios. III. D-Q tal tbl PLANE FOR SEVEN-PHASE VSI I a seve phase system the iverter space vectors are seve-dimesioal space. A space ca be decomposed ito three two-dimesioal sub-spaces (d- q, d2-q2 ad d3-q3) ad oe sigle dimesioal sub space (zerosequece). The problems i the d2-q2, d3-q3 ad zero subspaces are extesively reported i [5]. Therefore, i order to geerate pure siusoidal output voltages, SVPWM techique must sythesize fudametal compoet i the d-q plae. I the proposed work, oly the d-q plae for differet space vector is cosidered. Fig. 2 shows the d-q plae for seve-phase VSI. I a seve-phase system the iverter space vectors are twodimesioal space as expressed i (3). Vref cos si cos 2 cos3 cos 4 cos5 cos6 si 2 si3 si 4 si5 si Egieerig ad Techology Publishig SVPWM USING LARGE SPACE VECTORS V ref si(sec / 7 ) V l si / 7 ts V ref si( (sec ) / 7) V l si / 7 t0 / 2(ts tal tbl ) ts (4) (5) Fig. 3 shows the phasor diagram for large space vectors of seve-phase VSI. Here, tal ad tbl correspod to times of applicatio of large space vectors. I sector, tal is the time of applicatio of the voltage space vector V97, while tbl is the time of applicatio of the voltage space vector V3. t0 ad t27 is the time of applicatio of zero voltage vectors of V0 ad V27. For odd sectors, the sequece of the switchig period is (t0 tal tbl t27 tbl tal t0 ), while i eve sectors it is (t0 tbl tal t27 tal tbl t0) respectively. The maximum possible fudametal peak voltage of large space vector is Vmax=0.642Vdc. The switchig time sequece for large space vectors of sector is show i Fig. 4. It is see that i oe complete full cycle (ts) has (3) 276

3 Iteratioal Joural of Electroics ad Electrical Egieerig Vol., No. 4, December, 203 divided ito two half cycles (t s /2). I the first half of the switchig time sequece is zero space vector (t 0 ), two active space vectors (t al t bl ) ad zero space vector (t 27 ) respectively. The secod half of the switchig time sequece is a mirror image of the first cycle. Figure 3. Phasor diagram of large space vector (sector ) Determie the 7-phase referece voltages with symmetrical phase displacemet. Trasform 7-phase to 2-phase. Fid the ormalised referece vector from the 2-phase trasformatio. Idetify the sectors i d -q plae. Determie the switchig time calculatio for differet space vectors (t al, t bl, t 0 ). Fid the switchig time sequece for odd ad eve space vector for large space vectors. Determie the modulatig sigals. Determie the high frequecy carrier sigals (0 KHz). Compare modulatig sigals with high frequecy carrier sigals. Tur o upper switches if mod car, tur o lower switches if mod car. TABLE I. Product Versio SOFTWARE VERSION AND TARGET DEVICE ISE:2. (WebPack) - M.53d Target Family Target Device Target Package Sparta-3A DSP xc3sd800a fg676 Target speed -4 Tool Flow Sythesis tool Simulator ISE XST (VHDL/Verilog) Modelsim-SE VHDL Figure 4. Switchig time sequece of large space vectors (sector ) V. FPGA IMPLEMENTATION OF SVPWM ALGORITHM The SVPWM algorithm for 7-phase VSI has bee implemeted i FPGA. Table I shows the software versio ad target device utilized for this algorithm. This FPGA, belogs to the Sparta-3A DSP family from XILINX, has the basic Cofigurable Logic Blocks (CLBs) ad flexible Look-Up Tables (LUTs). CLBs has high data storage capacity ad hece perform a wide variety of logical fuctios. FPGA allows a great degree of freedom i the implemetatio of SVPWM algorithm ad reduces the total amout of hardware eeded ad keeps the fial cost at a reasoable poit. The istructios are doe with a 20-MHz clock, which is sufficiet to achieve a realtime operatio of the algorithm. The geeral high speed itegrated circuit hardware descriptio laguage (VHDL) is employed for SVPWM algorithm codig. The steps ivolved i FPGA implemetatio of SVPWM algorithm are listed below: VI. SIMULATION RESULTS The seve-phase iverter is simulated with the above said switchig schemes ad the results are observed. The switchig frequecy of the VSI is chose as 0 khz ad the fudametal frequecy is set to 50 Hz. The simulatio parameter of seve-phase VSI is show i appedix. The simulatio results of the SVPWM, FPGA implemetatio of SVPWM are discussed i the followig sectios for differet modulatio idices. A. Matlab/Simulik Simulatio Results for SVPWM Techique with Seve-Phase VSI The 7-phase VSIs is simulated with the pulses obtaied by SVPWM techique. Fig. 5 shows the switchig time period of t al, t bl ad t o respectively. Fig. 6 shows the resultat modulatig sigal for a modulatio idex of The output phase voltage ad its spectrum are show i Fig. 7. It is see that the output fudametal rms value is p.u. (0.633 p.u. peak) ad THD is 47.08%. The adjacet ad o-adjacet lie-to-lie voltages are show i Fig. 8 to Fig. 0. From Fig. 8 it see that the adjacet lie-to-lie voltage (a to b) rms is p.u. ( p.u. peak) ad THD is 94.52%. The 203 Egieerig ad Techology Publishig 277

4 Iteratioal Joural of Electroics ad Electrical Egieerig Vol., No. 4, December, 203 o-adjacet lie-to-lie voltages (a to c) rms is p.u. ( p.u. peak) ad THD is 40.72%. The oadjacet lie-to-lie voltages (a to d) rms is p.u. (.234 p.u. peak) ad THD is 35.32% respectively. From the simulatio results the seve phase VSI has three pairs of lie-to-lie voltages. It is see that the maximum lieto-lie voltage of.9497vp is obtaied i the oadjacet side ( a to d). Figure 8. Adjacet lie voltage (a to b) ad its spectrum for MI-0.85 Figure 5. Time period for tal, tbl ad to. Figure 9. No-adjacet lie voltage (a to c) ad its spectrum for MI0.85 Figure 6. Resultat modulatig sigal for seve phase VSI Figure 0. No-adjacet lie voltage (a to d) ad its spectrum for MI0.85 B. Simulatio Results of SVPWM i FPGA Fig. shows the 7-phase VSI is simulated with the SVPWM pulses obtaied by FPGA eviromet. Fig. (a) shows the results switchig time period of tal, tbl ad to respectively. Fig. (b) shows the resultat modulatig sigal for a 7-phase VSI. Fig. (c) shows the switchig pulses obtaied from FPGA. I the real time implemetatio the switchig pulses are used to activate the 7-phase VSI. Figure 7. Phase voltage ad its spectrum for MI Egieerig ad Techology Publishig 278

5 Iteratioal Joural of Electroics ad Electrical Egieerig Vol., No. 4, December, 203 C. Compariso of Fudametal Voltage ad THD for Differet MI Table II shows the percetage icrease of fudametal voltage (phase voltage ad lie-to-lie voltage) for differet modulatio idices. It is oted that the fudametal voltage is margially high ad also the icrease i voltage reduces with decreasig modulatio idex. The o-adjacet lie-to-lie voltage ad phase voltage maximum of rms ad rms is achieved for modulatio idex is It is see that the THD reductio is observed for icreasig modulatio idex. A miimum THD of 35.32% ad 47.78% is obtaied at o-adjacet lie-to-lie voltage ad phase voltage respectively. Fig. 2 shows the variatio of THD ad fudametal voltage for differet modulatio idex is 0.2 to (a) (b) (c) Figure 2. Fudametal voltage ad THD for differet MI Figure. FPGA implemetatio SVPWM results TABLE II. INCREASE IN FUNDAMENTAL VOLTAGE AND REDUCED THD FOR DIFFERENT MI Sl.o MI Vp (Phase voltage) VL (Adjacet lie voltage) VL (No-adjacet lie voltage of a to c) VL (No-adjacet lie voltage of a to d) THD i % THD i % THD i % THD i % VII. is easily implemeted i the SPARTAN-3A FPGA processor. Based o the results FPGA ca fuctio well with differet space vectors. CONCLUSION This paper presets the FPGA implemetatio of SVPWM switchig techique for seve-phase VSI. From the simulatio results the fudametal voltage is margially high ad also the icrease i voltage reduces with decreasig modulatio idex. The o-adjacet lieto-lie voltage ad phase voltage maximum of rms ad rms is achieved for modulatio idex is The THD reductio is observed for icreasig modulatio idex. A miimum THD of 35.32% ad 47.78% is obtaied at o-adjacet lie-to-lie voltage ad phase voltage respectively. The SVPWM techique 203 Egieerig ad Techology Publishig APPENDIX PARAMETERS OF THE 7-PHASE VSI Parameters 279 Values DC voltage p.u Fudametal frequecy Switchig frequecy Modulatio idex(mi) 50Hz 0KHz 0.2 to 0.85 Number of phases() 7

6 Iteratioal Joural of Electroics ad Electrical Egieerig Vol., No. 4, December, 203 REFERENCES [] D. Holmes ad T. A. Lipo, Pulse width modulatio for power coverters-priciples ad practice, i IEEE Press Series o Power Egieerig, Piscataway, NJ, USA: Joh Wiley ad Sos, [2] G. Reukadevi ad K. Rajambal, Novel carrier-based PWM techique for -phase VSI, Iteratioal Joural of Eergy Techologies ad Policy, pp. -9, 20. [3] G. Reukadevi ad K. Rajambal, Compariso of differet PWM schemes for -phase VSI, i Proc. Iteratioal Coferece o Advaces I Egieerig, Sciece Ad Maagemet, March 30-3, 202, pp [4] G. K. Sigh, Multi-phase iductio machie drive research A survey, Electric Power System Research, vol. 6, pp , [5] G. Reukadevi ad K. Rajambal, Geeralized model of multiphase iductio motor drive usig Matlab/Simulik, i Proc. Iteratioal IEEE PES Coferece Iovative Smart Grid Techologies, Kerala-Idia, 20. [6] E. Levi, R. Bojoi, F. Profumo, H. A. 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Reukadevi received her Bachelor of Egieerig i Electrical Egieerig from The Istitutio of Egieers, Idia i Her Master of techology i Electrical Drives ad Cotrol from Podicherry Egieerig College, Podicherry, i She is pursuig Ph.D i Podicherry Egieerig College, Podicherry, Idia. Curretly she is workig as Assistat professor i the Departmet of Electrical ad Electroics i Jeppiaar Istitute of Techology, Sriperumbudur, Cheai, Idia. Her field of iterest is Power Electroics, Drives ad Cotrol, Modelig, Reewable Eergy Sources ad Cotrol Systems. K. Rajambal received her Bachelor of Egieerig i Electrical & Electroics, Master of Egieerig i power electroics ad Ph.D i Wid Eergy Systems i 99, 993 ad 2005 respectively from Aa Uiversity, Cheai, Idia. She is workig as Professor i the Departmet of Electrical ad Electroics i Podicherry Egieerig College, Podicherry, Idia. Her area of iterest icludes i the fields of Wid Eergy systems ad Photovoltaic Cell, Power Coverter such as DC-DC Coverters, AC-AC Coverters ad Multilevel Iverters with soft switchig PWM schemes ad power electroics applicatio towards power systems. She has published papers i atioal, iteratioal cofereces ad jourals i the field of reewable eergy sources ad power electroics. 203 Egieerig ad Techology Publishig 280